Array substrate, display panel, display device and driving method
By designing alternating colored pixel electrodes in the array substrate of the liquid crystal display panel and employing HSR and DLG driving technologies, the limitations of scanning frequency and refresh rate are solved, resulting in more efficient display effects and lower power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUZHOU BOE OPTOELECTRONICS TECH CO LTD
- Filing Date
- 2024-09-23
- Publication Date
- 2026-06-30
AI Technical Summary
Existing LCD panels have limitations in scanning frequency and refresh rate, making it impossible to achieve efficient frequency multiplication, resulting in choppy display and lag.
By designing multiple pixel electrodes arranged alternately in the array substrate, the light emitted by adjacent pixel electrodes on the same data line is ensured to be the same color. HSR and DLG driving technologies are adopted to enable adjacent rows of gate lines to share the data line signal, thereby realizing frame flipping and frequency doubling driving.
The increased scanning frequency and refresh rate of the display panel improved image smoothness and brightness uniformity, while reducing power consumption and heat generation of integrated circuit chips, thus enhancing product competitiveness.
Smart Images
Figure CN118963031B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more particularly to an array substrate, a display panel, a display device, and a driving method. Background Technology
[0002] Liquid crystal display panels are a rapidly developing high-tech field in recent years. Due to their advantages such as being thinner and lighter, having low radiation, high contrast, fast response speed, and low energy consumption, they have been widely used in flat panel display devices. Summary of the Invention
[0003] This invention provides an array substrate, a display panel, a display device, and a driving method. The array substrate includes:
[0004] Substrate;
[0005] Multiple grid lines, the multiple grid lines extending along a first direction;
[0006] Multiple data lines, the multiple data lines extending along a second direction;
[0007] Multiple pixel electrode rows extend along a first direction and are arranged along a second direction; at least one pixel electrode row includes: multiple pixel electrodes with different emitted light colors; the pixel electrodes are located in the region formed by the intersection of the gate line and the data line.
[0008] Multiple transistors, wherein the pixel electrodes are electrically connected to the gate line and the data line through the transistors, and the multiple pixel electrodes electrically connected to the same data line through the transistors are alternately located on different sides of the data line;
[0009] Wherein, two pixel electrodes located in at least partially adjacent rows of pixel electrodes and electrically connected to the same data line via the transistor emit light of the same color.
[0010] In one possible implementation, in adjacent rows of pixel electrodes, the pixel electrodes with the same emitted light color are staggered.
[0011] In one possible implementation, the minimum misalignment width of pixel electrodes with the same light-emitting color in adjacent rows of pixel electrodes is the same as the spacing between two adjacent pixel electrodes in the same row of pixel electrodes.
[0012] In one possible implementation, any two pixel electrodes electrically connected to the same data line emit the same color light.
[0013] In one possible implementation, the array substrate includes: a plurality of first pixel electrode repeating units; the first pixel repeating unit includes: a first pixel electrode, a second pixel electrode, a third pixel electrode, a fourth pixel electrode, a fifth pixel electrode, and a sixth pixel electrode;
[0014] Wherein, the first pixel electrode is electrically connected to the Nth gate line and the Mth data line via the transistor; the second pixel electrode is electrically connected to the Nth gate line and the (M+1)th data line via the transistor; the third pixel electrode is electrically connected to the Nth gate line and the (M+2)th data line via the transistor; the fourth pixel electrode is electrically connected to the (N+1)th gate line and the (M+1)th data line via the transistor; the fifth pixel electrode is electrically connected to the (N+1)th gate line and the (M+2)th data line via the transistor; and the sixth pixel electrode is electrically connected to the (N+1)th gate line and the (M+3)th data line via the transistor; where N and M represent positive integers;
[0015] The first pixel electrode and the sixth pixel electrode emit the same light color; the second pixel electrode and the fourth pixel electrode emit the same light color; the third pixel electrode and the fifth pixel electrode emit the same light color.
[0016] In one possible implementation, the array substrate includes: a plurality of pixel electrode rows extending along the first direction and arranged along the second direction; at least one of the plurality of pixel electrode rows includes: two of the pixel electrode rows;
[0017] The two pixel electrodes that are electrically connected to the same data line via the transistor and are located in the same pixel electrode row group emit light of the same color.
[0018] In one possible implementation, two pixel electrodes that are electrically connected to the same data line via the transistor and are located in adjacent pixel electrode rows emit different colors of light.
[0019] In one possible implementation, the array substrate includes: a plurality of second pixel electrode repeating units; the second pixel repeating unit includes: a seventh pixel electrode, an eighth pixel electrode, a ninth pixel electrode, a tenth pixel electrode, an eleventh pixel electrode, a twelfth pixel electrode, a thirteenth pixel electrode, a fourteenth pixel electrode, a fifteenth pixel electrode, a sixteenth pixel electrode, a seventeenth pixel electrode, an eighteenth pixel electrode, a nineteenth pixel electrode, a twentieth pixel electrode, a twenty-first pixel electrode, a twenty-second pixel electrode, a twenty-third pixel electrode, a twenty-fourth pixel electrode, and a twenty-fifth pixel electrode;
[0020] Specifically, the seventh pixel electrode is electrically connected to the Jth gate line and the Kth data line via the transistor; the eighth pixel electrode is electrically connected to the Jth gate line and the (K+1)th data line via the transistor; the ninth pixel electrode is electrically connected to the Jth gate line and the (K+2)th data line via the transistor; the tenth pixel electrode is electrically connected to the (J+1)th gate line and the (K+1)th data line via the transistor; and the eleventh pixel electrode is electrically connected to the (J+1)th gate line via the transistor. The data line K+2; the twelfth pixel electrode is electrically connected to the gate line J+1 and the data line K+3 via the transistor; the thirteenth pixel electrode is electrically connected to the gate line J+2 and the data line K via the transistor; the fourteenth pixel electrode is electrically connected to the gate line J+2 and the data line K+1 via the transistor; the fifteenth pixel electrode is electrically connected to the gate line J+2 and the data line K+2 via the transistor; the sixteenth pixel electrode is electrically connected to the data line K+3 via the transistor. The transistor is electrically connected to the (J+3)th gate line and the (K+1)th data line; the seventeenth pixel electrode is electrically connected to the (J+3)th gate line and the (K+2)th data line via the transistor; the eighteenth pixel electrode is electrically connected to the (J+3)th gate line and the (K+3)th data line via the transistor; the nineteenth pixel electrode is electrically connected to the (J+4)th gate line and the (K)th data line via the transistor; the twentieth pixel electrode is electrically connected to the (J+4)th gate line and the (K+1)th data line via the transistor. The data lines; the 21st pixel electrode is electrically connected to the (J+4)th gate line and the (K+2)th data line via the transistor; the 22nd pixel electrode is electrically connected to the (J+5)th gate line and the (K+1)th data line via the transistor; the 23rd pixel electrode is electrically connected to the (J+5)th gate line and the (K+2)th data line via the transistor; the 24th pixel electrode is electrically connected to the (J+5)th gate line and the (K+3)th data line via the transistor; wherein, J and K represent positive integers;
[0021] The seventh, twelfth, fourteenth, sixteenth, twenty-first, and twenty-third pixel electrodes emit the same light color; the eighth, tenth, fifteenth, seventeenth, nineteenth, and twenty-fourth pixel electrodes emit the same light color; and the ninth, eleventh, thirteenth, eighteenth, twentieth, and twenty-second pixel electrodes emit the same light color.
[0022] In one possible implementation, the length of the pixel electrode in the first direction is greater than its length in the second direction.
[0023] In one possible implementation, the length of the pixel electrode in the first direction is less than its length in the second direction.
[0024] Based on the same inventive concept, this disclosure also provides a display panel, which includes the array substrate as provided in the embodiments of this disclosure, and further includes a counter substrate disposed opposite to the counter substrate.
[0025] Based on the same inventive concept, embodiments of this disclosure also provide a display device, which includes the display panel as described in embodiments of this disclosure.
[0026] Based on the same inventive concept, embodiments of this disclosure also provide a driving method for driving an array substrate as described in embodiments of this disclosure, wherein the driving method includes:
[0027] The data lines are controlled to sequentially load data signals;
[0028] During the period when the same data signal is loaded on the data line, at least two adjacent gate lines are controlled to open so that two pixel electrodes electrically connected to the same data line through the transistor and located in adjacent rows of pixel electrodes are loaded with the same data signal.
[0029] In one possible implementation, controlling at least two adjacent gate lines to open during the period when the same data signal is loaded on the data lines includes:
[0030] Controlling the nth gate line to open, and controlling the (n+1)th gate line to open, wherein the (n+1)th gate line has a first time period that opens simultaneously with the nth gate line, and a second time period that closes after the nth gate line;
[0031] During the first time period and the second time period, a first data signal is loaded onto the m-th data line, so that the two pixel electrodes electrically connected to the n-th, n+1-th gate lines and the m-th data line are all loaded with the first data signal, where n and m represent positive integers.
[0032] In one possible implementation, controlling at least two adjacent gate lines to open during the time period when the same data signal is loaded on the data lines includes:
[0033] Control the j-th and j+1-th gate lines to open simultaneously, wherein the j+1-th gate line has a third time period that opens simultaneously with the j-th gate line;
[0034] In the third time period, a second data signal is loaded onto the k-th data line so that the two pixel electrodes electrically connected to the j-th, j+1-th, and k-th data lines are all loaded with the second data signal, where j represents an odd or even number and k represents a positive integer. Attached Figure Description
[0035] Figure 1A This is one of the pixel architecture schematic diagrams provided in the embodiments of the present invention;
[0036] Figure 1B This is a second schematic diagram of the pixel architecture provided in an embodiment of the present invention;
[0037] Figure 2A and Figure 1A A schematic diagram of the array substrate layout corresponding to the pixel architecture shown;
[0038] Figure 2B for Figure 2A Film diagram of the layer containing the common electrode;
[0039] Figure 2C for Figure 2A Film layer diagram of the layer containing the middle gate line;
[0040] Figure 2D for Figure 2A A diagram of the film layer containing the active layer;
[0041] Figure 2E for Figure 2A Film layer diagram of the data cable;
[0042] Figure 2F for Figure 2A Film layer diagram of the middle pixel electrode;
[0043] Figure 3 This is the third schematic diagram of the pixel architecture provided in the embodiment of the present invention;
[0044] Figure 4 The fourth schematic diagram of the pixel architecture provided in the embodiment of the present invention;
[0045] Figure 5A This is a schematic diagram of the sub-pixel arrangement corresponding to the three-gate pixel architecture provided in an embodiment of the present invention;
[0046] Figure 5B for Figure 5A A magnified diagram of one pixel;
[0047] Figure 6A This is a schematic diagram of the sub-pixel arrangement corresponding to the single-gate pixel architecture provided in the embodiments of the present invention;
[0048] Figure 6Bfor Figure 6A A magnified diagram of one pixel;
[0049] Figure 7 A timing diagram of the HSR mode provided in an embodiment of the present invention;
[0050] Figure 8 Timing diagram of DLG mode provided in an embodiment of the present invention;
[0051] Figure 9 This is a schematic diagram of the driving method for an array substrate provided in an embodiment of the present invention. Detailed Implementation
[0052] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0053] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0054] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.
[0055] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.
[0056] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.
[0057] See Figure 1A , Figure 1B , Figures 2A-2F , Figure 3 and Figure 4 As shown, where, Figure 1A for Figure 2A Equivalent pixel architecture diagram, Figure 2B for Figure 2A Film diagram of the layer containing the common electrode; Figure 2C for Figure 2A Film layer diagram of the layer containing the middle gate line; Figure 2D for Figure 2A A diagram of the film layer containing the active layer; Figure 2E for Figure 2A Film layer diagram of the data cable; Figure 2F for Figure 2A A film layer diagram of the middle pixel electrode; an embodiment of the present invention provides an array substrate, comprising:
[0058] Substrate;
[0059] Multiple grid lines G extend along a first direction X;
[0060] Multiple data lines D extend along the second direction Y;
[0061] Multiple pixel electrode rows P00 extend along a first direction X and are arranged along a second direction Y; at least one pixel electrode row P00 includes: multiple pixel electrodes P with different emitted light colors; the pixel electrode P is located in the area formed by the intersection of the gate line G and the data line D.
[0062] Multiple transistors T, pixel electrodes P are electrically connected to gate line G and data line D through transistors T, and multiple pixel electrodes P that are electrically connected to the same data line D through transistors T are alternately located on different sides of data line D; for example, see Figure 1A As shown, for the second data line D(M+1) from left to right, multiple pixel electrodes P electrically connected to the second data line D(M+1) are alternately electrically connected to the second data line D(M+1) from left to right. Specifically, as shown... Figure 1A In the top-to-bottom direction, the first pixel electrode P (i.e., the green pixel electrode G that emits green light) is electrically connected to the right side of the second data line D(M+1), the second pixel electrode P (i.e., the green pixel electrode G that emits green light) is electrically connected to the left side of the second data line D(M+1), the third pixel electrode P (i.e., the green pixel electrode G that emits green light) is electrically connected to the right side of the second data line D(M+1), the fourth pixel electrode P (i.e., the green pixel electrode G that emits green light) is electrically connected to the left side of the second data line D(M+1), the fifth pixel electrode P (i.e., the green pixel electrode G that emits green light) is electrically connected to the right side of the second data line D(M+1), and the sixth pixel electrode P (i.e., the green pixel electrode G that emits green light) is electrically connected to the left side of the second data line D(M+1).
[0063] Specifically, two pixel electrodes P located in at least partially adjacent pixel electrode rows P00 and electrically connected to the same data line D via transistor T have the same emitted light color. The emitted light color of pixel electrode P can be understood as the emitted light color of the area where pixel electrode P is located when the display panel is powered on. For example, when the display panel is a liquid crystal display panel, the emitted light color of pixel electrode P can be the color emitted by the backlight through the color resist in the area where pixel electrode P is located.
[0064] In this embodiment, multiple pixel electrodes P electrically connected to the same data line D via transistor T are alternately located on different sides of data line D. Moreover, two pixel electrodes P located in at least partially adjacent pixel electrode rows P00 and electrically connected to the same data line D via transistor T emit the same light color. Therefore, during display driving, two pixel electrodes P in adjacent pixel electrode rows P00 can be loaded with the data signal of the same data line D. That is, two adjacent rows of gate lines G can share the data signal of data line D. Frequency multiplication driving can be applied to increase the scanning frequency of the display panel, making the display panel smoother and more lag-free during display, improving the specifications of the display device (e.g., 60Hz→120Hz), and enhancing product competitiveness.
[0065] In this embodiment, multiple pixel electrodes P are electrically connected to the same data line D via transistor T, and are alternately located on different sides of the data line D. That is, the display panel provided in this embodiment has a Z-shaped structure. This pixel structure can achieve pixel-level dot flipping by using frame flipping, which can improve the uniformity of panel brightness. Moreover, frame flipping means that within a frame, the same data line is either all positive or all negative signals. Compared with dot flipping, frame flipping has the advantages of low power consumption and less heat generation of integrated circuit chips (ICs). The embodiments of this invention can achieve the effect of dot flipping by frame flipping, which can improve the uniformity of display panel brightness, and also make the display panel have the advantages of low power consumption and less heat generation of integrated circuit chips (ICs).
[0066] The display panel provided in this disclosure can employ Hardware SuperResolution (HSR) and / or Dual Line Gate (DLG) technology. Without altering the original hardware and chip computing power, the refresh rate of the display panel can be increased by multiplying the gate drive circuit signal. For example, a 60Hz FHD product with a specification of 1920*1080*60Hz can be improved to 1920*540*120Hz; a 120Hz 4K product with a specification of 3840*2160*120Hz can be improved to 3840*1080*240Hz.
[0067] HSR drive mode allows multiple scan lines to share data output. To ensure adjacent scan lines (gate lines G) can share data on data line D, the pixel architecture requires one data line from each adjacent line to be connected to a sub-pixel of the same color. This enables correct display of R, G, B monochrome images and the correct overall image display function. DLG mode uses two scan lines (gate lines G) with identical timing, simultaneously enabled, and sharing data signals. Therefore, one data line from every two lines needs to be connected to a sub-pixel of the same color.
[0068] like Figure 7 As shown, the data signal "1" will be applied to the nth gate line and the (n+1)th gate line; Figure 1B Taking the pixel architecture shown as an example, it can be done through, as Figure 7The timing shown implements HSR driving. For example, when N=n and M=m, the nth gate line is controlled to open. The effective time periods of the nth gate line include: the initial time period t0 and the first time period t1. The initial time period t0 can be the pre-charge duration. For example, taking G(n+4) as an example, the initial time period t0 can pre-charge "1", "2", "2". The liquid crystal will also deflect during the initial time period t0, but this stage is not the required data. Therefore, it can be called the pre-charge period, which can make the liquid crystal deflect in advance. When the first time period t1 arrives, the pixel electrode will be charged to the required data "3". That is, the data pre-charged during the initial time period t0 can be covered by the data during the first time period t1. During the first time period t1, a data signal with content such as "1" can be loaded to the pixel electrode P through the data line D. Since the scanning frequency of the gate line is doubled, when the data line is still loading a data signal with content "1", the (n+1)th gate line has also been opened. Therefore, the data signal with content "1" can also be loaded to the pixel electrode controlled by the (n+1)th gate line.
[0069] The difference between DLG mode and HSR mode is that two adjacent gate lines are turned on simultaneously. Therefore, the same data signal can be applied to the pixel electrodes controlled by two gate lines at the same time.
[0070] In one possible implementation, see Figure 1B , Figure 2A , Figure 3 and Figure 5A As shown, the length b1 of the pixel electrode P in the first direction X is greater than the length b2 in the second direction Y. That is, in this embodiment of the present disclosure, the display panel can be a display panel with a triple gate pixel architecture, which can reduce the amount of chip-on-film (COF) used and reduce the cost of the display panel. Moreover, in the conventional triple gate pixel architecture, the pixel electrodes located in two adjacent pixel electrode rows and electrically connected to the same data line emit different colors of light, which cannot achieve frequency doubling drive. However, in this embodiment of the present disclosure, for the triple gate pixel architecture display panel, for each data line D, every two adjacent pixel electrode rows are connected to sub-pixels of the same color, which can achieve frequency doubling drive mode (HSR mode and / or DLG mode). This gives the triple gate pixel architecture display panel a low cost advantage, while also making the picture smoother and delay-free during the display process, further enhancing the competitiveness of the display product.
[0071] In one possible implementation, see Figure 4 and Figure 6AAs shown, the length b1 of the pixel electrode P in the first direction X is less than the length b2 in the second direction Y. That is, in this embodiment of the present disclosure, the display panel can also be a display panel with a single-gate pixel architecture. In a conventional single-gate pixel architecture, the pixel electrodes located in two adjacent pixel electrode rows and electrically connected to the same data line emit different colors of light, which cannot achieve frequency doubling drive. However, in this embodiment of the present disclosure, for a display panel with a single-gate pixel architecture, for each data line D, every two adjacent pixel electrode rows are connected to sub-pixels of the same color, which can realize the frequency doubling drive mode (HSR mode and / or DLG mode), which can make the picture smoother and without delay during the display process, and further enhance the competitiveness of the display product.
[0072] It should be noted that, Figure 3 and Figure 4 ,or, Figure 5A and Figure 6A The main difference lies in the Triple Gate and Single Gate architectures, although Figure 3 and Figure 4 The pixel architecture shown is the same in terms of pixel connection and sorting, but when combined with different display panel architectures, it will be a different pixel design. That is, the total area and resolution of the display area AA are the same, but the number of grid lines and data lines and the amount of COF are different. Figure 3 or Figure 5A In the Triple Gate architecture shown, the second direction Y (i.e., vertical) BGR is one pixel, the number of gate lines G (and sub-pixels in the second direction Y) is 1080*3, and the number of data lines D (and sub-pixels in the first direction X) is 1920. Therefore, the number of COFs used per unit is 1920 / 960 = 2. The total width of the display area AA along the first direction X is b1*1920, and the total width of the display area AA along the second direction Y is b2*1080*3. Figure 4 or Figure 6A In the Single Gate architecture shown: the first direction X (i.e., the horizontal direction) BGR is one pixel, the number of data lines D (and sub-pixels on the first direction X) is 1920*3, and the number of gate lines G (and sub-pixels on the second direction Y) is 1080; therefore, the number of COFs used per unit is 1920*3 / 960 = 6, the total width of the display area AA along the first direction X is b1*1920*3, and the total width of the display area AA along the second direction Y is b2*1080.
[0073] In one possible implementation, see Figure 5B As shown, where, Figure 5B for Figure 5A A magnified diagram of a pixel, where b1 = 3b2, shows that three sub-pixels can form a square pixel; in one possible implementation, see [link to implementation details]. Figure 6B As shown, where, Figure 6B for Figure 6A A magnified diagram of a pixel, b2 = 3b1, where three sub-pixels can form a square pixel.
[0074] In one possible implementation, see Figure 1A , Figure 3 and Figure 4 As shown, in adjacent pixel electrode rows P00, pixel electrodes P with the same emitted light color are staggered. For example, as... Figure 1A In the first pixel electrode row P100 and the second pixel electrode row P00 from top to bottom, the green pixel electrodes G that emit green light are misaligned and not located in the same column. That is, the green pixel electrode G that emits green light in the first pixel electrode row P100 and the red pixel electrode R that is adjacent to the green pixel electrode G and emits red light in the second pixel electrode row P00 are located in the same column.
[0075] In one possible implementation, see Figure 1B As shown, in adjacent pixel electrode rows P00, the minimum misalignment width a1 of pixel electrodes P with the same emitted light color is the same as the spacing a2 between two adjacent pixel electrodes P in the same pixel electrode row P00. Compared with conventional technology, in this embodiment, in the horizontal direction of each pixel electrode row, sub-pixels of the same color are shifted by one sub-pixel relative to the previous sub-pixel row, forming a new pixel arrangement. Each pixel still retains sub-pixels of the three primary colors R, G, and B, achieving a sub-pixel ratio of 1:1:1 within the pixel, maintaining the same resolution as the conventional structure, but enabling the application of HSR (High-Speed Reduction) mode, thereby improving the refresh rate of the display panel.
[0076] In one possible implementation, see Figure 1B As shown, the array substrate includes: a plurality of first pixel electrode repeating units PA; the first pixel repeating unit PA includes: a first pixel electrode P1, a second pixel electrode P2, a third pixel electrode P3, a fourth pixel electrode P4, a fifth pixel electrode P5 and a sixth pixel electrode P6;
[0077] Wherein, the first pixel electrode P1 is electrically connected to the Nth gate line G and the Mth data line G via transistor T; the second pixel electrode P2 is electrically connected to the Nth gate line G and the (M+1)th data line D via transistor T; the third pixel electrode P3 is electrically connected to the Nth gate line G and the (M+2)th data line D via transistor T; the fourth pixel electrode P4 is electrically connected to the (N+1)th gate line G and the (M+1)th data line D via transistor T; the fifth pixel electrode P5 is electrically connected to the (N+1)th gate line G and the (M+2)th data line D via transistor T; and the sixth pixel electrode P6 is electrically connected to the (N+1)th gate line G and the (M+3)th data line D via transistor T; where N and M represent positive integers;
[0078] The first pixel electrode P1 and the sixth pixel electrode P6 emit the same light color; the second pixel electrode P2 and the fourth pixel electrode P4 emit the same light color; the third pixel electrode P3 and the fifth pixel electrode P5 emit the same light color.
[0079] In this embodiment, by adjusting the positions of different sub-pixels, a pixel arrangement with 2 rows * 3 columns of sub-pixels as the smallest circulating unit is formed. This enables the display panel of the Triple Gate pixel architecture to apply the HSR frequency multiplication mode, thereby further improving the specifications of the display device (e.g., 60Hz → 120Hz) and enhancing product competitiveness. Moreover, compared with the prior art, this embodiment, by forming a pixel arrangement with 2 rows * 3 columns of sub-pixels as the smallest circulating unit, still retains the sub-pixels of the three primary colors RGB in each pixel, which can achieve a sub-pixel ratio of 1:1:1 in the pixel, maintain the same resolution, and at the same time, can implement the application of the HSR frequency multiplication mode, thereby improving the refresh rate of the display panel.
[0080] In one possible implementation, see Figure 1B As shown, the first pixel electrode P1 and the sixth pixel electrode P6 both emit blue light; the second pixel electrode P2 and the fourth pixel electrode P4 both emit green light; and the third pixel electrode P3 and the fifth pixel electrode P5 both emit red light.
[0081] In another possible implementation, the first pixel electrode P1 and the sixth pixel electrode P6 may both emit blue light; the second pixel electrode P2 and the fourth pixel electrode P4 may both emit red light; and the third pixel electrode P3 and the fifth pixel electrode P5 may both emit green light.
[0082] In another possible implementation, the first pixel electrode P1 and the sixth pixel electrode P6 both emit green light; the second pixel electrode P2 and the fourth pixel electrode P4 both emit blue light; and the third pixel electrode P3 and the fifth pixel electrode P5 both emit red light.
[0083] In another possible implementation, the first pixel electrode P1 and the sixth pixel electrode P6 both emit green light; the second pixel electrode P2 and the fourth pixel electrode P4 both emit red light; and the third pixel electrode P3 and the fifth pixel electrode P5 both emit blue light.
[0084] In another possible implementation, the first pixel electrode P1 and the sixth pixel electrode P6 both emit red light; the second pixel electrode P2 and the fourth pixel electrode P4 both emit green light; and the third pixel electrode P3 and the fifth pixel electrode P5 both emit blue light.
[0085] In another possible implementation, the first pixel electrode P1 and the sixth pixel electrode P6 both emit red light; the second pixel electrode P2 and the fourth pixel electrode P4 both emit blue light; and the third pixel electrode P3 and the fifth pixel electrode P5 both emit green light.
[0086] For two pixel electrodes P located in at least partially adjacent pixel electrode rows P00 and electrically connected to the same data line D via transistor T, the emitted light color is the same. In one possible implementation, this could mean that any two pixel electrodes P electrically connected to the same data line D emit the same light color. Figure 1A In this context, for any given data line D, the multiple pixel electrodes P electrically connected to that data line D emit light of the same color. For example, for the second data line D from left to right, the pixel electrodes P electrically connected to the second data line D are all green pixel electrodes G that emit green light; for another example, for the third data line D from left to right, the pixel electrodes P electrically connected to the third data line D are all red pixel electrodes R that emit red light; and for yet another example, for the fourth data line D from left to right, the pixel electrodes P electrically connected to the fourth data line D are all blue pixel electrodes B that emit blue light.
[0087] In this embodiment of the disclosure, any two pixel electrodes P electrically connected to the same data line D emit the same light color, which can simultaneously support the implementation of HSR mode and DLG mode.
[0088] For two pixel electrodes P located in at least partially adjacent pixel electrode rows P00 and electrically connected to the same data line D via transistor T, the emitted light color is the same. In one possible implementation, each pair of adjacent pixel electrode rows can be a group, and the emitted light colors of two pixel electrodes P located in the two pixel electrode rows of that group and electrically connected to the same data line D are the same. Specifically, in conjunction with... Figure 3 or Figure 4As shown, the array substrate includes: a plurality of pixel electrode rows PZ extending along a first direction X and arranged along a second direction Y; at least one of the plurality of pixel electrode rows PZ includes: two pixel electrode rows P00; the two pixel electrodes P that are electrically connected to the same data line D through a transistor T and are located in the same pixel electrode row PZ have the same emitted light color.
[0089] In this embodiment of the disclosure, any two pixel electrodes P electrically connected to the same data line D emit the same light color, thus realizing the DLG mode.
[0090] In one possible implementation, combining Figure 3 or Figure 4 As shown, two pixel electrodes P, electrically connected to the same data line D via transistor T and located in adjacent pixel electrode row groups PZ, emit light of different colors. For example, as... Figure 3 In the middle, for the second data line D from left to right, the multiple pixel electrodes P electrically connected to the second data line D are, in order from top to bottom, two green pixel electrodes G that emit green light, two blue pixel electrodes B that emit blue light, and two red pixel electrodes R that emit red light.
[0091] In one possible implementation, see Figure 3 or Figure 4 As shown, the array substrate includes: a plurality of second pixel electrode repeating units PB; the second pixel repeating units PB include: seventh pixel electrode P7, eighth pixel electrode P8, ninth pixel electrode P9, tenth pixel electrode P10, eleventh pixel electrode P11, twelfth pixel electrode P12, thirteenth pixel electrode P13, fourteenth pixel electrode P14, fifteenth pixel electrode P15, sixteenth pixel electrode P16, seventeenth pixel electrode P17, eighteenth pixel electrode P18, nineteenth pixel electrode P19, twentieth pixel electrode P20, twenty-first pixel electrode P21, twenty-second pixel electrode P22, twenty-third pixel electrode P23, twenty-fourth pixel electrode P24, and twenty-fifth pixel electrode P25;
[0092] Specifically, the seventh pixel electrode P7 is electrically connected to the J-th gate line G and the K-th data line D via transistor T; the eighth pixel electrode P8 is electrically connected to the J-th gate line G and the (K+1)-th data line D via transistor T; the ninth pixel electrode P9 is electrically connected to the J-th gate line G and the (K+2)-th data line D via transistor T; the tenth pixel electrode P10 is electrically connected to the (J+1)-th gate line G and the (K+1)-th data line D via transistor T; and the eleventh pixel electrode P11 is electrically connected to the (J+1)-th gate line G and the (K+2)-th data line D via transistor T. +2 data lines D; the twelfth pixel electrode P12 is electrically connected to the (J+1)th gate line G and the (K+3)th data line D via transistor T; the thirteenth pixel electrode P13 is electrically connected to the (J+2)th gate line G and the (K)th data line D via transistor T; the fourteenth pixel electrode P14 is electrically connected to the (J+2)th gate line G and the (K+1)th data line D via transistor T; the fifteenth pixel electrode P15 is electrically connected to the (J+2)th gate line G and the (K+2)th data line D via transistor T; the sixteenth pixel electrode P16 is connected to the (J+2)th data line G via transistor T; Transistor T is electrically connected to the (J+3)th gate line G and the (K+1)th data line D; the seventeenth pixel electrode P17 is electrically connected to the (J+3)th gate line G and the (K+2)th data line D via transistor T; the eighteenth pixel electrode P18 is electrically connected to the (J+3)th gate line G and the (K+3)th data line D via transistor T; the nineteenth pixel electrode P19 is electrically connected to the (J+4)th gate line G and the (K)th data line D via transistor T; the twentieth pixel electrode P20 is electrically connected to the (J+4)th gate line G and the (K+1)th data line D via transistor T. Data line D; the twenty-first pixel electrode P21 is electrically connected to the (J+4)th gate line G and the (K+2)th data line D via transistor T; the twenty-second pixel electrode P22 is electrically connected to the (J+5)th gate line G and the (K+1)th data line D via transistor T; the twenty-third pixel electrode P23 is electrically connected to the (J+5)th gate line G and the (K+2)th data line D via transistor T; the twenty-fourth pixel electrode P24 is electrically connected to the (J+5)th gate line G and the (K+3)th data line D via transistor T; where J and K represent positive integers;
[0093] The seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 emit the same light color; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 emit the same light color; the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 emit the same light color.
[0094] In this embodiment of the disclosure, by adjusting the positions of different sub-pixels, a pixel arrangement is formed with 6 rows * 3 columns of sub-pixels as the smallest cycle unit, so that the display panel of Triple Gate pixel architecture or single gate pixel architecture can apply HSR doubling mode, thereby further improving the specifications of the display device (e.g., 60Hz → 120Hz) and enhancing product competitiveness.
[0095] In one possible implementation, see Figure 3 or Figure 4 As shown, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 can all emit blue light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 can all emit green light; and the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 can all emit red light.
[0096] In another possible implementation, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 can all emit blue light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 can all emit red light; and the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 can all emit green light.
[0097] In another possible implementation, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 can all emit green light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 can all emit blue light; and the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 can all emit red light.
[0098] In another possible implementation, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 can all emit green light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 can all emit red light; and the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 can all emit blue light.
[0099] In another possible implementation, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 can all emit red light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 can all emit green light; and the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 can all emit blue light.
[0100] In another possible implementation, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 can all emit red light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 can all emit blue light; and the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 can all emit green light.
[0101] In one possible implementation, Figures 2B-2FThis can be a single-layer schematic diagram of various film layers sequentially disposed on a substrate. Specifically, the array substrate can sequentially disposed on the substrate a common electrode layer, a gate line layer, an active layer, a data line layer, and a pixel electrode layer. The common electrode layer can consist of multiple arrayed common electrode blocks Z. There may be no insulating layer between the common electrode layer and the layer containing the gate line G. There is a gap between the common electrode blocks Z and the gate line G, providing mutual insulation. The layer containing the gate line G may also include multiple first common connection lines G0 extending along a first direction X. The multiple common electrode blocks Z in the first direction X can directly overlap with the first common connection lines G0, thus connecting the multiple common electrode blocks Z in the first direction X to each other. The layer containing the pixel electrode P may also include multiple overlapping portions P0, combined with... Figure 2A As shown, multiple common electrode blocks Z in the second direction Y can be electrically connected to each other through the overlapping portion P0, so that the multiple common electrode blocks Z are interconnected in the second direction Y, thereby forming a structure of horizontal and vertical electrical connection of the common electrode layer; optionally, the common electrode blocks Z and the overlapping portion P0 can be electrically connected through the via K2; optionally, the active layer can include multiple active patterns F; the pixel electrode P can be electrically connected to the drain of the transistor T through the first via K1; optionally, the common electrode block Z can be a block electrode, and the pixel electrode P can have multiple slits.
[0102] Based on the same inventive concept, embodiments of this disclosure also provide a display panel, which includes an array substrate as provided in embodiments of this disclosure.
[0103] Based on the same inventive concept, this disclosure also provides a display device, including the display panel described above. Implementation of this display device can refer to the embodiments of the display panel described above; repeated details will not be repeated.
[0104] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.
[0105] Based on the same inventive concept, this disclosure also provides a driving method for driving an array substrate as described in this disclosure embodiment, see [link to relevant documentation]. Figure 9 As shown, the driving method includes:
[0106] Step S100: Control the data lines to sequentially load data signals;
[0107] Step S200: During the period when the same data signal is loaded on the data line, control at least two adjacent gate lines to open so that two pixel electrodes that are electrically connected to the same data line through a transistor and are located in adjacent pixel electrode rows are loaded with the same data signal.
[0108] In one possible implementation, combining Figure 7 As shown, for step S200, during the period when the same data signal is applied to the data lines, controlling at least two adjacent gate lines to open includes:
[0109] Control the opening of the nth gate line and control the opening of the (n+1)th gate line, wherein the (n+1)th gate line has a first time period t1 that is opened simultaneously with the nth gate line, and a second time period t2 that is delayed after the nth gate line is closed;
[0110] In the first time period t1 and the second time period t2, a first data signal is applied to the m-th data line so that the two pixel electrodes electrically connected to the n-th, n+1-th gate lines and the m-th data line are all loaded with the first data signal, where n and m represent positive integers.
[0111] In one possible implementation, combining Figure 8 As shown, for step S200, during the period when the same data signal is applied to the data lines, controlling at least two adjacent gate lines to open includes:
[0112] Control the j-th and j+1-th gate lines to open simultaneously, wherein the j+1-th gate line has a third time period t3 that opens simultaneously with the j-th gate line;
[0113] In the third time period t4, a second data signal is applied to the k-th data line so that the two pixel electrodes electrically connected to the j-th, j+1-th gate lines and the k-th data line are all loaded with the second data signal, where j represents an odd or even number and k represents a positive integer.
[0114] In one possible implementation, in the current frame, the polarity of the valid signals loaded on adjacent data lines can be opposite. For example, one data line may be loaded with a positive polarity data signal, while the adjacent data lines may be loaded with a negative polarity data signal. In the next frame, the polarity of the valid signal loaded on each data line may be opposite to that of the valid data signal loaded on the data line in the previous frame. For example, in the current frame, one data line may be loaded with a positive polarity data signal, while in the next frame, that data line may be loaded with a negative polarity data signal.
[0115] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.
[0116] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. An array substrate, wherein, include: Substrate; Multiple grid lines, the multiple grid lines extending along a first direction; Multiple data lines, the multiple data lines extending along a second direction; Multiple pixel electrode rows, the multiple pixel electrode rows extending along the first direction and arranged along the second direction; At least one of the plurality of pixel electrode rows includes: a plurality of pixel electrodes with different emitted light colors; the pixel electrodes are located in the region formed by the intersection of the gate line and the data line; Multiple transistors, wherein the pixel electrodes are electrically connected to the gate line and the data line through the transistors, and the multiple pixel electrodes electrically connected to the same data line through the transistors are alternately located on different sides of the data line; Wherein, two pixel electrodes located in at least partially adjacent rows of pixel electrodes and electrically connected to the same data line via the transistor emit light of the same color, and at least two adjacent gate lines are simultaneously turned on, so that two pixel electrodes electrically connected to the same data line via the transistor and located in adjacent rows of pixel electrodes are loaded with the same data signal; The array substrate includes: a plurality of second pixel electrode repeating units; the second pixel electrode repeating unit includes: a seventh pixel electrode, an eighth pixel electrode, a ninth pixel electrode, a tenth pixel electrode, an eleventh pixel electrode, a twelfth pixel electrode, a thirteenth pixel electrode, a fourteenth pixel electrode, a fifteenth pixel electrode, a sixteenth pixel electrode, a seventeenth pixel electrode, an eighteenth pixel electrode, a nineteenth pixel electrode, a twentieth pixel electrode, a twenty-first pixel electrode, a twenty-second pixel electrode, a twenty-third pixel electrode, and a twenty-fourth pixel electrode; Specifically, the seventh pixel electrode is electrically connected to the Jth gate line and the Kth data line via the transistor; the eighth pixel electrode is electrically connected to the Jth gate line and the (K+1)th data line via the transistor; the ninth pixel electrode is electrically connected to the Jth gate line and the (K+2)th data line via the transistor; the tenth pixel electrode is electrically connected to the (J+1)th gate line and the (K+1)th data line via the transistor; and the eleventh pixel electrode is electrically connected to the (J+1)th gate line via the transistor. The data line K+2; the twelfth pixel electrode is electrically connected to the gate line J+1 and the data line K+3 via the transistor; the thirteenth pixel electrode is electrically connected to the gate line J+2 and the data line K via the transistor; the fourteenth pixel electrode is electrically connected to the gate line J+2 and the data line K+1 via the transistor; the fifteenth pixel electrode is electrically connected to the gate line J+2 and the data line K+2 via the transistor; the sixteenth pixel electrode is electrically connected to the data line K+3 via the transistor. The transistor is electrically connected to the (J+3)th gate line and the (K+1)th data line; the seventeenth pixel electrode is electrically connected to the (J+3)th gate line and the (K+2)th data line via the transistor; the eighteenth pixel electrode is electrically connected to the (J+3)th gate line and the (K+3)th data line via the transistor; the nineteenth pixel electrode is electrically connected to the (J+4)th gate line and the (K)th data line via the transistor; the twentieth pixel electrode is electrically connected to the (J+4)th gate line and the (K+1)th data line via the transistor. The data lines; the 21st pixel electrode is electrically connected to the (J+4)th gate line and the (K+2)th data line via the transistor; the 22nd pixel electrode is electrically connected to the (J+5)th gate line and the (K+1)th data line via the transistor; the 23rd pixel electrode is electrically connected to the (J+5)th gate line and the (K+2)th data line via the transistor; the 24th pixel electrode is electrically connected to the (J+5)th gate line and the (K+3)th data line via the transistor; wherein, J and K represent positive integers; The seventh, twelfth, fourteenth, sixteenth, twenty-first, and twenty-third pixel electrodes emit the same light color; the eighth, tenth, fifteenth, seventeenth, nineteenth, and twenty-fourth pixel electrodes emit the same light color; the ninth, eleventh, thirteenth, eighteenth, twentieth, and twenty-second pixel electrodes emit the same light color. Within a frame, the polarities of the data signals loaded on adjacent data lines are opposite.
2. The array substrate as claimed in claim 1, wherein, In adjacent rows of pixel electrodes, the pixel electrodes with the same emitted light color are staggered.
3. The array substrate as described in claim 2, wherein, In adjacent rows of pixel electrodes, the minimum misalignment width of pixel electrodes with the same emitted light color is the same as the spacing between two adjacent pixel electrodes in the same row of pixel electrodes.
4. The array substrate according to any one of claims 1-3, wherein, The array substrate includes: a plurality of pixel electrode rows extending along the first direction and arranged along the second direction; at least one of the plurality of pixel electrode rows includes: two pixel electrode rows; The two pixel electrodes that are electrically connected to the same data line via the transistor and are located in the same pixel electrode row group emit light of the same color.
5. The array substrate as claimed in claim 4, wherein, The two pixel electrodes, which are electrically connected to the same data line via the transistor and are located in adjacent pixel electrode rows, emit different colors of light.
6. The array substrate according to any one of claims 1-3, wherein, The length of the pixel electrode in the first direction is greater than its length in the second direction.
7. The array substrate according to any one of claims 1-3, wherein, The length of the pixel electrode in the first direction is less than its length in the second direction.
8. A display panel, wherein, It includes the array substrate as described in any one of claims 1-7, and further includes a counter substrate disposed opposite to the array substrate.
9. A display device, wherein, Includes the display panel as described in claim 8.
10. A driving method for driving an array substrate as described in any one of claims 1-7, wherein, The driving method includes: The data lines are controlled to sequentially load data signals; During the period when the same data signal is loaded on the data line, at least two adjacent gate lines are controlled to open so that two pixel electrodes electrically connected to the same data line through the transistor and located in adjacent rows of pixel electrodes are loaded with the same data signal.
11. The driving method as described in claim 10, wherein, During the period when the same data signal is applied to the data lines, controlling at least two adjacent gate lines to open includes: Controlling the nth gate line to open, and controlling the (n+1)th gate line to open, wherein the (n+1)th gate line has a first time period that opens simultaneously with the nth gate line, and a second time period that closes after the nth gate line; During the first time period and the second time period, a first data signal is loaded onto the m-th data line, so that the two pixel electrodes electrically connected to the n-th, n+1-th gate lines and the m-th data line are all loaded with the first data signal, where n and m represent positive integers.
12. The driving method as described in claim 10, wherein, During the period when the same data signal is applied to the data lines, controlling at least two adjacent gate lines to open includes: The j-th and j+1-th gate lines are controlled to open simultaneously, wherein the j+1-th gate line has a third time period that is opened simultaneously with the j-th gate line; In the third time period, a second data signal is loaded onto the k-th data line so that the two pixel electrodes electrically connected to the j-th, j+1-th, and k-th data lines are all loaded with the second data signal, where j represents an odd or even number and k represents a positive integer.