A method for preparing a barrier layer of a metal interconnect device

Abstract

The present application provides a method for preparing a barrier layer of a metal interconnect device, the method comprising: obtaining an initial semiconductor substrate, the initial semiconductor substrate comprising a first channel in a dielectric layer located on a device layer of a metal interconnect device; depositing a first barrier layer on the initial semiconductor substrate according to a first deposition condition, the first barrier layer covering the initial semiconductor substrate; etching a groove corresponding to the first channel into a second channel by removing at least the first barrier layer at the bottom according to a preset etching condition, so as to obtain a substrate to be deposited; depositing a second barrier layer on the substrate to be deposited according to a second deposition condition, so as to obtain a target barrier layer covering the dielectric layer and the second channel; wherein the first deposition condition and the preset etching condition are both used to limit the specifications of the second channel, so as to improve the electromigration performance of the metal interconnect device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor process technology, and in particular to a method for preparing a barrier layer of a metal interconnect device. Background Art

[0002] In the copper back-end process manufacturing in the semiconductor process, copper is filled through the Damascus interconnection process to reduce the device resistance and capacitance, but the introduction of copper may cause electromigration (EM), affecting the service life of the device. Currently, electromigration is improved by adding a protective layer (Cap layer) covering the metal interconnection line at the copper interface, or removing contamination and improving the purity of the bottom of the through hole (VIA), or using CuAl and CuMn alloys as a barrier layer. Although the above methods can improve electromigration, they require the introduction of additional steps or replacement of the target material, which increases the cost of wafer manufacturing. Summary of the invention

[0003] In view of this, the purpose of the present application is to at least provide a method for preparing a barrier layer of a metal interconnect device, by depositing a first barrier layer on a dielectric layer on which a channel has been etched on a device layer of the metal interconnect device, and the first barrier layer prevents subsequent over-etching, and then etching the groove corresponding to the channel to at least remove the first barrier layer, thereby increasing the depth of the channel, and then depositing a second barrier layer to obtain a target barrier layer combining the first barrier layer and the second barrier layer, and then optimizing the electromigration phenomenon of the metal interconnect device by increasing the contact area of ​​the channel and increasing the thickness of the first barrier layer, thereby solving the technical problem of poor electromigration performance of the metal interconnect device in the prior art and achieving the technical effect of improving the electromigration performance of the metal interconnect device.

[0004] This application mainly includes the following aspects:

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a barrier layer of a metal interconnect device, the method comprising: obtaining an initial semiconductor substrate, the initial semiconductor substrate comprising a first channel in a dielectric layer located on a device layer of the metal interconnect device; depositing a first barrier layer on the initial semiconductor substrate according to a first deposition condition, the first barrier layer covering the initial semiconductor substrate; etching a groove corresponding to the first channel into a second channel by removing at least the bottom of the first barrier layer according to a preset etching condition, so as to obtain a substrate to be deposited; depositing a second barrier layer on the substrate to be deposited according to a second deposition condition, so as to obtain a target barrier layer covering the dielectric layer and the second channel; wherein the first deposition condition and the preset etching condition are both used to limit the specifications of the second channel, so as to improve the electromigration performance of the metal interconnect device.

[0006] Optionally, the first deposition condition is used to prevent over-etching of the second channel by limiting the thickness of the first barrier layer, and the preset etching condition is used to increase the contact area between the portion of the second channel below the etched dielectric layer and the second barrier layer.

[0007] Optionally, depositing a first barrier layer on the initial semiconductor substrate according to a first deposition condition includes: depositing an adhesion layer of a first material on the initial semiconductor substrate according to the first deposition condition and depositing an isolation layer of a second material on the adhesion layer, so that the adhesion layer and the isolation layer serve as the first barrier layer; wherein the first deposition condition is used to increase the thickness of the adhesion layer and the isolation layer.

[0008] Optionally, the first deposition condition increases the thickness of the adhesion layer and the isolation layer by increasing deposition time and / or increasing deposition power, and the preset etching condition increases the contact area by increasing etching time and / or increasing etching power.

[0009] Optionally, the second deposition condition is used to repair defects caused by etching, and the material of the second barrier layer is the same as that of the isolation layer.

[0010] Optionally, the method further comprises: depositing a preset metal on the target barrier layer, and then performing chemical mechanical polishing.

[0011] Optionally, a preset metal is deposited on the target barrier layer in the following manner: an initial seed layer of the preset metal is deposited on the target barrier layer; and the preset metal is deposited on the initial seed layer and fills the second trench.

[0012] Optionally, the method also includes: collecting multiple parameters of the metal interconnect device, the multiple parameters including thickness parameters of the target barrier layer at different positions and specification parameters of the second channel after etching; determining the ratio of two preset parameters among the multiple parameters; and judging the electromigration performance of the metal interconnect device through the ratio and the corresponding preset ratio range.

[0013] Optionally, the second channel includes a horizontal area, the second channel includes one or more, the target barrier layer includes the second barrier layer located in the second channel and a combined part other than the second barrier layer, wherein the multiple parameters include a first thickness of the combined part located on a target horizontal plane, a second thickness of the combined part located on a sidewall of the second channel, a depth and a width of the second channel located below the dielectric layer, wherein the target horizontal plane includes: a horizontal area of ​​a second channel, or a horizontal area where a preset metal is deposited between adjacent second channels.

[0014] Optionally, the preset metal is copper.

[0015] An embodiment of the present application provides a method for preparing a barrier layer of a metal interconnect device, the method comprising: obtaining an initial semiconductor substrate, the initial semiconductor substrate comprising a first channel in a dielectric layer located on a device layer of the metal interconnect device; depositing a first barrier layer on the initial semiconductor substrate according to a first deposition condition, the first barrier layer covering the initial semiconductor substrate; etching a groove corresponding to the first channel into a second channel by removing at least the bottom of the first barrier layer according to a preset etching condition, so as to obtain a substrate to be deposited; depositing a second barrier layer on the substrate to be deposited according to a second deposition condition, so as to obtain a target barrier layer covering the dielectric layer and the second channel; wherein the first deposition condition and the preset etching condition are both used to limit the specifications of the second channel, so as to improve the electromigration performance of the metal interconnect device. A first barrier layer is deposited on a dielectric layer on which a channel has been etched on a device layer of a metal interconnect device, and the first barrier layer prevents subsequent over-etching, and then a groove corresponding to the channel is etched to at least remove the first barrier layer, thereby increasing the depth of the channel, and then a second barrier layer is deposited to obtain a target barrier layer in which the first barrier layer and the second barrier layer are combined, thereby optimizing the electromigration phenomenon of the metal interconnect device by increasing the contact area of ​​the channel and increasing the thickness of the first barrier layer, thereby solving the technical problem of poor electromigration performance of the metal interconnect device in the prior art and achieving the technical effect of improving the electromigration performance of the metal interconnect device.

[0016] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A flow chart of a method for preparing a barrier layer of a metal interconnect device provided in an embodiment of the present application is shown.

[0019] Figure 2 A schematic diagram of a metal interconnect device provided in an embodiment of the present application is shown.

[0020] Figure 3 A schematic diagram of the first barrier layer provided in an embodiment of the present application is shown.

[0021] Figure 4 A schematic diagram of a second channel provided in an embodiment of the present application is shown.

[0022] Figure 5 A schematic diagram of the second barrier layer provided in an embodiment of the present application is shown.

[0023] Figure 6 A schematic diagram of depositing a preset metal on a target barrier layer provided in an embodiment of the present application is shown.

[0024] Figure 7 A schematic diagram of a chemical mechanical polishing process provided in an embodiment of the present application is shown.

[0025] Figure 8 A schematic diagram showing multiple parameters corresponding to a second channel and multiple second channels provided in an embodiment of the present application is shown.

[0026] Fig. 9 The logarithmic normal distribution diagram of TTF corresponding to different temperatures when the depth of the second channel and the thickness of the first barrier layer provided in the embodiment of the present application are not increased is shown.

[0027] Fig.10 The logarithmic normal distribution diagram of TTF corresponding to different currents when the depth of the second channel and the thickness of the first barrier layer provided in the embodiment of the present application are not increased is shown.

[0028] Fig.11 The logarithmic normal distribution diagram of TTF corresponding to different temperatures when the depth of the second channel and the thickness of the first barrier layer provided in the embodiment of the present application are increased is shown.

[0029] Fig.12 The logarithmic normal distribution diagram of TTF corresponding to different currents when the depth of the second channel and the thickness of the first barrier layer are increased according to the embodiment of the present application is shown. DETAILED DESCRIPTION

[0030] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art, under the guidance of the content of the present application, can add one or more other operations to the flowchart, or remove one or more operations from the flowchart.

[0031] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0032] In the prior art, in the copper back-end process manufacturing in the semiconductor process, copper is filled through the Damascus interconnection process to reduce the device resistance and capacitance, but the introduction of copper may cause electromigration (EM), affecting the service life of the device. Currently, electromigration is improved by adding a protective layer (Cap layer) covering the metal interconnection line at the copper interface, or removing contamination and improving the purity of the bottom of the through hole (VIA), or using CuAl and CuMn alloys as a barrier layer in 32nm technology. Although the above methods can improve electromigration, it requires the introduction of additional steps or replacement of the target material, which increases the cost of wafer manufacturing.

[0033] Based on this, the embodiment of the present application provides a method for preparing a barrier layer of a metal interconnect device, by depositing a first barrier layer on a dielectric layer on which a channel has been etched on a device layer of the metal interconnect device, and the first barrier layer prevents subsequent over-etching, and then etching a groove corresponding to the channel to at least remove the first barrier layer, thereby increasing the depth of the channel, and then depositing a second barrier layer to obtain a target barrier layer combining the first barrier layer and the second barrier layer, and then optimizing the electromigration phenomenon of the metal interconnect device by increasing the contact area of ​​the channel and increasing the thickness of the first barrier layer, solving the technical problem of poor electromigration performance of the metal interconnect device in the prior art, and achieving the technical effect of improving the electromigration performance of the metal interconnect device, without changing the traditional preparation steps, and without changing the target material, as described in detail as follows:

[0034] See also Figure 1 , Figure 1 The flowchart of a method for preparing a barrier layer of a metal interconnect device provided in an embodiment of the present application is as follows. Figure 1 As shown, the method for preparing a barrier layer of a metal interconnect device provided in an embodiment of the present application comprises the following steps:

[0035] S101: Obtain an initial semiconductor substrate.

[0036] The initial semiconductor substrate includes a first channel in a dielectric layer located above a device layer of a metal interconnect device.

[0037] Among them, the metal interconnection device is formed by the Damascene interconnection process. Figure 2 , Figure 2 A schematic diagram of a metal interconnect device provided in an embodiment of the present application. Figure 2 As shown, the device layer of the metal interconnect device includes an NPN structure and a PNP structure. The specific structure of the device layer can be changed according to actual conditions and is not limited to a certain structure. A layer of SiN (silicon nitride) is deposited on the basis of the device layer, a polysilicon oxide layer (ILD OX) is deposited on the SiN, and a channel is etched out of the polysilicon oxide layer and Ti (titanium) and / or TiN (titanium nitride) are filled at the bottom and inner wall of the channel, and then metal tungsten W is filled in the channel; finally, a thin film is deposited as a copper barrier layer NDC, and the material of the thin film can be silicon carbide; a low-k dielectric layer BD is deposited on the basis of the thin film; a hard mask layer is deposited on the low-k dielectric layer, and its material is tetraethyl silicate TEOS, so that NDC, BD and TEOS are used as the first initial dielectric layer above the device layer. Thus, a channel is etched out of the first initial dielectric layer, at which time the NDC, BD and TEOS in the channel area are etched away and the bottom of the channel is a polysilicon oxide layer, and then the etched channel is filled with a target barrier layer and copper to obtain M1; then chemical mechanical polishing (CMP) is performed for leveling, at which time part of the target barrier layer, copper, and TEOS and part of BD of the first initial dielectric layer are etched away, so that the first initial dielectric layer only includes the remaining BD and NDC to obtain the first dielectric layer; NDC, BD and TEOS are sequentially deposited on the first dielectric layer and the aforementioned steps are repeated until the second dielectric layer is obtained, and this cyclic operation is performed to achieve the arrangement of multiple dielectric layers on the polysilicon oxide layer according to the preset structure of the metal interconnect device, and the target barrier layer and the preset metal are deposited in each dielectric layer. Thus, the preset metals sequentially deposited in the metal interconnect device are M1, V1, M2, V2, and M3, where M represents metal and V represents VIA.

[0038] Exemplarily, the initial semiconductor substrate of the present application refers to a semiconductor substrate after etching is performed on any dielectric layer of the metal interconnect device to obtain the first trench. If the dielectric layer is the first dielectric layer closest to the polysilicon oxide layer, the bottom of the etched first trench may be the polysilicon oxide layer; if the dielectric layer is not the first dielectric layer closest to the polysilicon oxide layer, the bottom of the etched first trench is the preset metal filled in the trench of the dielectric layer below the dielectric layer.

[0039] That is to say, the target barrier layer deposited on the first channel of the present application is used to isolate the dielectric layer and the preset metal subsequently deposited in the channel of the dielectric layer, or to isolate the preset metal deposited in two adjacent dielectric layers, thereby optimizing the electromigration of the metal interconnect device by limiting the specifications of the barrier layer.

[0040] Exemplarily, the preset metal in the present application is copper. The technical solution of the present application is applied to copper back-end process manufacturing, specifically, to 55nm copper back-end process manufacturing.

[0041] return Figure 1 , S102: depositing a first barrier layer on the initial semiconductor substrate according to a first deposition condition.

[0042] Wherein, the first barrier layer covers the initial semiconductor substrate. Specifically, the first barrier layer is uniformly deposited on the initial semiconductor substrate, and the first barrier layer covers the surface of the initial semiconductor substrate.

[0043] The first deposition condition is used to prevent over-etching of the second channel by limiting the thickness of the first barrier layer. Specifically, the first deposition condition prevents over-etching in subsequent steps by increasing the thickness of the first barrier layer, ensuring the remaining thickness of the first barrier layer after etching, so as to optimize the electromigration effect. In addition, increasing the thickness of the first barrier layer is also used to protect the corner area at the top of the first channel to prevent the subsequent etching from etching away the corner area, and maintain the depth and width of the second channel etched subsequently.

[0044] The step of depositing a first barrier layer on the initial semiconductor substrate according to the first deposition condition comprises: depositing an adhesion layer of a first material on the initial semiconductor substrate according to the first deposition condition and depositing an isolation layer of a second material on the adhesion layer, so that the adhesion layer and the isolation layer serve as the first barrier layer; wherein the first deposition condition is used to increase the thickness of the adhesion layer and the isolation layer.

[0045] That is, the first deposition condition includes an adhesion layer deposition condition for depositing an adhesion layer and an isolation layer deposition condition for depositing an isolation layer. Further, an adhesion layer of a first material is uniformly deposited on the initial semiconductor substrate according to the adhesion layer deposition condition, so as to increase the thickness of the adhesion layer by the adhesion layer deposition condition, and then an isolation layer of a second material is deposited on the adhesion layer according to the isolation layer deposition condition, so as to increase the thickness of the isolation layer by the isolation layer deposition condition.

[0046] Furthermore, the adhesion layer is used to connect the dielectric layer and the second material and to connect the preset metal and the second material, the diffusion layer is used to prevent the subsequently deposited preset metal from diffusing in the dielectric layer, and the adhesion layer deposition conditions and the isolation layer deposition conditions deposit different materials respectively. For example, the first material is tantalum nitride TAN, and the second material is tantalum TA.

[0047] The first deposition condition increases the thickness of the adhesion layer and the isolation layer by increasing the deposition time and / or increasing the deposition power. Specifically, the adhesion layer deposition condition and the isolation layer deposition condition increase the deposition thickness by increasing the deposition time and / or increasing the deposition power, thereby increasing the thickness of the first barrier layer.

[0048] See also Figure 3 , Figure 3 This is a schematic diagram of the first barrier layer provided in the embodiment of the present application. Figure 3 As shown, after a channel is etched out in a dielectric layer of any layer on the device layer of the metal interconnect metal and filled with a preset metal Cu, a dielectric layer is deposited again and a first channel is etched out of the dielectric layer to obtain an initial semiconductor substrate. At this time, the dielectric layer where the first channel is located includes NDC, BD and TEOS deposited sequentially from bottom to top. Since the first channel needs to be etched in the dielectric layer, the NDC, BD and TEOS at the location of the first channel are all etched away, and the thickness of TEOS is reduced before and after etching. Thus, an adhesion layer (the blue line portion in the figure) is uniformly deposited on the surface of the initial semiconductor substrate, and then an isolation layer (the light gray portion in the figure) is uniformly deposited on the adhesion layer.

[0049] Among them, before etching, it is necessary to apply photoresist and perform exposure treatment. For example, the exposed part of the photoresist is etched away, so that the NDC, BD and TEOS at the location of the first channel that needs to be etched will be etched away, and the unexposed part of the photoresist will not be etched. The photoresist needs to be removed through ASHER and the corresponding WET process afterwards.

[0050] Generally, the thickness of the adhesion layer and the isolation layer is X, X is 35 to 45 angstroms, and the first deposition condition controls the thickness of the adhesion layer to increase to 1.4 to 1.6 times of X, and controls the thickness of the isolation layer to increase to 1.4 to 2 times of X.

[0051] return Figure 1 S103: etching the groove corresponding to the first channel into a second channel at least removing the first barrier layer at the bottom according to preset etching conditions to obtain a substrate to be deposited.

[0052] The preset etching conditions are used to increase the contact area between the portion of the second channel below the etched dielectric layer and the second barrier layer, and the first deposition conditions and the preset etching conditions are used to limit the specifications of the second channel to improve the electromigration performance of the metal interconnect device.

[0053] That is to say, since the first deposition condition prevents over-etching by increasing the thickness of the first barrier layer, the preset etching condition increases the depth of the second channel to prevent deposition from sealing the first channel and reduces the resistance of subsequent deposition of the preset metal in the second channel, and thus, the specifications of the second channel are limited by the combined effect of the first deposition condition and the preset etching condition.

[0054] Furthermore, the etched second trench will at least remove the first barrier layer deposited at the bottom of the first trench, so as to expose the portion below the surface of the initial semiconductor substrate, that is, the portion below the dielectric layer, at the bottom of the second trench, and etching will be performed while depositing according to the preset etching conditions, so as to better protect the corner portion of the first trench and perform etching more selectively. In this way, the depth and width of the second trench are determined by the preset etching conditions.

[0055] Furthermore, the preset etching conditions can selectively increase the contact area between the copper below the dielectric layer and the subsequently deposited tantalum, that is, increase the depth and width of the second trench. The width of the second trench can be understood as a critical dimension CD.

[0056] Specifically, the preset etching condition increases the depth of the second trench by increasing the etching time and / or increasing the etching power, and further increases the contact area by increasing the depth of the second trench, so as to optimize the electromigration performance of the device.

[0057] Generally, the depth difference between the second trench and the first trench is Y, and Y is generally 80 to 180 angstroms. By presetting etching conditions, the depth difference between the second trench and the first trench is increased to 1.3 to 1.8 times Y to increase the depth of the second trench.

[0058] Please refer to 4, Figure 4 Schematic diagram of the second channel provided in the embodiment of the present application. Figure 4 As shown, in Figure 3 After the first barrier layer is deposited, the groove corresponding to the first channel is etched, at least the first barrier layer at the bottom of the first channel in the dielectric layer is etched away, and a portion of the preset metal below the bottom of the first channel is also etched to generate a second channel. Furthermore, a portion of the surface of the inner wall of the second channel is the first barrier layer, and another portion of the surface of the inner wall of the second channel is exposed as the preset metal, thereby obtaining a substrate to be deposited.

[0059] return Figure 1 S104: depositing a second barrier layer on the substrate to be deposited according to a second deposition condition to obtain a target barrier layer covering the dielectric layer and the second channel.

[0060] The second deposition condition is used to repair defects caused by etching, and the material of the second barrier layer is the same as that of the isolation layer.

[0061] After etching the second groove, a second barrier layer is uniformly deposited on the surface of the substrate to be deposited. The material of the second barrier layer is tantalum TA to repair the defects caused by etching. The thickness of the second barrier layer is 35 to 45 angstroms.

[0062] Please refer to 5, Figure 5 This is a schematic diagram of the second barrier layer provided in the embodiment of the present application. Figure 5 As shown, the second barrier layer (the dark gray part in the figure) can cover the first barrier layer located on the dielectric layer in the substrate to be deposited and the preset metal part etched in the second trench, so that no preset metal is exposed on the substrate to be deposited. Thus, the first barrier layer and the second barrier layer deposited on the dielectric layer and the second barrier layer deposited on the second trench are combined as the target barrier layer.

[0063] The method further comprises: depositing a preset metal on the target barrier layer, and then performing a chemical mechanical polishing process.

[0064] The preset metal is deposited on the target barrier layer in the following manner: an initial seed layer of the preset metal is deposited on the target barrier layer; and the preset metal is deposited on the initial seed layer and fills the second trench.

[0065] See 6, Figure 6 This is a schematic diagram of depositing a preset metal on a target barrier layer provided in an embodiment of the present application. Figure 6 As shown, firstly, an initial seed layer of metal copper is uniformly electroplated on the target barrier layer, and then metal copper is deposited on the initial seed layer to fill the second trench. In other words, the surface of the target barrier layer located above the dielectric layer needs to be covered with the preset metal, and the surface of the target barrier layer located above the preset metal in the second trench also needs to be covered with the preset metal.

[0066] Among them, depositing the first barrier layer, etching the second trench and depositing the second barrier layer are completed in a chamber of a Barrier machine for depositing the target barrier layer; then the semiconductor substrate is moved to another chamber of the machine, an initial seed layer is deposited by physical vapor deposition (PVD), and then the second trench is filled by copper electroplating.

[0067] See also Figure 7 , Figure 7 This is a schematic diagram of the chemical mechanical polishing process provided in the embodiment of the present application. Figure 7As shown, after depositing the preset metal, chemical mechanical polishing (CMP) is used to remove the target barrier layer and the preset metal above the dielectric layer, as well as part of the metal located between two adjacent second trenches, so that the surface is in a horizontal state. At this time, the preparation of the metal interconnect device can be completed, or the dielectric layer can be continuously deposited to etch the first trench in the dielectric layer, thereby obtaining an initial semiconductor device that requires the deposition of the target barrier layer, thereby cyclically processing to prepare a multi-layer dielectric layer of the metal interconnect device.

[0068] Specifically, chemical mechanical polishing will also remove TEOS and part of BD in the dielectric layer, so that after chemical mechanical polishing, part of BD and NDC remain in the dielectric layer.

[0069] Specifically, the method also includes: collecting multiple parameters of the metal interconnect device, the multiple parameters including thickness parameters of the target barrier layer at different positions and specification parameters of the second channel after etching; determining the ratio of two preset parameters among the multiple parameters; and judging the electromigration performance of the metal interconnect device through the ratio and the corresponding preset ratio range.

[0070] Generally, multiple parameters of a metal interconnect device are collected by slicing, that is, slicing the metal interconnect device along a vertical direction to collect various parameters.

[0071] That is to say, after the chemical mechanical polishing treatment, it is necessary to collect the thickness of the target barrier layer at different positions of the metal interconnect device and the specifications of the second channel as multiple parameters of the metal interconnect device, calculate the ratio of the two preset parameters, and determine whether the ratio belongs to the corresponding preset ratio range to determine whether the electromigration performance of the metal interconnect device meets the requirements. When the ratio belongs to the corresponding preset ratio range, it is determined that the electromigration performance of the metal interconnect device meets the requirements, that is, the electromigration performance of the metal interconnect device is good, the metal interconnect device is not easy to be broken down, and it is not easy to cause the failure of the metal interconnect device; when the ratio does not belong to the corresponding preset ratio range, it is determined that the electromigration performance of the metal interconnect device does not meet the requirements, that is, the electromigration performance of the metal interconnect device is poor, the metal interconnect device is easy to be broken down, resulting in the failure of the metal interconnect device.

[0072] The second channel includes a horizontal area, the second channel includes one or more, the target barrier layer includes the second barrier layer located in the second channel and a combined part other than the second barrier layer, wherein the multiple parameters include a first thickness of the combined part located on a target horizontal plane, a second thickness of the combined part located on a sidewall of the second channel, a depth and a width of the second channel located below the dielectric layer, wherein the target horizontal plane includes: a horizontal area of ​​a second channel, or a horizontal area where a preset metal is deposited between adjacent second channels.

[0073] That is, the thickness parameters of the target barrier layer at different positions in the multiple parameters include: the first thickness of the combined part located on the target horizontal plane, the second thickness of the combined part located on the sidewall of the second channel, and the specification parameters of the second channel after etching in the multiple parameters include: the depth and width of the second channel located below the dielectric layer. Figure 2 As shown, the specification parameters of the second trench refer to the depth a and width b of the preset metal etched into the next dielectric layer.

[0074] That is to say, when the number of first channels is one, only one second channel will be generated at the same time, and when the number of first channels is multiple, multiple second channels will be generated accordingly. Each second channel includes a horizontal area, the channel cross section below the horizontal area is smaller than the size of the horizontal area, and the channel cross section above the horizontal area is greater than or equal to the size of the horizontal area. When multiple second channels are set, the horizontal areas of adjacent second channels will be connected during the etching process, and then the target barrier layer etched on the horizontal areas of two adjacent second channels is also connected, and then when the preset metal is subsequently deposited, the preset metal deposited on the horizontal areas of two adjacent second channels is connected.

[0075] Exemplarily, the horizontal region is located 150 nm above the connection position between the dielectric layer and the preset metal of the second channel.

[0076] Furthermore, when etching the groove corresponding to the first channel, a portion of the first barrier layer in the second channel is removed to expose the preset metal underneath, and then a second barrier layer is deposited on the second channel. Furthermore, a portion of the target barrier layer in the second channel includes only the deposited second barrier layer and a combined portion other than the deposited second barrier layer, and the combined portion includes the first barrier layer remaining after etching and the deposited second barrier layer.

[0077] For example, the second channel etched in the actual etching process does not have a uniform width, and thus, the width of the second channel refers to the maximum width of the second channel below the dielectric layer.

[0078] For example, see Figure 8 , Figure 8 A schematic diagram of multiple parameters corresponding to a second channel and multiple second channels provided in an embodiment of the present application. Figure 8 As shown, the thickness L of the target barrier layer on the horizontal area of ​​the second channel K1 is collected. 11 , collecting a thickness L of the combined portion consisting of the remaining first barrier layer etched on the sidewall of a second trench and the deposited second barrier layer 21 , collect a second channel at a depth L below the dielectric layer 31 , collect the maximum width L of the second channel located below the dielectric layer 41 , collect the thickness L of the target barrier layer on the horizontal area adjacent to the second channel 12 , collecting the thickness L of the combined portion consisting of the first barrier layer remaining after etching on the sidewall of any second channel and the second barrier layer deposited 22 , collect the depth L below the dielectric layer in any second channel 32 , collect the maximum width L of any second channel located below the dielectric layer 42 .

[0079] Exemplarily, the electromigration performance of the metal interconnect device is achieved when the following conditions are met: the thickness of the combined portion on the sidewall of the second channel is greater than 0.21 times the thickness of the target barrier layer on the horizontal region of the second channel, the thickness of the combined portion on the sidewall of the second channel is greater than 0.038 times the maximum width of the second channel below the dielectric layer, the thickness of the combined portion on the sidewall of the second channel is greater than 0.088 times the depth of the second channel below the dielectric layer, and the thickness of the target barrier layer on the horizontal region of the second channel is less than 0.77 times the depth of the second channel below the dielectric layer.

[0080] When only the depth of the second trench is increased, the electromigration performance of the metal interconnect device cannot be optimized. Table 1 shows a plurality of parameters of the metal interconnect device collected under different conditions.

[0081] Table 1:

[0082]

[0083] That is, it can be seen from Table 1 that when only the depth of the second channel is increased, the maximum width of the second channel below the dielectric layer is too large, and the depth is not as deep as the depth of the second channel generated when the depth of the second channel is increased and the thickness of the first barrier layer is increased. Therefore, the electromigration performance corresponding to only increasing the depth of the second channel fails to exceed the electromigration performance corresponding to increasing the depth of the second channel and increasing the thickness of the first barrier layer. Therefore, only increasing the depth of the second channel fails to better optimize the electromigration performance.

[0084] Exemplarily, Table 2 shows the ratios of two preset parameters calculated in different situations.

[0085] Table 2:

[0086]

[0087] That is to say, Table 2 shows that increasing the depth of the second channel and the thickness of the first barrier layer optimizes the ratio of the two preset parameters relative to not increasing the depth and thickness, so as to optimize the electromigration of the metal interconnect device. However, the ratio of the two preset parameters obtained by only increasing the depth of the second channel is not better than the ratio of the two preset parameters corresponding to not changing the depth of the second channel and the thickness of the first barrier layer, and thus, only increasing the depth of the second channel does not optimize the electromigration performance. In other words, only increasing the width of the second channel or only increasing the depth of the second channel does not optimize the electromigration performance.

[0088] Among them, the generated metal interconnection device is subjected to electromigration test, and the metal interconnection device is controlled to be at different temperatures or different currents are applied to the metal interconnection device. Electromigration test is performed on the V1 to M2 structures of multiple chips of a chip respectively, and the logarithmic normal distribution diagram of the chip failure time TTF (Time to failure) is obtained. One chip corresponds to one coordinate point, and the coordinate point is used to indicate the failure time TTF and time cumulative failure probability of the chip under different currents or different ambient temperatures. The horizontal axis is used to indicate the failure time of the chip, and the vertical axis is used to indicate the time cumulative failure probability of the chip. Generally, the higher the temperature, the faster the failure, and the higher the current, the faster the failure. Good electromigration performance means that the corresponding failure time TTF of each chip under the same temperature or the same current is uniformly accumulated, and the coordinate points of the corresponding TTF and the corresponding time cumulative failure probability under different temperatures or different currents can be separated, and the slope of the fitting function of TTF and time cumulative failure probability is high. Poor electromigration performance means that the corresponding failure time of each chip at the same temperature or the same current is irregular, and it may fail too early or too late, and the coordinate points of TTF and its corresponding time cumulative failure probability at different temperatures or different currents cannot be separated. In addition, when the chip is sliced ​​after failure, voids will be found in the structure.

[0089] For example, see Fig. 9 and Fig.10 , Fig. 9 The logarithmic normal distribution diagram of TTF corresponding to different temperatures when the depth of the second channel and the thickness of the first barrier layer are not increased provided in the embodiment of the present application, Fig.10The logarithmic normal distribution diagram of TTF corresponding to different currents when the depth of the second channel and the thickness of the first barrier layer are not increased provided in the embodiment of the present application. Fig. 9 and Fig.10 As shown, in the deposition Figure 2 Before the preset metal of V1 and M2, the depth of the second channel of the dielectric layer where V1 and M2 are located and the thickness of the first barrier layer are not increased, so as to carry out electromigration test, and the coordinate points of TTF and their corresponding time cumulative failure probability corresponding to multiple chips at different temperatures or different currents are relatively clustered, making it difficult to fit the data.

[0090] For example, see Fig.11 and Fig.12 , Fig.11 The logarithmic normal distribution diagram of TTF corresponding to different temperatures when the depth of the second channel and the thickness of the first barrier layer are increased provided in the embodiment of the present application, Fig.12 The logarithmic normal distribution diagram of TTF corresponding to different currents when the depth of the second channel and the thickness of the first barrier layer are increased provided in the embodiment of the present application. Fig.11 and Fig.12 As shown, in the deposition Figure 2 Before the preset metal of V1 and M2 in the circuit, the depth of the second channel of the dielectric layer where V1 and M2 are located and the thickness of the first barrier layer are increased, and then, an electromigration test is performed to obtain that the coordinate points of the TTF corresponding to multiple chips at different temperatures or different currents and their corresponding time cumulative failure probabilities are relatively separated, which can optimize the electromigration of metal interconnection devices and facilitate the fitting of the fitting curves of the TTL at different temperatures or different currents and their corresponding time cumulative failure probabilities, so as to facilitate technical personnel to perform failure analysis on metal interconnection devices.

[0091] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0092] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0093] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0094] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0095] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for preparing a barrier layer of a metal interconnect device, characterized in that: The method comprises: Acquire an initial semiconductor substrate, the initial semiconductor substrate comprising a first channel in a dielectric layer on a device layer of a metal interconnect device; Depositing a first barrier layer on the initial semiconductor substrate according to a first deposition condition, wherein the first barrier layer covers the initial semiconductor substrate; Etching the groove corresponding to the first channel into a second channel at least removing the first barrier layer at the bottom according to preset etching conditions to obtain a substrate to be deposited; Depositing a second barrier layer on the substrate to be deposited according to a second deposition condition to obtain a target barrier layer covering the dielectric layer and the second channel; Among them, the first deposition condition and the preset etching condition are both used to limit the specifications of the second channel to improve the electromigration performance of the metal interconnect device. The first deposition condition protects the corner area at the top of the first channel by limiting the thickness of the first barrier layer and prevents over-etching of the second channel and affecting the critical dimensions of the semiconductor manufacturing process by limiting the ratio of the depth to the width of the second channel after etching. The preset etching condition is used to increase the contact area between the portion of the second channel below the etched dielectric layer and the second barrier layer. The preset etching condition increases the contact area by increasing the depth and width of the second channel.

2. The method according to claim 1, characterized in that The step of depositing a first barrier layer on the initial semiconductor substrate according to a first deposition condition comprises: Depositing an adhesion layer of a first material on the initial semiconductor substrate according to the first deposition condition and depositing an isolation layer of a second material on the adhesion layer, so that the adhesion layer and the isolation layer serve as the first barrier layer; The first deposition condition is used to increase the thickness of the adhesion layer and the isolation layer.

3. The method according to claim 2, characterized in that The first deposition condition increases the thickness of the adhesion layer and the isolation layer by increasing the deposition time and / or increasing the deposition power, The preset etching condition increases the contact area by increasing etching time and / or increasing etching power.

4. The method according to claim 2, characterized in that: The second deposition condition is used to repair defects caused by etching, and the material of the second barrier layer is the same as that of the isolation layer.

5. The method according to claim 1, characterized in that The method further comprises: A preset metal is deposited on the target barrier layer, and then a chemical mechanical polishing process is performed.

6. The method according to claim 5, characterized in that Depositing a predetermined metal on the target barrier layer by: Depositing an initial seed layer of the preset metal on the target barrier layer; The predetermined metal is deposited on the initial seed layer and fills the second trench.

7. The method according to claim 5, characterized in that in, The method further comprises: Collecting multiple parameters of the metal interconnect device, wherein the multiple parameters include thickness parameters of the target barrier layer at different positions and specification parameters of the second channel after etching; Determining a ratio of two preset parameters among the plurality of parameters; The electromigration performance of the metal interconnect device is determined by the ratio and the corresponding preset ratio range.

8. The method according to claim 7, characterized in that The second channel includes a horizontal region, the second channel includes one or more, The target barrier layer includes the second barrier layer located in the second trench and a combined portion other than the second barrier layer, The plurality of parameters include a first thickness of the combined portion located on a target horizontal plane, a second thickness of the combined portion located on a sidewall of the second trench, a depth and a width of the second trench located below the dielectric layer, Wherein, the target horizontal plane includes: a horizontal area of ​​a second channel, or a horizontal area where a preset metal is deposited between adjacent second channels.

9. The method according to any one of claims 5 to 8, characterized in that: The preset metal is copper.

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