A method and switching device for querying the status of a service board
By using CPLD/FPGA chips to disable hot-swappable chips in chassis-type routing and switching equipment, the faulty bus board can be directly identified, solving the problem of rapid diagnosis in existing technologies, achieving rapid fault location and reducing on-site maintenance costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEW H3C TECH CO LTD
- Filing Date
- 2024-08-19
- Publication Date
- 2026-07-07
Smart Images
Figure CN119052202B_ABST
Abstract
Description
Technical Field
[0001] This specification relates to the field of communication technology, and in particular to a method and switching device for querying the status of a service board. Background Technology
[0002] like Figure 1 As shown, chassis-type routing and switching devices are generally quite complex. For example, the following architecture consists of two main control slots, slot0 and slot1, and eight service card slots, slots2 to 9. The main control and service cards are connected together through a backplane, and communication between them is generally accomplished through buses such as IIC, SPI, and LVDS.
[0003] Currently, when a bus in a chassis-type routing and switching device malfunctions, because the bus link is divided into three parts—the main control board, the service card, and the backplane—it is impossible to determine which part is causing the problem. In order to resolve the issue at once, our maintenance personnel must simultaneously apply for new main control boards, service cards, and chassis to be sent to the site. However, these devices are often located in remote mountainous areas, making on-site maintenance extremely troublesome. Summary of the Invention
[0004] To overcome the problems existing in related technologies, this specification provides a method and switching device for querying the status of service boards.
[0005] According to a first aspect of the embodiments of this specification, a method for querying the status of a service board is provided, the method comprising:
[0006] When the main control board fails to access the corresponding peripheral device in the service board through the first IIC bus, the hot-swappable chip between each IIC bus and the backplane is disabled through the CPLD / FPGA chip.
[0007] The main control board accesses the peripheral devices corresponding to the first IIC bus through the CPLD / FPGA chip.
[0008] In this case, each IIC bus in the service board is connected to a CPLD / FPGA chip.
[0009] The CPLD / FPGA chip is connected to each IIC bus via reserved pins.
[0010] The method further includes:
[0011] When the main control board normally accesses the corresponding peripheral devices in the service board through the first IIC bus, the pins of the CPLD / FPGA chip connected to each IIC are in an disabled state.
[0012] The method further includes:
[0013] When the primary main control board fails to access the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip, the backup main control board is switched from the primary main control board to enable the backup main control board.
[0014] If the backup main control board fails to access the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip, it can be determined that there is a fault in the service board.
[0015] The method further includes:
[0016] When the primary main control board fails to access the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip, the backup main control board is switched from the primary main control board to enable the backup main control board.
[0017] If the backup main control board successfully accesses the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip, then the connector failure can be determined.
[0018] As can be seen from the above embodiments, when the main control board fails to read peripheral devices through the IIC bus, it can be read through the CPLD / FPGA chip. On the one hand, it saves switching time by eliminating the need for the main control board to perform master-slave switching. On the other hand, the method in this embodiment can further determine which board among the main control board, backplane, and service board is faulty, providing a more convenient diagnostic function for network maintenance. At the same time, temporary remedial measures can be used to meet emergency work needs when a single bus problem occurs.
[0019] According to a second aspect of the embodiments of this specification, a switching device is provided, the switching device comprising: a primary main control board, a backplane, and service boards, wherein the primary main control board, the backplane, and the service boards are connected via connectors, and the primary main control board accesses peripheral devices of the service boards via various IIC buses; the switching device further comprising: a CPLD / FPGA chip, wherein the CPLD / FPGA chip is connected to each IIC bus and a hot-swappable chip respectively, and the hot-swappable chip is connected to the backplane and the IIC bus respectively.
[0020] The switching equipment also includes:
[0021] The judgment module is used to determine whether the main control board has successfully accessed the corresponding peripheral device in the service board through the first IIC bus.
[0022] The processing module is used to disable the hot-swappable chips between each IIC bus and the backplane via the CPLD / FPGA chip when the judgment module fails to determine the problem.
[0023] The access module is used by the main control board to access the peripheral devices corresponding to the first IIC bus through the CPLD / FPGA chip.
[0024] The CPLD / FPGA chip is connected to each IIC bus via reserved pins.
[0025] When the main control board normally accesses the corresponding peripheral device in the service board through the first IIC bus, the pins of the CPLD / FPGA chip connected to each IIC are in an disabled state.
[0026] The processing module is also used to switch the enable of the backup main control board when the main control board fails to access the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip.
[0027] The judgment module is also used to determine that the service board is faulty if the backup main control board fails to access the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip.
[0028] The processing module is further configured to switch from the primary main control board to enable the backup main control board when the primary main control board fails to access the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip.
[0029] The judgment module is also used to determine the connector failure if the backup main control board successfully accesses the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip.
[0030] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description
[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.
[0032] Figure 1 This is a schematic diagram of a chassis routing and switching device illustrated in this specification according to an exemplary embodiment.
[0033] Figure 2 This is a flowchart illustrating a method for querying the status of a service board according to an exemplary embodiment of this specification.
[0034] Figure 3 This is a schematic block diagram of a frame-type routing and switching device bus architecture illustrated in this specification according to an exemplary embodiment. Detailed Implementation
[0035] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.
[0036] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” as used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
[0037] It should be understood that although the terms first, second, third, etc., may be used in this specification to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."
[0038] Currently, when the main control board cannot read the information of the peripheral devices on the service board through the IIC bus, the usual practice is to perform a master-slave switch of the main control board to try to read the information of the peripheral devices. During the master-slave switch, the switch time is usually long and it affects the operation of the service. If it still cannot read the information after the master-slave switch, the maintenance personnel can only carry the new main control board, service card and chassis to the field. Often, these devices may be located in remote mountainous areas. Going to the field for maintenance will increase the labor cost of personnel and also increase the cost of equipment resources.
[0039] To address the aforementioned technical problems, this disclosure provides a method for querying the status of a service board, such as... Figure 2 As shown, the method includes:
[0040] S201 When the main control board fails to access the corresponding peripheral device in the service board through the first IIC bus, the hot-swappable chip between each IIC bus and the backplane is disabled through the CPLD / FPGA chip.
[0041] S202 The main control board accesses the peripheral devices corresponding to the first IIC bus through the CPLD / FPGA chip;
[0042] In this case, each IIC bus in the service board is connected to a CPLD / FPGA chip.
[0043] In this embodiment, a framework-type routing and switching device bus architecture block diagram is provided, such as... Figure 3 As shown, the switching device includes a primary main control board (backup main control board), a backplane, and service boards. The primary main control board, backplane, and service boards are connected by connectors. The primary main control board (backup main control board) accesses the peripheral devices of the service boards through each IIC bus. The switching device also includes a CPLD / FPGA chip, which is connected to each IIC bus and a hot-swappable chip. The hot-swappable chip is connected to the backplane and the IIC bus.
[0044] In step S201, when the main control board fails to access the corresponding peripheral device in the service board through the first IIC bus, the switching device can directly execute the CPLD / FPGA chip to shut down the hot-swappable chips between each IIC bus and the backplane, and execute the steps in step S202.
[0045] In another embodiment, when the primary main control board fails to access the corresponding peripheral device in the service board through the first IIC bus, the switching device can first enable the backup main control board, that is, switch between the primary main control board and the backup main control board. If the backup main control board can access the corresponding peripheral device in the service board normally through the first IIC bus after enabling the backup main control board, it can be determined that the primary main control board is faulty. At this time, maintenance personnel can take the main control board to the site to replace it and solve the fault problem.
[0046] In the above embodiments, the switching process between the primary and backup main control boards is lengthy and may significantly impact user services. However, the solution provided in this embodiment eliminates the need for switching between the primary and backup main control boards. Instead, it enables access to peripheral devices via the IIC bus through CPLD / FPGA chips, thus avoiding interruptions to user services caused by switching between the primary and backup main control boards and the problem of excessively long switching times.
[0047] In this embodiment, the reserved pins of the CPLD / FPGA chip can be used to connect to each IIC bus and to hot-swappable chips, such as... Figure 3 As shown, IIC1 and IIC2 are connected to the CPLD / FPGA chip, and the CPLD / FPGA chip is connected to the hot-swappable chip connected to IIC1 and the hot-swappable chip connected to IIC2, respectively.
[0048] To avoid loop problems, when all boards in the switching equipment are functioning normally, the ports connecting the CPLD / FPGA chip to each IIC are in a closed state (i.e., not enabled), and the CPLD / FPGA chip controls the hot-swap chip to be in an open state (i.e., enabled).
[0049] When all the boards in the switching equipment are functioning normally and the hot-swappable chip is in the open state, the main control board can access the peripheral devices connected to each IIC bus through the hot-swappable chip.
[0050] In this embodiment, accessing peripheral devices connected to the IIC bus includes reading and writing peripheral device information (configuration information).
[0051] In this embodiment, when the main control board fails to access the corresponding peripheral device on the service board through the first IIC bus, the maintenance personnel can disable the hot-swappable chips on each IIC bus through the CPLD / FPGA chip. After disabling the hot-swappable chips, the CPLD / FPGA chip opens the ports connected to each IIC bus, so that the maintenance personnel can try to access the corresponding peripheral device on the service board through the CPLD / FPGA chip.
[0052] In this embodiment, maintenance personnel can access the corresponding peripheral devices on the service board via the CPLD / FPGA chip through the LVDS bus.
[0053] In this embodiment, the above-described solution can also be used to locate the cause of the failure to access the corresponding peripheral device on the service board, combined with... Figure 3 As shown, the details are as follows:
[0054] 1. In one case, a primary / backup switch is performed on main control board 0 and main control board 1. If the problem disappears after the switch, it can be determined that the fault is related to the main control board. On-site maintenance personnel can replace the faulty main control board with a new one.
[0055] 2. In another scenario, if the fault persists after the primary / standby switchover, the hot-swappable chip of the corresponding IIC link can be turned off via the CPLD / FPGA of service card 2. The CPLD / FPGA can then be used to read the peripherals on the IIC link. If the fault still exists, it can be determined that service card 2 is faulty, and on-site maintenance personnel can replace the faulty service card with a new one.
[0056] 3. In another scenario, if the fault persists after executing step 1, but disappears after executing step 2, then the fault cannot be determined solely by software commands, as it is highly likely that the fault is related to the connector.
[0057] In this embodiment, the CPLD / FPGA is connected to these two IIC bus links. If one of them fails (not a problem with the service card backend), the other IIC bus can be used to read and write related peripherals (the two IIC links are directly connected inside the CPLD / FPGA) to meet emergency work requirements.
[0058] Additionally, if the LVDS link of service card 2 malfunctions, the CPLD registers can be read and written via the IIC link. If the CPLD can be read and written, the fault is most likely related to the connector or the LVDS coupling capacitor / bias resistor. If the CPLD cannot be read and written, the fault may be due to the CPLD / FPGA itself.
[0059] To simultaneously meet the location requirements of LVDS / IIC links, the CPLD / FPGA needs to be set as an IIC slave device by default. When LVDS malfunctions, the IIC link is used to assist in locating the LVDS problem. When LVDS is working properly, but one of the IIC links malfunctions, the two IIC links need to be directly connected through LVDS to continue locating the problem according to steps 1 / 2 / 3 above. When LVDS is working properly, but both IIC links malfunction, the CPLD / FPGA needs to be set as an IIC master device through LVDS, and the fault needs to be located according to steps 1 / 2 / 3 above.
[0060] As can be seen from the above embodiments, when the main control board fails to read peripheral devices through the IIC bus, it can be read through the CPLD / FPGA chip. On the one hand, it saves switching time by eliminating the need for the main control board to perform master-slave switching. On the other hand, the method in this embodiment can further determine which board among the main control board, backplane, and service board is faulty, providing a more convenient diagnostic function for network maintenance. At the same time, temporary remedial measures can be used to meet emergency work needs when a single bus problem occurs.
[0061] Based on the above method embodiments, this disclosure also provides a switching device, the switching device comprising: a primary main control board, a backplane, and service boards, wherein the primary main control board, backplane, and service boards are connected via connectors, and the primary main control board accesses peripheral devices of the service boards via various IIC buses. The switching device further comprises: a CPLD / FPGA chip, wherein the CPLD / FPGA chip is connected to each IIC bus and a hot-swappable chip, and the hot-swappable chip is connected to the backplane and the IIC bus.
[0062] The switching equipment also includes:
[0063] The judgment module is used to determine whether the main control board has successfully accessed the corresponding peripheral device in the service board through the first IIC bus.
[0064] The processing module is used to disable the hot-swappable chips between each IIC bus and the backplane via the CPLD / FPGA chip when the judgment module fails to determine the problem.
[0065] The access module is used by the main control board to access the peripheral devices corresponding to the first IIC bus through the CPLD / FPGA chip.
[0066] The CPLD / FPGA chip is connected to each IIC bus via reserved pins.
[0067] When the main control board normally accesses the corresponding peripheral device in the service board through the first IIC bus, the pins of the CPLD / FPGA chip connected to each IIC are in an disabled state.
[0068] The processing module is also used to switch the enable of the backup main control board when the main control board fails to access the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip.
[0069] The judgment module is also used to determine that the service board is faulty if the backup main control board fails to access the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip.
[0070] The processing module is further configured to switch from the primary main control board to enable the backup main control board when the primary main control board fails to access the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip.
[0071] The judgment module is also used to determine the connector failure if the backup main control board successfully accesses the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip.
[0072] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of the solution in this specification according to actual needs. Those skilled in the art can understand and implement this without creative effort.
[0073] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.
[0074] Other embodiments of this specification will readily occur to those skilled in the art upon consideration of the specification and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this specification are indicated by the following claims.
[0075] It should be understood that this specification is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this specification is limited only by the appended claims.
[0076] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.
Claims
1. A method for querying the status of a service board, characterized in that, The method includes: When the main control board fails to access the corresponding peripheral device in the service board through the first IIC bus, the hot-swappable chip between each IIC bus and the backplane is disabled through the CPLD / FPGA chip. The main control board accesses the peripheral devices corresponding to the first IIC bus through the CPLD / FPGA chip. In this case, each IIC bus in the service board is connected to a CPLD / FPGA chip.
2. The method according to claim 1, characterized in that, The CPLD / FPGA chip is connected to each IIC bus via reserved pins.
3. The method according to claim 2, characterized in that, The method further includes: When the main control board normally accesses the corresponding peripheral devices in the service board through the first IIC bus, the pins of the CPLD / FPGA chip connected to each IIC are in an disabled state.
4. The method according to claim 1, characterized in that, The method further includes: When the primary main control board fails to access the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip, the backup main control board is switched from the primary main control board to enable the backup main control board. If the backup main control board fails to access the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip, it can be determined that there is a fault in the service board.
5. The method according to claim 1, characterized in that, The method further includes: When the primary main control board fails to access the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip, the backup main control board is switched from the primary main control board to enable the backup main control board. If the backup main control board can successfully read the peripheral device after turning off the hot-swappable chip of the corresponding IIC link by accessing the external device corresponding to the first IIC bus through the CPLD / FPGA chip, then the connector failure can be determined.
6. A switching device, characterized in that, The switching equipment includes a primary control board, a backplane, and service boards. The primary control board, backplane, and service boards are connected via connectors. The primary control board accesses peripheral devices on the service boards through various IIC buses. The switching equipment also includes a CPLD / FPGA chip, which is connected to each IIC bus and a hot-swappable chip. The hot-swappable chip is connected to the backplane and the IIC bus. The switching equipment also includes: The judgment module is used to determine whether the main control board has successfully accessed the corresponding peripheral device in the service board through the first IIC bus. The processing module is used to disable the hot-swappable chips between each IIC bus and the backplane via the CPLD / FPGA chip when the judgment module fails to determine the problem. The access module is used by the main control board to access the peripheral devices corresponding to the first IIC bus through the CPLD / FPGA chip.
7. The switching device according to claim 6, characterized in that, The CPLD / FPGA chip is connected to each IIC bus via reserved pins.
8. The switching device according to claim 6, characterized in that, When the main control board normally accesses the corresponding peripheral devices in the service board through the first IIC bus, the pins of the CPLD / FPGA chip connected to each IIC are in an disabled state.
9. The switching device according to claim 6, characterized in that, The processing module is also used to switch from the primary main control board to enable the backup main control board when the primary main control board fails to access the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip. The judgment module is also used to determine that the service board is faulty if the backup main control board fails to access the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip.
10. The switching device according to claim 6, characterized in that, The processing module is also used to switch from the primary main control board to enable the backup main control board when the primary main control board fails to access the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip. The judgment module is also used to determine the connector failure if the backup main control board can successfully read the peripheral device after turning off the hot-swappable chip of the corresponding IIC link when accessing the peripheral device corresponding to the first IIC bus through the CPLD / FPGA chip.