A common-gate pixel driving circuit

Abstract

This invention discloses a common-gate pixel driving circuit, comprising: a pre-storage module and a driving module, wherein the pre-storage module includes a first transistor and a second transistor, the first source-drain of the first transistor is coupled to a data signal line, the second source-drain is coupled to a pre-storage capacitor and the second transistor, and the gate is coupled to a control signal line; the gate of the second transistor is coupled to a transfer signal line; the driving module includes a third transistor and a fourth transistor, the first source-drain of the third transistor is coupled to a first global signal, and the second source-drain is coupled to a pixel capacitor; the first source-drain of the fourth transistor is coupled to a second global signal, and the second source-drain is coupled to the pixel capacitor; the gates of the third transistor and the fourth transistor are both coupled to the second source-drain of the second transistor.

Description

Technical Field

[0001] This invention relates to the field of pixel driving technology, and more specifically to a common-gate pixel driving circuit. Background Technology

[0002] In traditional field-sequential or color-sequential display driving technologies, the backlight can only be turned on after all screen data has been written and the liquid crystal has reached a stable state. Otherwise, image distortion will occur. Therefore, the data writing and liquid crystal deflection time greatly compresses the backlight turn-on time, leading to difficulties in increasing display brightness, refresh rate, and resolution, as well as increased power consumption and backlight material costs. Therefore, how to accelerate the liquid crystal driving time and increase the backlight turn-on time is a crucial issue.

[0003] For circuits with gate-controlled drive structures, the storage capacitor requirement is much smaller compared to charge-sharing or conventional LCD pixel drive circuits. Taking conventional display circuits as an example, Cst is at least on the same order of magnitude as Clc, and in some high refresh rate products, it is even tens of times larger than Clc. Since the size of Clc is related to liquid crystal deflection, and liquid crystal deflection is voltage-dependent, and the response of liquid crystal takes time, the shorter the charging time, the less time Clc has to react to the target potential capacitor, requiring Cst to continuously supply power to it.

[0004] For a gate-controlled drive structure circuit, the data capacitor stores the gate signal Vg = Vdata within the drive transistor. When Vpixel < Vdata and Vg - Vpixel > Vth, a channel is formed. The gate-controlled drive transistor operates in the saturation region. For NMOS, Vdg = Vdd - Vg > Vth. At this point, for Vpixel, electrons will flow from Vpixel to Vdd, gradually raising the Vpixel potential until it reaches an equilibrium state close to Vgs = Vth and Vdg > Vth. Because if electrons continue to flow out at this point, Vs will increase in potential, Vgs < Vth, and the device channel will be pinched off. Furthermore, from the above driving process, it can be seen that the target charging potential is only related to the gate signal potential and not to the gate signal capacitance. Therefore, the gate signal capacitance can be made very small, which is beneficial for improving the aperture ratio. However, it also has a fatal drawback. For NMOS, if the previous frame signal is a negative frame voltage and the next frame is a positive frame voltage, the state of Vgs > Vth can be satisfied. However, if the previous frame is a positive frame voltage and the next frame is a negative frame voltage, Vgs < Vth, the channel cannot be opened, and the same gate drive process cannot be achieved.

[0005] Even if Vpixel is set to Vd during the driving process, and discharge logic is used to keep Vdd at a low potential, satisfying Vg - Vdd > Vth to achieve channel opening, the potential of Vpixel continuously decreases due to electron inflow until Vpixel - Vg = Vth. However, since the channel still exists, electrons will continue to flow into Vpixel, causing the potential to continuously decrease to Vdd. Therefore, ensuring the polarity reversal of the liquid crystal under gate control is a limitation of gate control schemes in liquid crystal applications.

[0006] In summary, traditional gate-controlled pixel driving circuits have the problem of being unable to reverse the polarity of liquid crystals. Summary of the Invention

[0007] In view of this, the present invention provides a common-gate pixel driving circuit, which solves the problem that traditional gate-controlled pixel driving circuits cannot perform liquid crystal polarity reversal by improving the circuit structure and driving timing.

[0008] To solve the above problems, the technical solution of the present invention is to adopt a common-gate pixel driving circuit, comprising: a pre-storage module and a driving module, wherein the pre-storage module includes a first transistor and a second transistor, the first source-drain of the first transistor is coupled to a data signal line, the second source-drain is coupled to a pre-storage capacitor and the second transistor, and the gate is coupled to a control signal line; the gate of the second transistor is coupled to a transfer signal line; the driving module includes a third transistor and a fourth transistor, the first source-drain of the third transistor is coupled to a first global signal, and the second source-drain is coupled to a pixel capacitor; the first source-drain of the fourth transistor is coupled to a second global signal, and the second source-drain is coupled to the pixel capacitor; the gates of the third transistor and the fourth transistor are both coupled to the second source-drain of the second transistor.

[0009] Optionally, if the third transistor is an N-type MOS transistor and the fourth transistor is a P-type MOS transistor, the second source and drain of the third transistor and the fourth transistor are both coupled to the same end of the pixel capacitor, and the other end of the pixel capacitor is coupled to a common signal line.

[0010] Optionally, both the third transistor and the fourth transistor can be configured as dual-gate transistors.

[0011] Optionally, the second gate of the third transistor is coupled to the first reference signal line and the second gate of the fourth transistor is coupled to the second reference signal line, wherein the second source and drain of the third transistor are both coupled to one end of the pixel capacitor and the second source and drain of the fourth transistor are both coupled to the other end of the pixel capacitor.

[0012] Optionally, the second gate of the third transistor is coupled to a second global signal and the second gate of the fourth transistor is coupled to a first global signal, wherein the second source and drain of the third transistor are both coupled to one end of the pixel capacitor, and the second source and drain of the fourth transistor are both coupled to the other end of the pixel capacitor.

[0013] Optionally, the end of the pre-stored capacitor furthest from the transistor is coupled to a common signal line.

[0014] Optionally, the pixel driving circuit further includes a reset module, which includes a fifth transistor. The first source-drain of the fifth transistor is coupled to a common signal, and the second source-drain is coupled to the gates of the third and fourth transistors. The gates are coupled to a reset signal line.

[0015] Optionally, during a positive polarity frame: during the backlight-on phase, the control signal jumps to a high potential, the first transistor turns on, and the data signal is stored in the pre-storage capacitor; during the backlight-off phase, the transfer signal jumps to a high potential, and the second global signal and the first global signal jump to a high potential successively, and the data signal is transmitted to the gates of the third transistor and the fourth transistor. At this time, the third transistor is turned on and the fourth transistor remains off, thereby transmitting the positive polarity data signal to the pixel capacitor through the third transistor.

[0016] Optionally, during a negative polarity frame: during the backlight-on phase, the control signal jumps to a high potential, the first transistor turns on, and the data signal is stored in the pre-storage capacitor; during the backlight-off phase, the transfer signal jumps to a high potential, and the first global signal and the second global signal successively jump to a low potential, and the data signal is transmitted to the gates of the third transistor and the fourth transistor. At this time, the third transistor is turned off and the fourth transistor is turned on, thereby transmitting the negative polarity data signal to the pixel capacitor through the fourth transistor.

[0017] The primary improvement of this invention is the common-gate pixel driving circuit, which, by setting a pre-storage capacitor in conjunction with a transistor, enables the storage of the grayscale voltage of the next frame during the backlight illumination time of the current frame. This allows all pixels to synchronously achieve grayscale voltage when the backlight is off, greatly reducing the pixel voltage writing time and relatively increasing the backlight illumination time.

[0018] Meanwhile, by coupling the gates of the third and fourth transistors to the second source and drain of the second transistor, the present invention achieves a smaller capacitor area ratio through a common gate, enabling the voltage across the liquid crystal capacitor to reverse with the frame. This solves the problem that traditional gate-controlled pixel driving circuits cannot reverse the polarity of the liquid crystal, thus avoiding the problem of liquid crystal polarization.

[0019] Furthermore, by cooperating with the third and fourth transistors, only one of the third and fourth transistors is in the conducting state in any frame, thereby reducing the rate of transistor threshold voltage drift and improving the accuracy of grayscale control of the pixel driving circuit. Attached Figure Description

[0020] Figure 1 This is a simplified circuit diagram of the pixel driving circuit of Embodiment 1 of the present invention;

[0021] Figure 2 This is a simplified driving timing diagram of the pixel driving circuit of Embodiment 1 of the present invention;

[0022] Figure 3 This is a simplified circuit diagram of the pixel driving circuit of Embodiment 2 of the present invention;

[0023] Figure 4 This is a simplified driving timing diagram of the pixel driving circuit of Embodiment 2 of the present invention;

[0024] Figure 5 This is a simplified circuit diagram of the pixel driving circuit of Embodiment 3 of the present invention. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0028] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0030] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0031] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0032] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship. Example 1

[0033] Specifically, such as Figure 1 As shown, a common-gate pixel driving circuit includes a pre-storage module and a driving module. The pre-storage module includes a first transistor M1 and a second transistor M2. The first source-drain of the first transistor M1 is coupled to a data signal line Data, and the second source-drain is coupled to a pre-storage capacitor Cst and the second transistor M2. The gate of the first transistor M1 is coupled to a control signal line Scan. The gate of the second transistor M2 is coupled to a transfer signal line Tran. The driving module includes a third transistor M3 and a fourth transistor M4. The first source-drain of the third transistor M3 is coupled to a first global signal Vdd1, and the second source-drain is coupled to a pixel capacitor Clc. The first source-drain of the fourth transistor M4 is coupled to a second global signal Vdd2, and the second source-drain is coupled to the pixel capacitor Clc. The gates of both the third transistor M3 and the fourth transistor M4 are coupled to the second source-drain of the second transistor M2.

[0034] Furthermore, if the third transistor M3 is an N-type MOS transistor and the fourth transistor M4 is a P-type MOS transistor, the second source and drain of the third transistor M3 and the fourth transistor M4 are both coupled to the same end of the pixel capacitor Clc, and the other end of the pixel capacitor Clc is coupled to the common signal line Com.

[0035] Furthermore, the end of the pre-storage capacitor Cst furthest from the transistor is coupled to the common signal line Com.

[0036] Specifically, such as Figure 2 As shown, the driving timing of the pixel driving circuit is configured as follows:

[0037] During the first frame of the positive polarity, in the backlight-on phase, the control signal jumps to a high potential line by line, the first transistor M1 turns on, and the data signal is stored in the pre-storage capacitor Cst; in the backlight-off phase, the transfer signal jumps to a high potential, and the second global signal and the first global signal jump to a high potential one after another, and the data signal is transmitted to the gates of the third transistor M3 and the fourth transistor M4. At this time, the third transistor M3 is turned on and the fourth transistor M4 remains off, so that the positive polarity data signal is transmitted to the pixel capacitor Cst through the third transistor M3.

[0038] During the second frame with negative polarity, in the backlight-on phase, the control signal jumps to a high potential, the first transistor M1 turns on, and the data signal is stored in the pre-storage capacitor Cst. In the backlight-off phase, the transfer signal jumps to a high potential, and the first global signal and the second global signal jump to a low potential successively. The data signal is transmitted to the gates of the third transistor M3 and the fourth transistor M4. At this time, the third transistor M3 is turned off and the fourth transistor M4 is turned on, thereby transmitting the negative polarity data signal to the pixel capacitor Cst through the fourth transistor M4.

[0039] Furthermore, the high potential of the control signal and the transfer signal is defined as the potential that enables the transistor to turn on, and the low potential of the control signal and the transfer signal is defined as the potential that enables the transistor to turn off; the high potential of the first global signal is defined as a potential higher than Vop-max (maximum grayscale voltage), and the low potential is defined as the same as the common signal Com; the high potential of the second global signal is defined as the same as the common signal Com, and the low potential is defined as a potential lower than -Vop-max.

[0040] Furthermore, the pixel driving circuit also includes a reset module, which includes a fifth transistor M5. The first source-drain of the fifth transistor M5 is coupled to a common signal Com, and the second source-drain is coupled to the gates of the third transistor M3 and the fourth transistor M4. The gates are coupled to the reset signal line Reset.

[0041] Specifically, when the pixel driving circuit is equipped with a reset module, the driving timing of the pixel driving circuit further includes: during the backlight off stage, the reset signal is first switched to a high potential to turn on the fifth transistor, thereby resetting the potential of the gates of the third transistor M3 and the fourth transistor M4 based on the common signal, and then the reset signal is switched to a low potential before the transfer signal is switched.

[0042] This invention, by configuring a pre-storage capacitor in conjunction with a transistor, allows the grayscale voltage of the next frame to be stored within the backlight illumination time of the current frame. This enables all pixels to synchronously achieve grayscale voltage when the backlight is off, significantly reducing pixel voltage write time and relatively increasing backlight illumination time. Simultaneously, by coupling the gates of both the third and fourth transistors to the second source-drain terminals of the second transistor, this invention achieves a smaller capacitor area ratio through a common gate configuration. This allows the voltage across the liquid crystal capacitor to invert with each frame, solving the problem of traditional gate-controlled pixel driving circuits being unable to reverse liquid crystal polarity and avoiding liquid crystal polarization issues. Furthermore, the coordination of the third and fourth transistors ensures that only one of them is active in any given frame, thereby reducing the rate of transistor threshold voltage drift and improving the accuracy of grayscale control in the pixel driving circuit. Example 2

[0043] like Figure 3 As shown, the third transistor M3 and the fourth transistor M4 can both be configured as dual-gate transistors.

[0044] Furthermore, the second gate of the third transistor M3 is coupled to the first reference signal line Ref1 and the second gate of the fourth transistor M4 is coupled to the second reference signal line Ref2. The second source and drain of the third transistor M3 are both coupled to one end of the pixel capacitor Clc, and the second source and drain of the fourth transistor M4 are both coupled to the other end of the pixel capacitor Clc.

[0045] Furthermore, such as Figure 4 As shown, the driving timing of the pixel driving circuit is configured as follows:

[0046] In the first frame, during the backlight-on phase, the control signal jumps to a high potential line by line, the first transistor M1 turns on, and the data signal is stored in the pre-storage capacitor Cst. During the backlight-off phase, the transfer signal jumps to a high potential, the first global signal and the second reference signal jump to a high potential, and the second global signal and the first reference signal jump to a normal potential. When the data signal is transmitted to the gates of the third transistor M3 and the fourth transistor M4, due to the effect of the reference signal, the Vth of the third transistor remains unchanged, while the Vth of the fourth transistor decreases. This causes the third transistor M3 to operate in the saturation region and the fourth transistor to operate in the linear region. Consequently, the data signal is transmitted to one end of the pixel capacitor Cst through the third transistor M3, and the common signal is transmitted to the other end of the pixel capacitor Cst through the fourth transistor M4, thereby completing the grayscale control of the positive frame of the pixel capacitor.

[0047] In the second frame, during the backlight-on phase, the control signal jumps to a high potential line by line, the first transistor M1 turns on, and the data signal is stored in the pre-storage capacitor Cst. During the backlight-off phase, the transfer signal jumps to a high potential, the first global signal and the second reference signal jump to a normal potential, and the second global signal and the first reference signal jump to a high potential. When the data signal is transmitted to the gates of the third transistor M3 and the fourth transistor M4, due to the effect of the reference signal, the Vth of the fourth transistor remains unchanged, while the Vth of the third transistor decreases. This causes the third transistor M3 to operate in the linear region and the fourth transistor to operate in the saturation region. Consequently, the common signal is transmitted to one end of the pixel capacitor Cst through the third transistor M3, and the data signal is transmitted to the other end of the pixel capacitor Cst through the fourth transistor M4, thereby completing the grayscale control of the negative frame of the pixel capacitor.

[0048] Furthermore, in this embodiment, the high potential of the first global signal, the second global signal, the first reference signal, and the second reference signal is higher than Vop-max (maximum grayscale voltage), and the normal potential is the same as that of the common signal Com.

[0049] This embodiment achieves a lower data range and higher operating stability by switching pixel electrodes, avoiding the problem that when the fourth transistor M4 uses PMOS (such as LTPS process), the high leakage current that may exist in the off state will cause the Vpixel to deviate from the target charging level as the circuit refresh rate decreases.

[0050] Furthermore, the pixel driving circuit also includes a reset module, which includes a fifth transistor M5. The first source-drain of the fifth transistor M5 is coupled to a common signal Com, and the second source-drain is coupled to the gates of the third transistor M3 and the fourth transistor M4. The gates are coupled to the reset signal line Reset. Example 3

[0051] like Figure 5 As shown, the third transistor M3 and the fourth transistor M4 can both be configured as dual-gate transistors.

[0052] Furthermore, the second gate of the third transistor M3 is coupled to the second global signal Vdd2 and the second gate of the fourth transistor M4 is coupled to the first global signal Vdd1. The second source and drain of the third transistor M3 are both coupled to one end of the pixel capacitor Clc, and the second source and drain of the fourth transistor M4 are both coupled to the other end of the pixel capacitor Clc.

[0053] Furthermore, the driving timing of this embodiment is similar to that of Embodiment 2, so it will not be described again.

[0054] Compared to Example 2, this embodiment combines the Vref and Vdd signal lines, further increasing the aperture ratio. At the same time, by removing the fifth transistor M5 and its corresponding signal line, the size of Cst1 can be appropriately increased, making the capacitance ratio of Cst1 / Cst2 differ by 2-3 orders of magnitude, and the voltage loss can be basically ignored.

[0055] The above describes the common-gate pixel driving circuit provided by the embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principle of the invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0056] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can implement the described functions using different methods for each specific application, but such implementation should not be considered beyond the scope of the invention. The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be implemented directly in hardware, software modules executed by a processor, or a combination of both. Software modules can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

Claims

1. A common-gate pixel driving circuit, characterized in that, include: A pre-storage module and a driving module, wherein the pre-storage module includes a first transistor (M1) and a second transistor (M2), the first source and drain of the first transistor (M1) are coupled to a data signal line (Data), the second source and drain are coupled to a pre-storage capacitor (Cst) and the second transistor (M2), and the gate is coupled to a control signal line (Scan); the gate of the second transistor (M2) is coupled to a transfer signal line (Tran). The driving module includes a third transistor (M3) and a fourth transistor (M4). The first source-drain of the third transistor (M3) is coupled to a first global signal (Vdd1); the first source-drain of the fourth transistor (M4) is coupled to a second global signal (Vdd2); the gates of both the third transistor (M3) and the fourth transistor (M4) are coupled to the second source-drain of the second transistor (M2). Both the third transistor (M3) and the fourth transistor (M4) are configured as dual-gate transistors. The second gate of the third transistor (M3) is coupled to the first reference signal line (Ref1), the second gate of the fourth transistor (M4) is coupled to the second reference signal line (Ref2), the second source and drain of the third transistor (M3) are coupled to one end of the pixel capacitor (Clc), and the second source and drain of the fourth transistor (M4) are coupled to the other end of the pixel capacitor (Clc). In the first frame, during the backlight-on phase, the control signal jumps to a high potential line by line, the first transistor (M1) is turned on, and the data signal is stored in the pre-storage capacitor (Cst); during the backlight-off phase, the transfer signal jumps to a high potential, the first global signal (Vdd1) and the second reference signal jump to a high potential, and the second global signal (Vdd2) and the first reference signal jump to a normal potential. In the second frame, during the backlight-on phase, the control signal jumps to a high potential line by line, the first transistor (M1) is turned on, and the data signal is stored in the pre-storage capacitor (Cst); during the backlight-off phase, the transfer signal jumps to a high potential, the first global signal (Vdd1) and the second reference signal jump to a normal potential, and the second global signal (Vdd2) and the first reference signal jump to a high potential.

2. The pixel driving circuit according to claim 1, characterized in that, The end of the pre-storage capacitor (Cst) away from the transistor is coupled to the common signal line (Com).

3. The pixel driving circuit according to claim 1, characterized in that, The pixel driving circuit also includes a reset module. The reset module includes a fifth transistor (M5), the first source-drain of the fifth transistor (M5) is coupled to a common signal (Com), the second source-drain is coupled to the gates of the third transistor (M3) and the fourth transistor (M4), and the gates are coupled to the reset signal line (Reset).

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