Device for preventing needle burning in FV-MI mode test of discrete device

Abstract

The invention provides a discrete device FV-MI mode test anti-needle-burning device comprising a test source which comprises a high potential and a low potential; the tested die is fixed on the chuck, and the chuck is connected with the high potential of the test source; a standard resistor is connected in series between the probe card and the low potential end of the test source, and the standard resistor is used for detecting the current in the test loop; the external standard MOSFET is low in turn-on voltage, high in withstand voltage and high in power, if current in a loop is abnormally large during testing to cause increase of voltage division of the standard resistor, the external standard MOSFET is conducted to shunt current passing through the probe card, and the current flowing through the probe card is controlled to avoid probe burning. The external standard MOSFET is conducted so as to shunt the current flowing through the probe, and the probe is prevented from being burnt by controlling the current flowing through the probe card.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a device for testing an anti-burning needle of a discrete device in FV-MI mode. Background Art

[0002] The static test items of discrete devices, such as IGSS / IDSS, are essentially FV-MI (apply voltage and measure current) mode. The IDSS test schematic is as follows Figure 1 : Short-circuit G / S, apply a specific voltage between DS, measure the leakage current at both ends to detect whether there is an abnormality between DS; the IGSS test principle diagram is as follows Figure 2 :D / S are short-circuited, a specific voltage is applied between GS, and the current in the circuit is measured to detect whether there is any abnormality in the gate oxide film.

[0003] The typical relationship between current and time when testing FV-MI with IGSS / IDSS is as follows: Figure 3 In normal testing, the voltage or current applied needs to be maintained for a period of time before the relationship diagram becomes stable.

[0004] Considering the differences of products, sufficient application time must be reserved during mass production testing to ensure that the voltage or current is stable. During this period, the die under test cannot withstand the high voltage, which will cause the current in the test loop to increase. At this time, if there is aluminum chips or other contamination at the contact point between the needle tip and the PAD (solder pad), the resistance here will increase and the partial pressure will increase. Under high voltage and high current, the temperature will continue to rise and melt more aluminum chips and other contamination, causing the resistance at the needle tip to further increase and the partial pressure to increase by only one step. Under such positive excitation feedback, the resistance at the needle tip becomes larger and the partial pressure becomes higher, and the accumulated heat becomes more and more (Q=U*I*t), which eventually causes the needle tip of the test needle card to melt and burn (a typical photo of a burning needle is shown in the figure below). Figure 4 ).

[0005] In order to solve the above problems, it is necessary to propose a new device for testing the anti-burning needle of discrete devices in FV-MI mode. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a device for preventing the needle from burning during FV-MI mode testing of discrete devices, so as to solve the problem of melting and burning of the needle tip of the test needle card in the prior art.

[0007] To achieve the above-mentioned and other related purposes, the present invention provides a device for testing a burn-proof pin of a discrete device in FV-MI mode, comprising:

[0008] A test source, which includes a high potential and a low potential;

[0009] The die under test is fixed on the chuck, and the chuck is connected to the high potential of the test source;

[0010] A probe card is connected in series with a standard resistor between the low potential end of the test source, and the standard resistor is used to detect the current in the test loop.

[0011] An externally connected standard MOSFET with a low turn-on voltage, high breakdown voltage and high power, where

[0012] During testing, if the current in the loop is abnormally large, causing the voltage division of the standard resistor to increase, the externally connected standard MOSFET is turned on to shunt the current passing through the probe card, and the current passing through the probe card is controlled to avoid burning the pins.

[0013] Preferably, the test mode is IDSS test, the source and drain terminals of the standard MOSFET are connected in parallel with the high and low potential terminals of the test source, and the gate terminal is short-circuited to the high potential of the standard resistor.

[0014] Preferably, the standard MOSFET includes: a plurality of standard MOSFETs G1 to Gn, switches KD1 to KDn are respectively connected between the drain terminals of the standard MOSFETs G1 to Gn and the high potential of the test source, switches KS1 to KSn are respectively connected between the source terminals of the standard MOSFETs G1 to Gn and the low potential of the test source, and switches KG1 to KGn are respectively connected between the drain terminals of the standard MOSFETs G1 to Gn and the high potential of the test source.

[0015] Preferably, the standard resistor includes: a plurality of resistors R1 to Rn with different resistance values, switches K1 to Kn are respectively connected in series with the resistors R1 to Rn, and a switch K0 is also connected in parallel with the resistors R1 to Rn.

[0016] Preferably, the standard resistor is used to adapt to different standard MOSFET turn-on voltages VT and test specification upper limits I. The resistance value selection needs to simultaneously satisfy Rx>VT / I / k and Rx<VT / I, where k is an adjustment coefficient, and the value range is 1 to 1000. The smaller I is, the larger the value of k is.

[0017] Preferably, the breakdown voltage of the standard MOSFET is more than 1.5 times that of the die under test.

[0018] Preferably, the low potential of the test source is grounded.

[0019] Preferably, if the voltage applied during the test is low and there is no risk of burning the pins, only the switch K0 is turned off during the entire test process, and the switches KDx / KSx / KGx remain all open, and no current control is required.

[0020] Preferably, if the test voltage is relatively high and loop current control is required, it is necessary to ensure that the breakdown voltage of the connected standard MOSFET is much greater than the actual breakdown voltage of the die under test, and then turn off the corresponding switches KDx / KSx.

[0021] Preferably, the voltage application test can be performed multiple times during the test.

[0022] Preferably, after applying the test voltage V0, wait for a short time t1, charge the capacitor in the test loop, open the switch K0, and close the corresponding switches Kx and KGx; after waiting for a sufficient t0 time, measure the leakage current I1 normally, and calculate the voltage division of the standard resistor: Vr1 = I1*Rx.

[0023] Preferably, the criteria for determining whether to conduct the second test are: Vr1 / V0>B1% and Vr1>=S1, and the first test current is within the specification, wherein B1 and S1 are set to fixed values ​​in the program according to the test accuracy requirements.

[0024] Preferably, the judgment criteria for whether to perform subsequent multiple tests are: Vrx / V0>B1% and Vrx>=S1, and the last test current is within the specification, and Vrx is defined as the current test voltage division value of the standard resistor Rx minus the last test voltage division value, where B1 and S1 are set to fixed values ​​in the program according to the test accuracy requirements.

[0025] Preferably, if the divided voltage Vr1 of the standard resistor is small or I1 exceeds the upper limit of the specification, I1 is output as the actual leakage value of the die under test.

[0026] Preferably, if the voltage division Vr1 value of the standard resistor is large and I1 does not exceed the upper limit of the specification and I*Rx is large, re-apply the voltage: V1=V0+Vr1, re-measure the leakage I2, and then calculate the voltage division of the standard resistor at this time: Vr2=I2*Rx; define Vr21=Vr2-Vr1; if I2 exceeds the upper limit of the specification or the value of Vr21 is small, I2 is output as the actual leakage value of the die under test; if the value of Vr21 is large and I2 does not exceed the upper limit of the specification and I*Rx is large, re-apply the voltage: V2=V0+Vr2, re-measure the leakage I3, and repeat the above judgment logic to determine whether to perform the next test.

[0027] Preferably, the t1 time is set according to the debugging result and does not exceed 2ms.

[0028] Preferably, the t0 time is set according to product characteristics, generally between 2ms and 2000ms.

[0029] Preferably, when the voltage V=V0+I*Rx is applied, the current test value is directly output as the actual leakage value of the die under test without subsequent retesting.

[0030] Preferably, the conditions for setting the applied voltage V = V0 + I*Rx include: the applied voltage of the product can be greater than a preset value, or I*Rx / V0 < B2% and I*Rx < S2 are satisfied, where the values of B2 and S2 are set according to the product characteristics.

[0031] As described above, the device for preventing needle burning in the FV-MI mode test of discrete devices of the present invention has the following beneficial effects:

[0032] The externally connected standard MOSFET of the present invention is turned on to shunt the current passing through the probe, and the current passing through the probe card is controlled to avoid needle burning. Description of the Drawings

[0033] Figure 1 Schematic diagram showing the IDSS test principle of the prior art;

[0034] Figure 2 Schematic diagram showing the IGSS test principle of the prior art;

[0035] Figure 3 Schematic diagram showing the typical current change with time during the IGSS / IDSS test FV-MI of the prior art;

[0036] Figure 4 Schematic diagram showing the needle burning of the prior art;

[0037] Figure 5 Schematic diagram showing the IDSS test circuit of the present invention. Detailed Embodiments

[0038] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0039] The present invention provides a device for preventing needle burning in the FV-MI mode test of discrete devices, including:

[0040] A test source, which includes a high potential and a low potential;

[0041] A die under test fixed on a chuck, and the chuck is connected to the high potential of the test source;

[0042] A probe card, in which a standard resistor is connected in series between the probe card and the low potential end of the test source, and the standard resistor is used to detect the current in the test circuit;

[0043] An externally connected standard MOSFET with a low turn-on voltage, high breakdown voltage, and high power, where,

[0044] When testing, if the current in the circuit is abnormally large, causing the voltage division of the standard resistor to increase, the externally connected standard MOSFET is turned on to shunt the current passing through the probe card, and the current passing through the probe card is controlled to avoid burning the pins. The test modes include IDSS test, IGSS test, etc.

[0045] In some embodiments, refer to Figure 5 , the test mode is IDSS test. The source and drain terminals of the standard MOSFET are connected in parallel with the high and low potential terminals of the test source, and the gate terminal is short-circuited to the high potential of the standard resistor.

[0046] In some embodiments, the standard MOSFET includes: a plurality of standard MOSFETs G1 to Gn. There are switches KD1 to KDn respectively connected between the drain terminals of the standard MOSFETs G1 to Gn and the high potential of the test source, and switches KS1 to KSn respectively connected between the source terminals of the standard MOSFETs G1 to Gn and the low potential of the test source. There are switches KG1 to KGn respectively connected between the drain terminals of the standard MOSFETs G1 to Gn and the high potential of the test source.

[0047] In some embodiments, the standard resistor includes: a plurality of resistors R1 to Rn with different resistance values. Switches K1 to Kn are respectively connected in series with the resistors R1 to Rn, and a switch K0 is also connected in parallel with the resistors R1 to Rn. When performing test items such as IDSS / IGSS in the FV-MI mode, assuming the upper limit condition of the specification is I, a suitable resistor Rx is selected according to the VT (turn-on / threshold voltage) of the standard MOSFET and I.

[0048] The resistor / standard MOSFET with low turn-on voltage and high breakdown voltage inserted into the test circuit should be selected according to the actual test conditions.

[0049] During the formal mass production test process, first turn off the corresponding KDx / KSx and K0 according to the test conditions.

[0050] In some embodiments, the standard resistor is used to adapt to different turn-on voltages VT of the standard MOSFET and the upper limit I of the test specification. The resistance value selection needs to satisfy both Rx > VT / I / k and Rx < VT / I, where k is an adjustment coefficient, and the value range is 1 to 1000. The smaller I is, the larger the value of k is.

[0051] In some embodiments, the breakdown voltage of the standard MOSFET is more than 1.5 times that of the die under test.

[0052] In some embodiments, the low potential of the test source is grounded.

[0053] In some embodiments, if the voltage applied during the test is low and there is no risk of burning the needle, only switch K0 is closed during the entire test process, and switches KDx / KSx / KGx remain all disconnected, without the need for current control.

[0054] In some embodiments, if the test voltage is relatively high and loop current control is required, it is necessary to ensure that the withstand voltage of the connected standard MOSFET is much greater than the actual withstand voltage of the die being tested, and then turn off the corresponding switch KDx / KSx.

[0055] In some embodiments, the voltage application test may be performed multiple times during the test (with the additional benefit of preventing voltage overshoot).

[0056] In some embodiments, after applying the test voltage V0, after waiting for a short time t1, the capacitor in the test loop is charged, the switch K0 is opened, and the corresponding switches Kx and KGx are closed; after waiting for a sufficient t0 time, the leakage current I1 is measured normally, and the voltage division of the standard resistor is calculated: Vr1 = I1*Rx.

[0057] In some embodiments, the criteria for determining whether to conduct a second test are: Vr1 / V0>B1% and Vr1>=S1, and the current of the first test is within the specification, where B1 and S1 are set to fixed values ​​in the program according to the test accuracy requirements. For example, B1=1, S1=0.1. (If B1>100 and S1>VT are set, the next test will definitely not be triggered)

[0058] In some embodiments, the criteria for determining whether to conduct subsequent multiple tests are: Vrx / V0>B1% and Vrx>=S1, and the last test current is within the specification, Vrx is defined as the current test voltage division value of the standard resistor Rx minus the last test voltage division value, where B1 and S1 are set to fixed values ​​in the program according to the test accuracy requirements. For example, B1=1, S1=0.1. (If B1>100 and S1>VT are set, the next test will definitely not be triggered).

[0059] In some embodiments, if the divided voltage Vr1 of the standard resistor is small or I1 exceeds the upper specification limit, I1 is output as the actual leakage value of the die under test.

[0060] In some embodiments, if the voltage division value Vr1 of the standard resistor is large, I1 does not exceed the specification upper limit, and I*Rx is large, apply the voltage again: V1 = V0 + Vr1, measure the leakage current I2 again, and then calculate the voltage division of the standard resistor at this time: Vr2 = I2*Rx; define Vr21 = Vr2 - Vr1; if I2 exceeds the specification upper limit or the value of Vr21 is small, output I2 as the actual leakage current value of the DUT (device under test); if the value of Vr21 is large, I2 does not exceed the specification upper limit, and I*Rx is large, apply the voltage again: V2 = V0 + Vr2, measure the leakage current I3 again, and repeat the above judgment logic to determine whether to perform the next test. If the product has extremely high requirements for test accuracy, continue to repeat the logic of this step for multiple tests (which additionally brings the benefit of preventing voltage overshoot).

[0061] In some embodiments, the t1 time is set according to the debugging result, and it does not exceed 2 ms, which is mainly to charge the capacitor in the test circuit.

[0062] In some embodiments, the t0 time is set according to the product characteristics, generally in the range of 2 ms to 2000 ms.

[0063] In some embodiments, when the applied voltage V = V0 + I*Rx, the current test value is directly output as the actual leakage current value of the DUT without subsequent re-testing.

[0064] In some embodiments, the conditions for setting the applied voltage V = V0 + I*Rx include: the voltage applied to the product can be greater than the preset value, or satisfy I*Rx / V0 < B2% and I*Rx < S2, where the values of B2 and S2 are set according to the product characteristics.

[0065] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0066] In summary, the externally connected standard MOSFET of the present invention is turned on to shunt the current passing through the probe, and the current flowing through the probe card is controlled to avoid pin burning. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A device for testing the anti-burning needle of discrete devices in FV-MI mode, characterized in that: Comprising: A test source, which includes a high potential and a low potential; The die under test fixed on a chuck, and the chuck is connected to the high potential of the test source; A probe card, with a standard resistor connected in series between it and the low potential end of the test source, and the standard resistor is used to detect the current in the test loop; An externally connected standard MOSFET with a low turn-on voltage, high breakdown voltage and high power, where During testing, if the current in the loop is abnormally large, causing the voltage division of the standard resistor to increase, the externally connected standard MOSFET is turned on to shunt the current passing through the probe card, and the current passing through the probe card is controlled to avoid burning the pins.

2. The device for testing the anti-burning needle of discrete device in FV-MI mode according to claim 1, characterized in that: The test mode is IDSS test, the source and drain ends of the standard MOSFET are connected in parallel with the high and low potential ends of the test source, and the gate end is short-circuited to the high potential of the standard resistor.

3. The device for testing the anti-burning needle of discrete device in FV-MI mode according to claim 2, characterized in that: The standard MOSFET includes: a plurality of standard MOSFETs G1 to Gn, and switches KD1 to KDn are respectively connected between the drain ends of the standard MOSFETs G1 to Gn and the high potential of the test source, and switches KS1 to KSn are respectively connected between the source ends of the standard MOSFETs G1 to Gn and the low potential of the test source, and switches KG1 to KGn are respectively connected between the drain ends of the standard MOSFETs G1 to Gn and the high potential of the test source.

4. The device for testing the anti-burning needle of discrete device in FV-MI mode according to claim 3, characterized in that: The standard resistor includes: a plurality of resistors R1 to Rn with different resistance values, switches K1 to Kn are respectively connected in series with the resistors R1 to Rn, and a switch K0 is also connected in parallel with the resistors R1 to Rn.

5. The device for testing the anti-burning pin of discrete device in FV-MI mode according to claim 4, characterized in that: The standard resistor is used to adapt to different standard MOSFET turn-on voltages VT and test specification upper limits I. The resistance value selection needs to simultaneously satisfy Rx>VT / I / k and Rx<VT / I, where k is an adjustment coefficient, and the value range is 1 to 1000. The smaller I is, the larger the value of k is.

6. The device for testing the anti-burning needle of discrete device in FV-MI mode according to claim 1, characterized in that: The breakdown voltage of the standard MOSFET is more than 1.5 times that of the die under test.

7. The device for testing the anti-burning needle of discrete device in FV-MI mode according to claim 1, characterized in that: The low potential of the test source is grounded.

8. The device for testing the anti-burning pin of discrete device in FV-MI mode according to claim 4, characterized in that: If the voltage applied during the test is low and there is no risk of burning the pins, then only switch K0 is closed during the entire test process, and switches KDx / KSx / KGx all remain open, and no current control is required.

9. The device for testing the anti-burning pin of discrete device in FV-MI mode according to claim 4, characterized in that: If the test voltage is relatively high and loop current control is required, it is necessary to ensure that the breakdown voltage of the connected standard MOSFET is much greater than the actual breakdown voltage of the die under test, and then turn off the corresponding switches KDx / KSx.

10. The device for testing the anti-burning pin of discrete device in FV-MI mode according to claim 4, characterized in that: Multiple voltage application tests can be performed during the test.

11. The device for testing the anti-burning pin of discrete device in FV-MI mode according to claim 10, characterized in that: After applying the test voltage V0, wait for a short time t1 to charge the capacitor in the test loop, turn on switch K0, turn off the corresponding switches Kx and KGx; after waiting for a sufficient time t0, measure the leakage current I1 normally, and calculate the voltage division of the standard resistor: Vr1 = I1*Rx.

12. The device for testing the anti-burning pin of discrete device in FV-MI mode according to claim 11, characterized in that: The judgment criterion for whether to perform a second test is: Vr1 / V0>B1% and Vr1>=S1, and the current in the first test is within the specification, where B1 and S1 are fixed values set in the program according to the test accuracy requirements.

13. The device for testing the anti-burning pin of discrete device in FV-MI mode according to claim 12, characterized in that: The criteria for determining whether to conduct subsequent multiple tests are as follows: Vrx / V0 > B1% and Vrx >= S1, and the current of the previous test is within the specification. Define Vrx as the difference between the current test voltage division value of the standard resistor Rx and the previous test voltage division value. Here, B1 and S1 are set as fixed values in the program according to the test accuracy requirements.

14. The device for testing the anti-burning pin of discrete device in FV-MI mode according to claim 13, characterized in that: If the voltage division Vr1 of the standard resistor is small or I1 exceeds the upper limit of the specification, I1 is output as the actual leakage value of the die under test.

15. The device for testing the anti-burning pin of discrete device in FV-MI mode according to claim 13, characterized in that: If the voltage division Vr1 value of the standard resistor is large, I1 does not exceed the upper limit of the specification, and I*Rx is large, apply the voltage again: V1 = V0 + Vr1, measure the leakage current I2 again, and then calculate the voltage division of the standard resistor at this time: Vr2 = I2*Rx; define Vr21 = Vr2 - Vr1; if I2 exceeds the upper limit of the specification or the Vr21 value is small, I2 is output as the actual leakage value of the die under test; if the Vr21 value is large, I2 does not exceed the upper limit of the specification, and I*Rx is large, apply the voltage again: V2 = V0 + Vr2, measure the leakage current I3 again, and repeat the above judgment logic to determine whether to conduct the next test.

16. The device for testing the anti-burning pin of discrete device in FV-MI mode according to claim 11, characterized in that: The t1 time is set according to the debugging results and does not exceed 2 ms.

17. The device for testing the anti-burning pin of discrete device in FV-MI mode according to claim 11, characterized in that: The t0 time is set according to the product characteristics and is generally between 2 ms and 2000 ms.

18. The device for testing the anti-burning pin of discrete device in FV-MI mode according to claim 11, characterized in that: When the applied voltage V = V0 + I*Rx, the current test value is directly output as the actual leakage value of the die under test without subsequent re - testing.

19. The device for testing the anti-burning pin of discrete device in FV-MI mode according to claim 18, characterized in that: The conditions for setting the applied voltage V = V0 + I*Rx include: the applied voltage of the product can be greater than the preset value, or satisfy I*Rx / V0 < B2% and I*Rx < S2, where the values of B2 and S2 are set according to the product characteristics.

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