I2C bus fault injection system and method and storage medium

Abstract

The invention discloses an I2C bus fault injection system and method and a storage medium. Comprising an electrical fault injection module, a protocol data injection module, a fault switching module and an injection control module, the electrical fault injection module is configured to generate a fault voltage according to the electrical fault configuration data; the protocol data injection module is set to generate an I2C bus digital signal according to protocol data to be tested; the fault switching module is set to control the fault voltage output by the electrical fault injection module or the I2C bus digital signal output by the protocol data injection module to be switched to be communicated with the tested I2C bus equipment according to the electrical fault injection control signal; the injection control module is configured to generate electrical fault configuration data and electrical fault injection control signals according to the upper computer instruction data. According to the scheme, the electrical fault and / or the protocol data fault are / is injected into the I2C bus according to the external simulation fault configuration based on the electrical characteristics and the protocol characteristics of the I2C bus signal, so that the test completeness and the automation level of the I2C bus system are improved.

Description

Technical Field

[0001] This article involves I 2 C bus testing technology, especially an I 2 C-bus fault injection system, method and storage medium. Background Art

[0002] I 2 The I2C bus is generally used in equipment sensor interfaces, programmable peripheral chips, and display interfaces. It is widely used in equipment information communication due to its simplified connection, multi-device capability, scalability, low cost, high reliability, and flexibility. 2 C fault injection test platform to simulate possible interference and failures, and more strictly test the stability of information modules during data transmission. Faults are injected on demand to fully test I 2 C equipment, which is beneficial to improve I 2 C Equipment robustness and reliability. Summary of the invention

[0003] The present application embodiment provides a kind of I 2 C bus fault injection system, method and storage medium based on I 2 The electrical characteristics and protocol characteristics of the C bus signal are used to inject electrical faults and / or protocol data faults into the I 2 C bus, ensuring that the I 2 C The testing completeness of equipment and systems has improved the level of automated testing.

[0004] This application provides an I 2 C-bus fault injection system, comprising:

[0005] An electrical fault injection module, a protocol data injection module, a fault switching module and an injection control module;

[0006] The electrical fault injection module is configured to generate a fault voltage according to the electrical fault configuration data;

[0007] The protocol data injection module is configured to generate I 2 C bus digital signal;

[0008] The fault switching module is configured to control the fault voltage output by the electrical fault injection module or the I output by the protocol data injection module according to the electrical fault injection control signal. 2 C bus digital signal is switched to connect to the tested I 2 C bus devices;

[0009] The injection control module is configured to generate the electrical fault configuration data and the electrical fault injection control signal according to host computer instruction data.

[0010] This application also provides I 2 C bus fault injection method, including:

[0011] According to the electrical fault injection control signal, the fault voltage output by the electrical fault injection module or the I output by the protocol data injection module is controlled. 2 C bus digital signal is switched to connect to the tested I 2 C bus devices;

[0012] Wherein, the fault voltage is generated by the electrical fault injection module according to the electrical fault configuration data; 2 The C bus digital signal is generated by the protocol data injection module according to the protocol data to be tested;

[0013] The electrical fault configuration data and the electrical fault injection control signal are generated according to host computer instruction data.

[0014] The present application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the I described in any embodiment of the present application. 2 C-bus fault injection method.

[0015] Compared with the related art, the present application scheme has changed the traditional 2 In the I C bus test solution, the method of artificial simulation of electrical faults overcomes the inconvenience of artificial simulation, can realize the on-demand combination of electrical faults and protocol faults, and more comprehensive electrical fault tests, effectively ensuring the I 2 C The testing completeness of equipment and systems has improved the level of automated testing.

[0016] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0018] Figure 1 This is one of the embodiments of the present application. 2 C bus fault injection system structure diagram;

[0019] Figure 2Another embodiment of the present application is 2 C bus fault injection system structure diagram;

[0020] Figure 3 This is a schematic diagram of a SPDT switch connection in an embodiment of the present application;

[0021] Figure 4 Another embodiment of the present application is 2 C bus fault injection system structure diagram;

[0022] Figure 5 This is one of the embodiments of the present application. 2 C-bus fault injection method. DETAILED DESCRIPTION

[0023] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0024] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0025] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0026] I 2 In the C bus and system integration joint debugging test, comprehensive simulation of possible interference and failures is very important for improving the reliability and robustness of equipment and systems. 2 C bus and system faults are generally divided into electrical layer faults and protocol layer faults. Protocol faults refer to violations of I 2 The faults specified in the C communication protocol usually involve logical errors or incorrect operations in the data transmission process, such as bit data errors related to the start bit / data bit / stop bit, etc. Electrical faults refer to electrical problems at the physical level, usually involving abnormalities in physical parameters such as signal voltage and current, such as abnormal voltage values ​​corresponding to high and low levels, etc.

[0027] The present application embodiment provides a kind of I 2 C bus fault injection system 100, such as Figure 1 As shown, including:

[0028] An electrical fault injection module 110, a protocol data injection module 120, a fault switching module 130 and an injection control module 140;

[0029] The electrical fault injection module 110 is configured to generate a fault voltage according to the electrical fault configuration data;

[0030] The protocol data injection module 120 is configured to generate I 2 C bus digital signal;

[0031] The fault switching module 130 is configured to control the fault voltage output by the electrical fault injection module 110 or the I output by the protocol data injection module 120 according to the electrical fault injection control signal. 2 C bus digital signal is switched to connect to the tested I 2 C bus device 200;

[0032] The injection control module 140 is configured to generate the electrical fault configuration data and the electrical fault injection control signal according to host computer instruction data.

[0033] It can be understood that the protocol data injection module 120 converts the protocol data to be tested from the injection control module 140 into a signal that conforms to I 2 C protocol SDA (data line) and SCL (clock line) signals, that is, the I 2 C-bus digital signals.

[0034] In some exemplary embodiments, the injection control module 140 is connected to the host computer via a PCI bus to receive host computer instruction data; or, is connected to the host computer via a USB interface to receive host computer instruction data. Optionally, other types of interfaces may also be used to interact with the host computer, not limited to the aspects of the examples of this application.

[0035] In some exemplary embodiments, the injection control module 140 is an FPGA module, which interacts with the host computer through the PCI bus, receives the host computer instruction data, and generates electrical fault configuration data to control the electrical fault injection module to generate I 2 C-bus fault injection voltage.

[0036] You can know that I 2 The I2C bus is a digital interface bus, also known as the I2C bus, and its default level standard is generally TTL or LVTTL level. The fault voltage described in the embodiment of the present application is a voltage value outside the standard voltage range defined by the specification. By injecting fault voltages with different offset degrees, the I2C bus can be fully tested. 2 C-bus devices' fault tolerance and device stability in the event of a fault.

[0037] In some exemplary embodiments, the host computer instruction data includes: the protocol data to be tested, a fault level identifier and a fault level offset level; wherein the fault level identifier includes: a high level or a low level; and the fault level offset level indicates the degree of offset of the fault level compared to the standard level.

[0038] The protocol data to be tested includes: 2 C protocol data, or a faulty I 2 C protocol data. Accordingly, the protocol data injection module generates I 2 C bus digital signal, corresponding to the correct I 2 C bus digital signal, or an I 2 C bus digital signal. It can be understood that when the protocol data to be tested is correct I 2In the case of C protocol data, electrical faults (also called level faults) are injected to test the case where only electrical faults exist. 2 In the case of C protocol data, no electrical fault is injected, and the case where only the protocol fault exists can be tested; when the protocol data to be tested is the fault I 2 In the case of C protocol data, electrical faults are injected to test the presence of protocol faults and electrical faults; when the protocol data to be tested is correct I 2 In the case of C protocol data, no electrical fault is injected, and the correct protocol data can be tested without electrical fault. 2 C bus device testing.

[0039] For example, for certain service-related data, the correct protocol data is "10001010", and the protocol data to be tested may be "10001010", or may be faulty protocol data "10001000" or "10001001" which introduces one or more errors.

[0040] Among them, the fault level is marked as high level, indicating that this test is for I 2 The high level of the C bus signal injects an electrical fault; the fault level is marked as a low level, indicating that this test is for I 2 A low level on the C-bus signal injects an electrical fault.

[0041] The fault level offset level indicates the degree of offset of the injected fault level compared to the standard level range, including positive offset or negative offset. A positive offset indicates a level higher than the standard level, and a negative offset indicates a level lower than the standard level. Each fault offset level corresponds to an offset, which may be the absolute value of the voltage difference compared to the standard voltage, or the voltage difference ratio; the offset difference between adjacent fault offset levels may be equal or unequal, and may be flexibly set according to the test needs, and is not limited to a specific aspect.

[0042] In some exemplary embodiments, the offset difference between adjacent fault offset levels is a set voltage value, which is called a fault level adjustment accuracy, indicating the variation range of the fault voltage value that the fault level can generate based on the standard voltage range.

[0043] For example, the fault level adjustment accuracy is 0.1V, and the high level range of the standard voltage is 4V-5V. The fault voltage value for the positive offset of the high level can be 5.1V, 5.2V, 5.3V, ..., etc., and the fault voltage value for the negative offset of the high level can be 3.9V, 3.8V, 3.7V, ..., etc. More examples are not listed here one by one.

[0044] In some exemplary embodiments, the fault level offset level is a level indicated by an integer, where a value greater than 0 indicates a positive offset, and a value less than 0 indicates a negative offset, for example, -3, -2, -1, 1, 2, 3, and the like.

[0045] In some exemplary embodiments, the electrical fault configuration data is a target voltage value. The electrical fault injection module generates a corresponding fault voltage according to the target voltage value, and then injects I 2 C bus to test the fault tolerance or reliability of the device under test for the target voltage value.

[0046] In some exemplary embodiments, the injection control module is configured to generate a target voltage value higher than a standard high level range when the fault level indicator is a high level and the fault level offset level is a positive offset;

[0047] When the fault level indicator is a high level and the fault level offset level is a negative offset, generating a target voltage value lower than a standard high level range;

[0048] and / or,

[0049] The injection control module is configured to generate a target voltage value higher than a standard low level range when the fault level indicator is a low level and the fault level offset level is a positive offset;

[0050] When the fault level indicator is a low level and the fault level offset level is a negative offset, a target voltage value lower than a standard low level range is generated.

[0051] It can be understood that the fault level indicator indicates whether the current test is for high-level electrical fault injection or low-level electrical fault injection. When the electrical fault is injected at a high level, the target voltage value is determined based on the standard level range of the high level; when the fault level offset level is positive, the target voltage value is determined based on the upper limit of the standard level range of the high level and the fault level offset level, and when the fault level offset level is negative, the target voltage value is determined based on the lower limit of the standard level range of the high level and the fault level offset level.

[0052] When injecting an electrical fault at a low level, the target voltage value is determined based on the standard level range of the low level; when the fault level offset level is positive, the target voltage value is determined based on the upper limit of the standard level range of the low level and the fault level offset level; when the fault level offset level is negative, the target voltage value is determined based on the lower limit of the standard level range of the low level and the fault level offset level.

[0053] The specific value of the standard level range varies according to different electrical standards; the standard level range can be a value or a range of values, and is not limited to a specific range.

[0054] In some exemplary embodiments, the target voltage value is determined based on a standard level range, according to a fault level identifier, a fault level offset grade, and a fault level adjustment accuracy.

[0055] For example, the fault level offset level is an integer indicating the level L = -3, -2, -1, 1, 2, 3, the fault level adjustment accuracy A = 0.1V, the high level range of the standard voltage is 4V-5V, and the low level range of the standard voltage is 0V-1V. If the fault level is marked as a high level, when L is greater than 0, the target voltage value = 5 + L × 0.1, for example, if the fault level is marked as a high level, when L is less than 0, the target voltage value = 4 + L × 0.1; for example, L = -3, the target voltage value = 4-3 × 0.1 = 3.7V, L = 1, the target voltage value = 5 + 1 × 0.1 = 5.1V. If the fault level is marked as a low level and L is greater than 0, the target voltage value = 1 + L × 0.1. For example, if the fault level is marked as a low level and L is less than 0, the target voltage value = 0 + L × 0.1; for example, L = -3, the target voltage value = 0-3 × 0.1 = -0.3V, L = 1, the target voltage value = 1 + 1 × 0.1 = 1.1V.

[0056] In some exemplary embodiments, a scheme of looking up an offset mapping table or other mapping function calculation may also be adopted to determine the target voltage value based on the standard level range, the fault level identifier and the fault level offset level. That is, the offset is determined based on the fault level identifier and the fault level offset level, and then the target voltage value is determined based on the standard level range, the fault level identifier and the offset. It is not limited to the specific manner of the examples of this application.

[0057] In some exemplary embodiments, Figure 2 As shown, the electrical fault injection module 110 includes: a digital-to-analog conversion DA unit 1110 and a drive filter unit 1120; the DA unit 1110 is configured to generate an initial fault voltage according to the electrical fault configuration data; the drive filter unit 1120 is configured to amplify and / or filter the initial fault voltage to obtain the fault voltage.

[0058] In some exemplary embodiments, the injection control module 140 is configured to generate the electrical fault injection control signal according to the first set value in the protocol data to be tested when the fault level indicator is a high level, so as to control the fault voltage output by the electrical fault injection module to be connected to the test I 2 C bus devices;

[0059] and / or,

[0060] The injection control module is set 140 to generate the electrical fault injection control signal according to the second set value in the protocol data to be tested when the fault level indicator is a low level, so as to control the fault voltage output by the electrical fault injection module to be connected to the tested I 2 C-bus device.

[0061] In some exemplary embodiments, the first set value is 1, and the second set value is 0. That is, when the fault level indicator is a high level, the test I 2 C bus and the tested I 2 C bus device, the bit period of the injected high-level fault is indicated by the bit position of "1" in the protocol data to be tested; when the fault level is marked as low level, this test I 2 C bus and the tested I 2 C-bus device, the bit period of the injected low-level fault is indicated by the bit position of "0" in the protocol data to be tested.

[0062] For example, when the protocol data to be tested is "10001010", and the fault level indicator is a high level, it indicates that the current test is a high level fault injection. The injection control module generates an electrical fault injection control signal in the clock cycle (also called a bit cycle) corresponding to the 1st, 5th, and 7th bits, so that the fault voltage (high voltage) output by the electrical fault injection module passes through I 2 C bus connectivity is tested 2 When the fault level indicator is low, it indicates that the current test is low-level fault injection. The injection control module generates an electrical fault injection control signal in the clock cycle corresponding to the 2nd, 3rd, 4th, 6th, and 8th bits, so that the fault voltage (low voltage) output by the electrical fault injection module passes through I 2 C bus connectivity is tested 2 C-bus device.

[0063] In some exemplary embodiments, the host computer instruction data further includes: an electrical fault injection bit indication for indicating a bit for electrical fault injection for the protocol data to be tested;

[0064] The injection control module is configured to generate the electrical fault injection control signal according to the electrical fault injection bit indication when the fault level indicator is a high level or a low level, so as to control the fault voltage output by the electrical fault injection module to be connected to the test I 2 C-bus device.

[0065] Wherein, when the fault level is identified as a high level, the fault high voltage output by the electrical fault injection module is injected; when the fault level is identified as a low level, the fault low voltage output by the electrical fault injection module is injected.

[0066] It can be seen that the electrical fault injection bit indication is used to indicate which bits in the protocol data to be tested are to be subjected to electrical fault injection. In some exemplary embodiments, the electrical fault injection bit indication includes multiple indication bits, which correspond one-to-one to the multiple bits included in the protocol data to be tested, and each indication bit indicates whether the corresponding bit in the protocol data to be tested is injected with an electrical fault; or, other methods are used to indicate which one or more specific bits in the protocol data to be tested will be injected with an electrical fault.

[0067] In some exemplary embodiments, the electrical fault injection bit indication is determined based on the protocol data to be tested; when the fault level is identified as a high level, the electrical fault injection bit indication is used to indicate at least one bit corresponding to a first set value in the protocol data to be tested; when the fault level is identified as a low level, the electrical fault injection bit indication is used to indicate at least one bit corresponding to a second set value in the protocol data to be tested.

[0068] For example, the protocol data to be tested is "10001010", the electrical fault injection bit indication is "10000000" (1 indicates injection, 0 indicates no injection), and when the fault level indicator is a high level, it indicates that the current test is a high level fault injection, and the injection control module generates an electrical fault injection control signal in the clock cycle (also called the bit cycle) corresponding to the first bit, so that the fault voltage (high voltage) output by the electrical fault injection module passes through I 2 C bus connectivity is tested 2 For another example, the protocol data to be tested is "10001010", the electrical fault injection bit indication is "01100001" (1 indicates injection, 0 indicates no injection), and when the fault level indicator is low level, it indicates that the current test is low level fault injection, and the injection control module generates an electrical fault injection control signal in the clock cycle corresponding to the 2nd, 3rd, and 8th bits, so that the fault voltage (low voltage) output by the electrical fault injection module passes through I 2 C bus connectivity is tested 2 C-bus device.

[0069] It can be understood that in some exemplary embodiments, when the fault level identifier has been determined, whether a corresponding electrical fault is injected into a specific bit in the protocol data to be tested is determined according to the electrical fault injection bit indication corresponding to the bit.

[0070] In some exemplary embodiments, the host computer instruction data further includes: an electrical fault injection bit indication for indicating a bit for electrical fault injection for the protocol data to be tested;

[0071] The injection control module is configured to generate the electrical fault injection control signal according to the first set value in the protocol data to be tested and the corresponding electrical fault injection bit indication when the fault level indicator is at a high level, so as to control the fault voltage output by the electrical fault injection module to be connected to the tested I 2 C bus devices;

[0072] and / or,

[0073] The injection control module is configured to generate the electrical fault injection control signal according to the second set value in the protocol data to be tested and the corresponding electrical fault injection bit indication when the fault level indicator is at a low level, so as to control the fault voltage output by the electrical fault injection module to be connected to the tested I 2 C-bus device.

[0074] It can be seen that the electrical fault injection control signal is finally generated according to the fault level identifier, the first set value / the second set value in the protocol data to be tested, and the electrical fault injection bit indication.

[0075] In some exemplary embodiments, when the fault level indicator is a high level, a certain bit in the protocol data to be tested is a first set value, and the corresponding electrical fault injection bit indicates that the bit is injected with an electrical fault, then the electrical fault injection control signal is generated for the bit to control the fault voltage output by the electrical fault injection module to be connected to the tested I 2 C bus device; if a certain bit in the protocol data to be tested is the first set value, but the corresponding electrical fault injection bit indicates that the bit does not inject an electrical fault, then the electrical fault injection control signal is not generated for the bit. In some exemplary embodiments, when the fault level is identified as a high level, a certain bit in the protocol data to be tested is not the first set value, although the corresponding electrical fault injection bit indicates that the bit injects an electrical fault, because the bit is not the first set value, the electrical fault injection condition is not met. In these cases, the injected fault voltage is regarded as a fault voltage for a high level, and the voltage value is the target voltage value.

[0076] In some exemplary embodiments, when the fault level indicator is a low level, a certain bit in the protocol data to be tested is a second set value, and the corresponding electrical fault injection bit indicates that the bit is injected with an electrical fault, then the electrical fault injection control signal is generated for the bit to control the fault voltage output by the electrical fault injection module to be connected to the tested I 2 C bus device; if a certain bit in the protocol data to be tested is the second set value, but the corresponding electrical fault injection bit indicates that the bit does not inject an electrical fault, then the electrical fault injection control signal is not generated for the bit. In some exemplary embodiments, when the fault level is identified as a low level, a certain bit in the protocol data to be tested is not the second set value, although the corresponding electrical fault injection bit indicates that the bit injects an electrical fault, because the bit is not the second set value, the electrical fault injection condition is not met. In these cases, the injected fault voltage is regarded as a fault voltage for a low level, and the voltage value is the target voltage value.

[0077] For example, the protocol data to be tested is "10001010", the electrical fault injection bit indication is "10000000" (1 indicates injection, 0 indicates no injection), and when the fault level indicator is a high level, it indicates that the current test is a high level fault injection, and the injection control module generates an electrical fault injection control signal in the clock cycle (also called the bit cycle) corresponding to the first bit, so that the fault voltage (high voltage) output by the electrical fault injection module passes through I 2 C bus connectivity is tested 2 For another example, the protocol data to be tested is "10001010", the electrical fault injection bit indication is "01100000" (1 indicates injection, 0 indicates no injection), and when the fault level indicator is low level, it indicates that the current test is low level fault injection, and the injection control module generates an electrical fault injection control signal in the clock cycle corresponding to the 2nd and 3rd bits, so that the fault voltage (low voltage) output by the electrical fault injection module passes through I 2 C bus connectivity is tested 2 C-bus device.

[0078] It can be understood that in some exemplary embodiments, when the fault level identifier has been determined, whether a specific bit in the protocol data to be tested is injected with a corresponding electrical fault is determined based on the value of the bit and the corresponding electrical fault injection bit indication.

[0079] In some exemplary embodiments, Figure 3 As shown, the fault switching module 130 is a single-pole double-throw SPDT switch, and the common terminal COM of the SPDT switch is connected to the I 2 C bus connects the I2 C bus devices;

[0080] The control end of the SPDT switch is connected to the injection control module 140 to receive the electrical fault injection control signal;

[0081] The normally closed terminal NC of the SPDT switch is connected to the I output of the protocol data injection module 120. 2 The C bus digital signal, the normally open terminal NO is connected to the fault voltage output by the electrical fault injection module 110 .

[0082] It can be understood that the normally closed terminal NC of the SPDT switch is connected to the I output of the protocol data injection module 120. 2 C bus digital signal, indicating the I output of the protocol data injection module when there is no electrical fault injection control signal input. 2 C bus digital signals pass through I 2 C bus connectivity is tested 2 C device, these digital signals meet the standard level specification requirements; when the designed electrical fault needs to be injected, the SPDT switch is controlled to switch to the normally open terminal NO through the electrical fault injection control signal, so that the fault voltage generated by the electrical fault injection module is injected through the I 2 C bus, realizing on-demand injection of electrical faults.

[0083] In some exemplary embodiments, the protocol data injection module includes: 2 C digital signal interface unit, used to convert the protocol data to I 2 C-bus digital signals.

[0084] In some exemplary embodiments, Figure 4 As shown, the system further includes a memory 150, a PCI bus 160 and a power module 170;

[0085] The memory 150 is used to store one or more of the following configuration data: standard high level range, standard low level range, fault level adjustment accuracy, offset mapping table. Optionally, other data can also be stored as needed, not limited to the example aspects. The PCI bus 160 is used to connect to the host computer for data / instruction interaction. The power module 170 realizes the secondary conversion of the PCI bus input power to the power required by the functional circuits inside the system.

[0086] In some exemplary embodiments, the switching action time of the fault switching module is less than I 2For example, the switching action time of the SPDT switch includes: the closing time of the normally open switch (the opening time of the normally closed switch) is recorded as Ton / Toff, that is, the time required for the switch to complete the path switching needs to be less than one bit period, and needs to be controlled below half of the bit period.

[0087] In some exemplary embodiments, the electrical fault injection control signal of the SPDT switch is also recorded as the SPDT control signal. In some exemplary embodiments, the DA unit is also called a low-speed DA because of its low data conversion rate.

[0088] In some exemplary embodiments, the electrical fault injection time is I 2 C-bus clock rising or falling edge.

[0089] As can be seen, FPGA completes the analysis of PCI bus data, receives the instructions of the host computer, and cooperates with the host computer software to control the injection of the protocol data to be tested and the fault voltage. 2 C bus. When it is necessary to inject faults at the electrical layer, the SPDT switch is synchronized with the bus bit clock to control the switching. 2 The line rate of C is relatively low. In some exemplary embodiments, electrical layer fault injection is implemented by switching, that is, the final test signal output port is switched at the fault injection bit by the switch. In order to prevent overshoot and ringing caused by switch switching, a filter circuit can be added to ensure the signal characteristics during electrical layer fault injection. The target voltage value of the fault injection is implemented by the DA unit. In some exemplary embodiments, the DA unit uses at least a DA unit with a resolution of 10 bits or more. Since the electrical layer fault injection is implemented by the front-end switch, the update rate (setup time) of the DA unit will not be considered. Therefore, I 2 C During electrical fault injection, uniform electrical (voltage amplitude) fault injection can be performed on any position.

[0090] I 2 When the C bus is performing fault injection, it is injected according to the bit time as the basic unit. The module performs fault injection at the bit time (bit period) corresponding to the error to be injected. There are electrical layer level fault injection and protocol layer bit fault injection. When performing electrical layer fault injection, it is necessary to perform synchronous control of the switch according to the start time of the bit time (bit period), and the action time of the switch (after Ton and Toff) needs to be less than one bit time period, and needs to be controlled below half of the bit period.

[0091] I 2 The protocol layer fault injection of the C bus supports both master and slave modes. When working in master mode, I 2 C-bus fault injection system as an I 2C master port for data communication, at this time, fault injection can be performed on the SCL and SDA ends; when working in slave mode, I 2 C-bus fault injection system as an I 2 C's slave port for data communication, and fault injection can be performed on the SDA end.

[0092] The present application also provides a kind of I 2 C bus fault injection methods, such as Figure 5 As shown, including:

[0093] Step 510: Control the fault voltage output by the electrical fault injection module or the I output by the protocol data injection module according to the electrical fault injection control signal. 2 C bus digital signal is switched to connect to the tested I 2 C bus devices;

[0094] Wherein, the fault voltage is generated by the electrical fault injection module according to the electrical fault configuration data; 2 The C bus digital signal is generated by the protocol data injection module according to the protocol data to be tested;

[0095] The electrical fault configuration data and the electrical fault injection control signal are generated according to host computer instruction data.

[0096] In some exemplary embodiments, the host computer instruction data includes: the protocol data to be tested, a fault level identifier and a fault level offset level; the fault level identifier includes: a high level or a low level; the fault level offset level indicates the degree of offset of the fault level compared to the standard level.

[0097] In some exemplary embodiments, the electrical fault configuration data is a target voltage value;

[0098] When the fault level identifier is a high level and the fault level offset level is a positive offset, the generated target voltage value is higher than the standard high level range; when the fault level identifier is a high level and the fault level offset level is a negative offset, the generated target voltage value is lower than the standard high level range.

[0099] and / or,

[0100] When the fault level identifier is a low level and the fault level offset level is a positive offset, the generated target voltage value is higher than the standard low level range; when the fault level identifier is a low level and the fault level offset level is a negative offset, the generated target voltage value is lower than the standard low level range.

[0101] In some exemplary embodiments, step 510 includes: the SPDT switch controls the fault voltage output by the electrical fault injection module or the I output by the protocol data injection module according to the electrical fault injection control signal. 2 C bus digital signal is switched to connect to the tested I 2 C bus devices;

[0102] The common terminal COM of the SPDT switch is connected to the 2 C bus connects the I 2 C bus devices;

[0103] The control end of the SPDT switch is connected to the injection control module to receive the electrical fault injection control signal;

[0104] The normally closed terminal NC of the SPDT switch is connected to the I output of the protocol data injection module. 2 C bus digital signal, the normally open terminal NO is connected to the fault voltage output by the electrical fault injection module.

[0105] It can be understood that in this embodiment, the SPDT switch is used as an I 2 The fault switching module in the I C bus fault injection system controls the injection of electrical faults through switches. In some exemplary embodiments, the SPDT switch is 2 The rising edge or falling edge of the C bus clock is controlled by the electrical fault injection control signal to control the corresponding conduction state to achieve switching.

[0106] The present application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the I described in any embodiment of the present application. 2 C-bus fault injection method.

[0107] The embodiment of the present application provides 2 The I C bus fault injection solution generates fault voltage on demand according to the relevant configuration data and performs fault injection according to the bit cycle, avoiding the inaccuracy of manual injection of electrical faults. Based on variable configuration data, the voltage fault amplitude is flexibly controlled and the corresponding voltage fault value is automatically generated, which significantly improves the I 2 The automation level of C bus system testing provides a convenient tool for more comprehensive testing.

[0108] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A kind of I 2 C bus fault injection system, characterized in that, include: An electrical fault injection module, a protocol data injection module, a fault switching module and an injection control module; The electrical fault injection module is configured to generate a fault voltage according to the electrical fault configuration data; The protocol data injection module is configured to generate I 2 C bus digital signal; The fault switching module is configured to control the fault voltage output by the electrical fault injection module or the I output by the protocol data injection module according to the electrical fault injection control signal. 2 C bus digital signal is switched to connect to the tested I 2 C bus devices; The injection control module is configured to generate the electrical fault configuration data and the electrical fault injection control signal according to host computer instruction data.

2. The method according to claim 1 2 C bus fault injection system, characterized in that, The host computer instruction data includes: the protocol data to be tested, the fault level identifier and the fault level offset level; The fault level identifier includes: a high level or a low level; the fault level offset level indicates the degree of offset of the fault level compared to the standard level.

3. The method according to claim 2 2 C bus fault injection system, characterized in that, The electrical fault configuration data is a target voltage value; The injection control module is configured to generate a target voltage value higher than a standard high level range when the fault level indicator is a high level and the fault level offset level is a positive offset; When the fault level indicator is a high level and the fault level offset level is a negative offset, generating a target voltage value lower than a standard high level range; and / or, The injection control module is configured to generate a target voltage value higher than a standard low level range when the fault level indicator is a low level and the fault level offset level is a positive offset; When the fault level indicator is a low level and the fault level offset level is a negative offset, a target voltage value lower than a standard low level range is generated.

4. The method according to claim 2 or 3 2 C bus fault injection system, characterized in that, The electrical fault injection module includes: a digital-to-analog conversion DA unit and a drive filter unit; the DA unit is configured to generate an initial fault voltage according to the electrical fault configuration data; the drive filter unit is configured to amplify and / or filter the initial fault voltage to obtain the fault voltage.

5. The method according to claim 2 2 C bus fault injection system, characterized in that, The injection control module is configured to generate the electrical fault injection control signal according to the first set value in the protocol data to be tested when the fault level indicator is at a high level, so as to control the fault voltage output by the electrical fault injection module to be connected to the tested I 2 C bus devices; and / or, The injection control module is configured to generate the electrical fault injection control signal according to the second set value in the protocol data to be tested when the fault level indicator is at a low level, so as to control the fault voltage output by the electrical fault injection module to be connected to the tested I 2 C-bus device.

6. The method according to claim 2 2 C bus fault injection system, characterized in that, The host computer instruction data also includes: an electrical fault injection bit indication, which is used to indicate the bit position for electrical fault injection for the protocol data to be tested; The injection control module is configured to generate the electrical fault injection control signal according to the electrical fault injection bit indication when the fault level indicator is a high level or a low level, so as to control the fault voltage output by the electrical fault injection module to be connected to the test I 2 C-bus device.

7. The method according to claim 5 or 6. 2 C bus fault injection system, characterized in that, The fault switching module is a single-pole double-throw SPDT switch, and the common terminal COM of the SPDT switch is connected to the I 2 C bus connects the I 2 C bus devices; The control end of the SPDT switch is connected to the injection control module to receive the electrical fault injection control signal; The normally closed terminal NC of the SPDT switch is connected to the I output of the protocol data injection module. 2 C bus digital signal, the normally open terminal NO is connected to the fault voltage output by the electrical fault injection module.

8. A kind of I 2 C bus fault injection method, characterized in that, include: According to the electrical fault injection control signal, the fault voltage output by the electrical fault injection module or the I output by the protocol data injection module is controlled. 2 C bus digital signal is switched to connect to the tested I 2 C bus devices; Wherein, the fault voltage is generated by the electrical fault injection module according to the electrical fault configuration data; 2 The C bus digital signal is generated by the protocol data injection module according to the protocol data to be tested; The electrical fault configuration data and the electrical fault injection control signal are generated according to host computer instruction data.

9. The method according to claim 8 2 C bus fault injection method, It is characterized in that The host computer instruction data includes: the protocol data to be tested, a fault level identifier and a fault level offset level; the fault level identifier includes: a high level or a low level; the fault level offset level indicates the degree of offset of the fault level compared to the standard level.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the I 2 C-bus fault injection method.

Images