Method for automatically generating debugger and debugging communication protocol

Abstract

The invention discloses a method for automatically generating a debugger and debugging a communication protocol, and relates to the technical field of processor design. According to the method, a processor design result file is automatically scanned through a tool, related information such as a processor framework and a register is obtained, the generation process of a protocol XML file, an online debugger code and a configuration file can be automatically completed through the tool, automatic support of a communication protocol and an online debugger on processor design is achieved, and the design efficiency is improved. And therefore, the problems of long time consumption and easiness in making mistakes in development implementation in the prior art are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of processor design, and in particular to a method for automatically generating a debugger and a debugging communication protocol. Background Art

[0002] Most existing processor design solutions rely on the participation of developers, who read processor design manuals and develop debugger codes to support processors. This leads to problems such as time-consuming development and easy errors. Summary of the invention

[0003] In order to solve the above problems existing in the prior art, the present invention provides a method for automatically generating a debugger and a debugging communication protocol.

[0004] To achieve the above object, the present invention provides the following solutions:

[0005] A method for automatically generating a debugger and a debugging communication protocol, comprising:

[0006] Obtaining a processor design result file; the processor design result file stores processor design information, interface functions, and debugging protocol requirements;

[0007] Scan and analyze the processor design result file using a software tool to obtain register information and processor architecture information;

[0008] Automatically generate a debugging communication protocol based on the register information and the processor architecture information;

[0009] Automatically generate software code and configuration files supporting the target processor for the online debugging tool based on the register information and the processor architecture information, so as to realize the automatic support of the debugger for the target processor; the target processor is a processor that meets the requirements of the processor design result file;

[0010] The system Verilog code for the debugger to access registers is automatically generated based on the processor instruction information, so as to realize the automatic generation and support of the debugging instructions of the target processor.

[0011] Optionally, the processor design information is represented in the form of a structure and a doubly linked list.

[0012] Optionally, automatically generating a debugging communication protocol based on the register information and the processor architecture information specifically includes:

[0013] Encapsulating the register information and the processor architecture information in XML format to generate an XML description file according to the debugging protocol requirements in the processor design result file;

[0014] The XML description file is used as a transmission file for acquiring the register information communication protocol to automatically generate a debugging communication protocol for the target processor.

[0015] Optionally, automatically generating software code and configuration files supporting the target processor for an online debugging tool based on the register information and the processor architecture information, so as to realize automatic support of the debugger for the target processor, specifically includes:

[0016] Add configuration commands and software codes to the online debugging tool;

[0017] Based on the register information and the processor architecture information, automatically generating a software code file and an emulator configuration file supporting a target processor according to the configuration command and the format of the software code added in the online debugging tool;

[0018] Using the source code and the software code file to build an online debugging tool and generate an executable file;

[0019] The executable file and the simulator configuration file are used to realize the automatic support of the debugger for the target processor.

[0020] Optionally, the systemverilog code for the debugger to access the register is automatically generated based on the processor instruction information to realize the automatic generation and support of the debugging instructions of the target processor, specifically including:

[0021] Use f2xx_get_regfile_load_inst function and f2xx_get_regfile_store_inst function to get instruction information;

[0022] Automatically generate a systemverilog code for a debugger to access a register according to the instruction information;

[0023] The automatically generated SystemVerilog code file is integrated into the RTL code of the target processor to realize the automatic generation and support of the debugging instructions of the target processor.

[0024] Optionally, the register information includes the number of registers, register names, register lengths, register categories and register functions.

[0025] A computer storage medium stores a computer program; the computer program is used to implement the method for automatically generating a debugger and debugging a communication protocol provided above.

[0026] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0027] The present invention uses a tool to automatically scan the processor design result file to obtain relevant information such as the processor architecture and registers. The tool can automatically complete the generation process of the protocol XML file, the online debugger code and the configuration file, realize the automatic support of the communication protocol and the online debugger for the processor design, ensure high efficiency and correctness, and thus solve the problems of time-consuming and error-prone development in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 The present invention provides a flow chart of a method for automatically generating a debugger and debugging a communication protocol. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] The purpose of the present invention is to provide a method for automatically generating a debugger and a debugging communication protocol, which can solve the problems of the prior art that the development and implementation is time-consuming and prone to errors.

[0032] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] like Figure 1 As shown, the method for automatically generating a debugger and a debugging communication protocol provided by the present invention includes:

[0034] Step 1: Obtain the processor design result file. The processor design result file stores processor design information, interface functions, and debugging protocol requirements.

[0035] Among them, the processor design result file is a dynamic link library file, assuming its name is core.so, the processor design information is represented in the form of a structure (for example, C language struct) and a doubly linked list and stored in the so file, and the so file also provides a series of interfaces (functions). The tool designed by the present invention will load the so file and call the interfaces provided by it, and restore the processor design information of the so file to the memory. In the memory, the processor design information is also stored and represented in the form of a structure and a doubly linked list to facilitate retrieval.

[0036] Step 2: Use software tools to scan and analyze the processor design result file to obtain register information and processor architecture information. Among them, the register information can be obtained through the f2dbg_get_reg_groups function. The register information includes: register number, name, length, category and function, etc.

[0037] Step 3: Automatically generate the debugging communication protocol based on the register information and processor architecture information. The implementation process of this step includes:

[0038] Step 3.1: According to the debugging protocol requirements, encapsulate the information obtained in step 2 in XML format, that is, automatically generate an XML description file of the new processor required by the debugging protocol. This XML description file contains the above-obtained register information.

[0039] This step automatically generates the required XML file communication protocol format according to the debug communication protocol requirements based on the acquired processor related information, so that the communication protocol can automatically and quickly support the processor design through the tool.

[0040] Step 3.2: In the debugger workflow, the XML description file automatically generated in step 3.1 above is used as the transmission file for obtaining the communication protocol of the processor register information, and finally the communication protocol of the new processor (i.e., the target processor) is automatically generated. The content of the communication protocol is the XML description file.

[0041] Step 4: Based on the register information and processor architecture information, the software code and configuration file supporting the target processor are automatically generated for the online debugging tool to realize the automatic support of the debugger for the target processor. The target processor is a processor that meets the requirements of the processor design result file.

[0042] The implementation process of this step can be:

[0043] Step 4.1: Implement automatic support mechanisms and methods for the target processor by adding configuration commands and software codes in the online debugging tool.

[0044] This step implements the processor automation support mechanism by adding processor information configuration methods and commands. When the processor changes, the relevant software code files and emulator configuration files are automatically generated through step 3.2, which can automatically support processor debugging without human intervention.

[0045] Step 4.2: Based on the register information and processor architecture information obtained in step 2, the software code files and simulator configuration files required to support the target processor are automatically generated according to the online debugging tool software code and configuration command format.

[0046] Step 4.3: Use the source code and the automatically generated processor information software code file to build an online debugging tool to generate an executable file, thereby realizing the automatic support of the online debugging tool for the processor.

[0047] Step 4.4: Use the executable file built above and the simulator configuration file automatically generated by the software in step 4.2 to finally realize the debugger's automatic support for the target processor.

[0048] Step 5: Automatically generate SystemVerilog code for the debugger to access registers based on the processor instruction information to achieve automatic generation and support of debug instructions for the target processor.

[0049] Step 5.1: Get instruction information through f2xx_get_regfile_load_inst function and f2xx_get_regfile_store_inst function.

[0050] Step 5.2: Based on the instruction information obtained in step 5.1, the SystemVerilog code for the debugger to access the register is automatically generated.

[0051] Step 5.3: Integrate the automatically generated SystemVerilog code file into the processor RTL code to realize the automatic generation and support of debugging related instructions by the debugging module in the processor.

[0052] In step 5.1 and step 5.2, the target processor instruction information is automatically obtained and a SystemVerilog code file is generated. When the processor instruction changes, there is no need to modify the processor RTL code, thereby realizing automatic support for the processor instruction by the debugging module.

[0053] In addition, when the above-mentioned method of automatically generating a debugger and debugging communication protocol is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk.

[0054] Based on the above description of the present invention, compared with the prior art, the present invention also has the following advantages:

[0055] 1. The present invention will automatically scan and analyze the processor design result file, extract the register information therein, and automatically generate an XML file according to the debugging communication protocol requirements, thereby realizing the automatic and rapid support of the debugger for the target processor.

[0056] 2. The present invention adjusts the construction and generation method of the debugger, and the functions related to the support of new instructions will be placed in an independent dynamic link library. When the instruction design of the target processor changes, it is only necessary to recompile and generate the dynamic link library to realize the debugger's automatic and rapid support for the target processor.

[0057] 3. The present invention will automatically scan and analyze the processing design result files, obtain all processor information related to processor debugging, and automatically generate software code files and simulator configuration files that meet the requirements of online debugging tools. The online debugger tool adds configuration methods and commands for processor information in the software code, combined with automatically generated software code files and simulator configuration files, to achieve automatic and rapid support for the debugging function of the target processor.

[0058] 4. The present invention realizes the automatic generation and support of debugging-related instructions by the processor debugging module, obtains the SystemVerilog code file of the register access instruction according to the processing design result file, integrates it into the hardware RTL code of the target processor, and realizes the rapid support of the processor instructions by the target processor debugging module.

[0059] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0060] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for automatically generating a debugger and a debugging communication protocol, characterized in that: include: Get the processor design result file; The processor design result file stores processor design information, interface functions and debugging protocol requirements; Scan and analyze the processor design result file using a software tool to obtain register information and processor architecture information; Automatically generate a debugging communication protocol based on the register information and the processor architecture information; Automatically generate software code and configuration files supporting the target processor for the online debugging tool based on the register information and the processor architecture information, so as to realize automatic support of the debugger for the target processor; The target processor is a processor that meets the requirements of the processor design result file; The system Verilog code for the debugger to access registers is automatically generated based on the processor instruction information, so as to realize the automatic generation and support of the debugging instructions of the target processor.

2. The method for automatically generating a debugger and a debugging communication protocol according to claim 1, characterized in that: The processor design information is represented in the form of a structure and a doubly linked list.

3. The method for automatically generating a debugger and a debugging communication protocol according to claim 1, characterized in that: Automatically generating a debugging communication protocol based on the register information and the processor architecture information specifically includes: Encapsulating the register information and the processor architecture information in XML format to generate an XML description file according to the debugging protocol requirements in the processor design result file; The XML description file is used as a transmission file for acquiring the register information communication protocol to automatically generate a debugging communication protocol for the target processor.

4. The method for automatically generating a debugger and a debugging communication protocol according to claim 1, characterized in that: Automatically generating software code and configuration files supporting the target processor for the online debugging tool based on the register information and the processor architecture information, so as to realize the automatic support of the debugger for the target processor, specifically including: Add configuration commands and software codes to the online debugging tool; Based on the register information and the processor architecture information, automatically generating a software code file and an emulator configuration file supporting a target processor according to the configuration command and the format of the software code added in the online debugging tool; Using the source code and the software code file to build an online debugging tool and generate an executable file; The executable file and the simulator configuration file are used to realize the automatic support of the debugger for the target processor.

5. The method for automatically generating a debugger and a debugging communication protocol according to claim 1, characterized in that: Automatically generate SystemVerilog code for debugger to access registers based on processor instruction information to achieve automatic generation and support of debug instructions for target processor, including: Use f2xx_get_regfile_load_inst function and f2xx_get_regfile_store_inst function to get instruction information; Automatically generate a systemverilog code for a debugger to access a register according to the instruction information; The automatically generated SystemVerilog code file is integrated into the RTL code of the target processor to realize the automatic generation and support of the debugging instructions of the target processor.

6. The method for automatically generating a debugger and a debugging communication protocol according to claim 1, characterized in that: The register information includes the number of registers, register names, register lengths, register categories and register functions.

7. A computer storage medium, characterized in that: A computer program is stored; the computer program is used to implement the method for automatically generating a debugger and a debugging communication protocol as described in any one of claims 1-6.

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