PTP data transmission method of high-speed signal acquisition / generation equipment

Abstract

The invention discloses a PTP (Precision Time Protocol) data transmission method of high-speed signal acquisition / generation equipment, which comprises the following steps of: constructing a PTP data transmission system based on a PCIe (Peripheral Component Interconnect Express) bus, performing memory mapping in a BAR (Broadband Augmented Reality) address mode, providing a PCIe bus link for realizing parallel access to four PCIe 3.0 * 4 NVMe solid state disks, and performing data access to an NVMe solid state disk end on the basis of the PCIe bus link. According to the PCIe 3.0 * 4 NVMe solid state disk, the read-write performance of each PCIe 3.0 * 4 NVMe solid state disk is exerted at the same time, and if the independent continuous read-write speed of each PCIe 3.0 * 4 NVMe SSD is 1.5 GB / s, the theoretical continuous read-write speed of the PCIe 3.0 * 8 NVMe SSD formed by splicing the four PCIe 3.0 * 4 NVMe SSDs can reach 6GB / s, so that the data transmission rate of high-speed signal acquisition / generation equipment is met.

Description

Technical Field

[0001] The present invention belongs to the technical field of high-speed signal acquisition / generation equipment, and more specifically, relates to a PTP data transmission method for a high-speed signal acquisition / generation equipment, that is, a method for performing high-speed point-to-point (PTP) data transmission between a high-speed signal acquisition / generation equipment and a high-speed NVMe solid-state hard disk (Non-Volatile Memory express Solid State Disk, NVMe SSD) through a PCIe (Peripheral Component Interconnect express) bus. Background Art

[0002] The data transmission rate requirement of high-speed signal acquisition / generation equipment is generally above 5GB / s, and it has PCIe bus function, generally including PCIe / PXIe bus high-speed signal acquisition equipment, PCIe / PXIe bus broadband signal generation equipment, etc.

[0003] NVMe SSD is a high-performance, high-read and high-write bandwidth storage device that stores data in non-volatile memory. Its read and write interface is a PCIe bus interface that complies with the NVMe protocol. Conventional NVMe SSD read and write access is performed using a host device (Host) such as a computer through the PCIe bus in a manner that complies with the NVMe protocol. If data transmission between a high-speed signal acquisition device and an NVMe SSD is required, the host device must first read the data from the high-speed signal acquisition device to the host's internal memory, and then write the data to the NVMe SSD. Similarly, if data transmission between a high-speed signal generation device and an NVMe SSD is required, the host device must first read the data from the NVMe SSD to the host's internal memory, and then write the data to the high-speed signal generation device. Such an operation will greatly reduce the data read and write speed between the high-speed signal acquisition / generation device and the NVMe SSD, and cannot meet the data transmission rate of the high-speed signal acquisition / generation device, that is, the transmission rate requirement of 5GB / s. Summary of the invention

[0004] The object of the present invention is to overcome the deficiencies of the prior art and to provide a PTP data transmission method for a high-speed signal acquisition / generation device to meet the data transmission rate of the high-speed signal acquisition / generation device.

[0005] To achieve the above-mentioned object of the invention, the PTP data transmission method of the high-speed signal acquisition / generation device of the present invention is characterized in that it comprises the following steps:

[0006] (1) Construct a PTP data transmission system based on PCIe bus, which includes:

[0007] The host includes a DMA (Direct Memory Access) controller, a multi-threaded CPU, a BAR address space, and physical memory;

[0008] Two PCIe switches PCIe Switch 1 and 2, wherein PCIe switch PCIe Switch 1 includes at least 3 PCIe interfaces, and the configuration of the 3 PCIe interfaces is not less than PCIe3.0 x8, wherein 1 PCIe interface is connected to the host, 1 PCIe interface is connected to PCIe switch PCIe Switch 2, and 1 PCIe interface is connected to a high-speed signal acquisition / generation device; PCIe switch PCIe Switch 2 includes at least 5 PCIe interfaces, and 1 interface is configured not less than PCIe3.0 x8, and the other 4 interfaces are configured not less than PCIe3.0 x4, the interface configured not less than PCIe3.0 x8 is used to connect to PCIe switch PCIe Switch 1, and the other 4 interfaces configured not less than PCIe3.0 x4 are used to connect to 4 NVMe solid-state drives NVMe SSD1, 2, 3, and 4 respectively;

[0009] 4 NVMe solid state drives NVMe SSD1, 2, 3, and 4, each NVMe solid state drive includes an NVMe controller, a DMA controller, a BAR address space, and a non-volatile memory;

[0010] A high-speed signal acquisition / generation device including a PCIe controller, a BAR address space, and a cache;

[0011] (2) Memory Mapping

[0012] For a high-speed signal acquisition / generation device, a storage space with a storage capacity of C is planned in its high-speed cache, and the storage space is mapped to the host physical memory in the BAR address mode according to the BAR address DEV_BAR_ADDR in the BAR address space, so as to obtain a physical memory with a storage capacity of C on the host. On the host side, the BAR address space of the physical memory with a storage capacity of C is equally divided into four sub-address spaces of the same size, and the BAR addresses SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, and SSD4_BAR_ADDR of the four sub-address spaces are recorded and used for the direct memory access start addresses of the NVMe controllers of the NVMe solid-state drives NVMe SSD1, 2, 3, and 4 connected to the four PCIe3.0 x4 interfaces, respectively. Among them:

[0013] SSD1_BAR_ADDR=DEV_BAR_ADDR

[0014] SSD2_BAR_ADDR=DEV_BAR_ADDR+C / 4

[0015] SSD3_BAR_ADDR=DEV_BAR_ADDR+C / 2

[0016] SSD4_BAR_ADDR=DEV_BAR_ADDR+3C / 4

[0017] (3) Data access

[0018] 3.1) Writing to NVMe SSD

[0019] When the high-speed signal acquisition device samples the data, it stores the data in the storage space planned by the internal cache, and generates an MSI (Message Signaled Interrupt) interrupt to notify the high-speed signal acquisition device kernel driver on the host to access the cache. After receiving the MSI interrupt notification, the kernel driver, under the control of the multi-threaded CPU, moves the data to the host in a "direct memory access" manner according to the BAR address DEV_BAR_ADDR through the host's DMA controller;

[0020] After the sampled data is moved to the physical memory of the host, the NVMe controllers of the four NVMe solid-state drives NVMe SSD1, 2, 3, and 4 call their respective DMA controllers according to the BAR addresses SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, and SSD4_BAR_ADDR in a "direct memory access" manner to transfer the data to the non-volatile memories of the four NVMe solid-state drives NVMe SSD1, 2, 3, and 4 for storage;

[0021] 3.2) Reading from NVMe SSD

[0022] The NVMe controllers of the four NVMe solid-state drives NVMe SSD1, 2, 3, and 4 call their own DMA controllers to transfer the storage data to the physical memory of the host in a "direct memory access" manner according to the BAR addresses SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, and SSD4_BAR_ADDR;

[0023] After the stored data is moved to the physical memory of the host, under the control of the multi-threaded CPU, the kernel driver of the high-speed signal generating device calls the DMA controller of the host to move the data to the high-speed cache inside the high-speed signal generating device in a "direct memory access" manner according to the BAR address DEV_BAR_ADDR;

[0024] The writing of sampled data and the reading of stored data are completed based on files.

[0025] The object of the invention of the present invention is achieved in this way:

[0026] The PTP data transmission method of the high-speed signal acquisition / generation device of the present invention constructs a PTP data transmission system based on the PCIe bus, and performs memory mapping in a BAR address manner to provide a PCIe bus link for parallel access to four PCIe3.0 x4 NVMe solid-state hard drives. On this basis, data access is performed on the NVMe solid-state hard drive end to simultaneously exert the read and write performance of each PCIe3.0 x4 NVMe solid-state hard drive. If the independent continuous read and write speed of each PCIe3.0 x4 NVMe SSD is 1.5GB / s, the theoretical continuous read and write speed of the PCIe3.0 x8 NVMe SSD after the four PCIe3.0x4 NVMe SSDs are spliced ​​can reach 6GB / s, which meets the data transmission rate of the high-speed signal acquisition / generation device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a flow chart of a specific implementation method of the PTP data transmission method of the high-speed signal acquisition / generation device of the present invention;

[0028] Figure 2 It is a principle block diagram of a specific implementation of the PTP data transmission system based on the PCIe bus constructed in the present invention;

[0029] Figure 3 yes Figure 1 This is a schematic diagram of the principle of memory mapping. DETAILED DESCRIPTION

[0030] The specific implementation of the present invention is described below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0031] Figure 1 It is a flow chart of a specific implementation of the PTP data transmission method of the high-speed signal acquisition / generation device of the present invention.

[0032] In this embodiment, if Figure 1 As shown, the PTP data transmission method of the high-speed signal acquisition / generation device of the present invention comprises the following steps:

[0033] Step S1: Building a PTP data transmission system based on PCIe bus

[0034] In this embodiment, if Figure 2 As shown, the PTP data transmission system based on the PCIe bus includes: a host Host, two PCIe switches PCIe Switch 1, 2, four NVMe solid-state hard drives NVMe SSD1, 2, 3, 4 and a high-speed signal acquisition / generation device.

[0035] The host Host includes a DMA (Direct Memory Access) controller, a multi-threaded CPU, a BAR address space, and physical memory.

[0036] The PCIe switch PCIe Switch 1 includes 3 PCIe interfaces, and the configuration of the 3 PCIe interfaces is not less than PCIe3.0 x8, wherein 1 PCIe interface is connected to the host, 1 PCIe interface is connected to the PCIe switch PCIe Switch 2, and 1 PCIe interface is connected to the high-speed signal acquisition / generation device.

[0037] PCIe switch PCIe Switch 2 includes 5 PCIe interfaces, and one of the interfaces is configured not less than PCIe3.0x8, and the other four interfaces are configured not less than PCIe3.0 x4. The interface configured not less than PCIe3.0 x8 is used to connect to PCIe switch PCIe Switch 1, and the other four interfaces configured not less than PCIe3.0 x4 are used to connect to four NVMe solid-state drives NVMe SSD1, 2, 3, and 4 respectively.

[0038] There are four NVMe solid state drives NVMe SSD1, 2, 3, and 4. Each NVMe solid state drive includes an NVMe controller, a DMA controller, a BAR address space, and a non-volatile memory.

[0039] A high-speed signal acquisition / generation device includes a PCIe controller, a BAR address space, and a cache.

[0040] In the present invention, if Figure 2As shown in the figure, four PCIe3.0 x4 NVMe solid-state drives are integrated together through a PCIe-Switch chip, namely PCIe switch PCIe Switch 2. PCIe switch PCIe Switch 2 provides five PCIe interfaces, namely one PCIe3.0x8 and four PCIe3.0x4 interfaces. Among them, the PCIe3.0x8 interface is used to connect to another PCIe switch PCIe Switch 1, and is connected to the host through PCIe switch PCIe Switch 1, and the four PCIe3.0x4 interfaces are used to connect to the four PCIe3.0x4 NVMe solid-state drives. This connection method can realize a PCIe3.0 x8 NVMe SSD with four times the storage capacity for the host side, and can provide a PCIe bus link for parallel access to four PCIe3.0 x4 NVMe solid-state drives, so as to give full play to the read and write performance of the four PCIe3.0 x4 NVMe solid-state drives. If the individual continuous read and write speed of each PCIe3.0x4 NVMe SSD is 1.5GB / s, the theoretical continuous read and write speed of the PCIe3.0 x8 NVMe SSD after four PCIe3.0 x4 NVMe SSDs are spliced ​​together can reach 6GB / s.

[0041] Step S2: Memory Mapping

[0042] In this embodiment, if Figure 3 As shown, for a high-speed signal acquisition / generation device, a storage space with a storage capacity of C is planned in its high-speed cache, and the storage space is mapped to the host physical memory in the BAR address mode according to the BAR address DEV_BAR_ADDR in the BAR address space, so as to obtain a physical memory with a storage capacity of C on the host. On the host side, the BAR address space of the physical memory with a storage capacity of C is equally divided into 4 sub-address spaces of the same size, and the BAR addresses SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, and SSD4_BAR_ADDR of the 4 sub-address spaces are recorded and used for the direct memory access start addresses of the NVMe controllers of the NVMe solid-state drives NVMe SSD1, 2, 3, and 4 connected to the 4 PCIe3.0 x4 interfaces, respectively. Among them:

[0043] SSD1_BAR_ADDR=DEV_BAR_ADDR

[0044] SSD2_BAR_ADDR=DEV_BAR_ADDR+C / 4

[0045] SSD3_BAR_ADDR=DEV_BAR_ADDR+C / 2

[0046] SSD4_BAR_ADDR=DEV_BAR_ADDR+3C / 4

[0047] In this embodiment, the storage capacity is C=4MB. In this embodiment, in order to realize continuous data acquisition and transmission, two storage spaces with a storage capacity of C are planned in the cache of the high-speed signal acquisition / generation device, that is, 8MB storage space is planned in the cache of the high-speed signal acquisition / generation device, and the 8MB storage space in the internal cache of the high-speed signal acquisition device is mapped to the host physical memory in the form of BAR address. This 8MB storage space is defined as two continuous sub-storage spaces connected end to end for "ping-pong cache" access, and the BAR address of sub-storage space 1 is defined as DEV_BAR1_ADDR, and the BAR address of sub-storage space 2 is defined as DEV_BAR2_ADDR.

[0048] Step S3: Data Access

[0049] Step S3.1: NVMe SSD writing

[0050] When the high-speed signal acquisition device samples the data, it stores the data in the storage space planned by the internal cache, and generates an MSI (Message Signaled Interrupt) interrupt to notify the high-speed signal acquisition device kernel driver on the host to access the cache. After receiving the MSI interrupt notification, the kernel driver, under the control of the multi-threaded CPU, moves the data to the host in a "direct memory access" manner according to the BAR address DEV_BAR_ADDR through the host's DMA controller.

[0051] After the sampled data is moved to the physical memory of the host, the NVMe controllers of the four NVMe solid-state drives NVMe SSD1, 2, 3, and 4 call their respective DMA controllers according to the BAR addresses SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, and SSD4_BAR_ADDR in a "direct memory access" manner to transfer the data to the non-volatile memories of the four NVMe solid-state drives NVMe SSD1, 2, 3, and 4 for storage.

[0052] In this embodiment, the steps of writing to the NVMe solid state drive, i.e., transmitting data from the high-speed signal acquisition device to the NVMe SSD, are as follows:

[0053] Step S3.1.1: Start the Host data storage software;

[0054] Step S3.1.2: Query whether there are at least 4 NVMe solid-state drives and at least 1 high-speed signal acquisition device in the PTP data transmission system based on the PCIe bus;

[0055] Step S3.1.3: Create file systems in the four NVMe solid-state drives in turn and mount drive letters;

[0056] Step S3.1.4: Initialize the high-speed signal acquisition device to make it enter the acquisition preparation state;

[0057] Step S3.1.5: When the high-speed signal acquisition device enters the acquisition preparation state, an 8MB storage space is planned in its internal cache to implement the PTP data transmission operation. In the host Host, the 8MB storage space in the internal cache of the high-speed signal acquisition device is mapped to the host Host physical memory in the form of a BAR address, and this 8MB storage space is defined as two end-to-end continuous sub-storage spaces 1 and 2, and the BAR address of sub-storage space 1 is defined as DEV_BAR1_ADDR, and the BAR address of sub-storage space 2 is defined as DEV_BAR2_ADDR;

[0058] Step S3.1.6: Define the initial mapping BAR addresses of the four NVMe solid state drives in the host Host memory as SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, and SSD4_BAR_ADDR, where:

[0059] SSD1_BAR_ADDR=DEV_BAR1_ADDR

[0060] SSD2_BAR_ADDR=DEV_BAR1_ADDR+1MB

[0061] SSD3_BAR_ADDR=DEV_BAR1_ADDR+2MB

[0062] SSD4_BAR_ADDR=DEV_BAR1_ADDR+3MB

[0063] Step S3.1.7: Create a main process control thread on the host Host, and bind the main process control thread to any thread CPU;

[0064] Step S3.1.8: In the main process control thread, the file name and file path of the data file to be stored are respectively passed into the four NVMe solid-state drive file systems, so that the four NVMe solid-state drives simultaneously create files with the same file name in the same path;

[0065] Step S3.1.9: Create four data writing sub-threads in the main process control thread, and bind these four data writing sub-threads to different thread CPUs respectively;

[0066] Step S3.1.10: The BAR addresses SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, and SSD4_BAR_ADDR of the four NVMe solid-state drives are respectively passed to the four data writing sub-threads as mapping binding address variables of the four NVMe solid-state drives during direct memory access transmission;

[0067] Step S3.1.11: In the main process control thread, control the high-speed signal acquisition device to start signal acquisition. At this time, the high-speed signal acquisition device initializes the internal read completion flag register DEV_RD_DONE_REG = 0, that is, the internal storage space read operation is not completed, the sub-storage space 1 empty flag DEV_MEM1_EMPTY = 1, that is, the sub-storage space 1 is empty, and the sub-storage space 2 empty flag DEV_MEM2_EMPTY = 1, that is, the sub-storage space 2 is empty;

[0068] Step S3.1.12: The high-speed signal acquisition device determines the value of the sub-storage space 1 empty flag DEV_MEM1_EMPTY. If it is 0, wait. If it is 1, set it to 0 and store the acquired data into the sub-storage space 1 with DEV_BAR1_ADDR as the starting address inside the device.

[0069] Step S3.1.13: When the 4MB of data in sub-storage space 1 is full, the high-speed signal acquisition device determines the value of the empty flag DEV_MEM2_EMPTY of sub-storage space 2. If it is 0, it waits; if it is 1, it sets it to 0, and immediately switches the collected data to be stored in the sub-storage space 2 with DEV_BAR2_ADDR as the starting address inside the device. At the same time, the high-speed signal acquisition device sets the internal valid memory register DEV_MEM_VALID_REG to 0, indicating that the currently readable sub-storage space is the sub-storage space 1 pointed to by DEV_BAR1_ADDR, and sends a read enable interrupt signal DEV_RD_ENABLE_INT to the host Host to notify the host Host to start reading data from sub-storage space 1;

[0070] Step S3.1.14: After the host Host receives the interrupt signal DEV_RD_ENABLE_INT, it reads the value of the device valid memory register DEV_MEM_VALID_REG. At this time, DEV_MEM_VALID_REG = 0, indicating that the sub-storage space that can be read currently is the sub-storage space 1 pointed to by DEV_BAR1_ADDR. The DMA controller of the host Host moves the data to the host in the "direct memory access" mode according to the BAR address DEV_BAR1_ADDR. The host Host configures the BAR address as:

[0071] SSD1_BAR_ADDR=DEV_BAR1_ADDR

[0072] SSD2_BAR_ADDR=DEV_BAR1_ADDR+1MB

[0073] SSD3_BAR_ADDR=DEV_BAR1_ADDR+2MB

[0074] SSD4_BAR_ADDR=DEV_BAR1_ADDR+3MB

[0075] Step S3.1.15: The host Host initiates NVMe SSD file write events through four data writing sub-threads respectively, and the NVMe controllers of the four NVMe SSDs immediately call their own DMA controllers to read data from the BAR addresses of the host Host: SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, SSD4_BAR_ADDR into their own internal non-volatile memories;

[0076] Step S3.1.16: After the NVMe SSD file write events of the four data writing sub-threads are executed, the host Host sets the signal acquisition device read completion flag register DEV_RD_DONE_REG to 1 to notify the high-speed signal acquisition device that the transmission is completed;

[0077] Step S3.1.17: After the high-speed signal acquisition device detects that the read completion flag register DEV_RD_DONE_REG = 1, the sub-storage space 1 empty flag DEV_MEM1_EMPTY is set to 1, and the completion flag register DEV_RD_DONE_REG is set to 0;

[0078] Step S3.1.18 After the 4MB data in sub-storage space 2 is filled, the high-speed signal acquisition device determines the value of the empty flag DEV_MEM1_EMPTY of sub-storage space 1. If it is 0, it waits; if it is 1, it sets it to 0, and immediately switches the collected data to be stored in the sub-storage space 1 with DEV_BAR1_ADDR as the starting address inside the device. At the same time, the high-speed signal acquisition device sets the internal valid memory register DEV_MEM_VALID_REG to 1, indicating that the currently readable sub-storage space is the sub-storage space 2 pointed to by DEV_BAR2_ADDR, and sends a read enable interrupt signal DEV_RD_ENABLE_INT to the Host again to notify the Host to start reading data from sub-storage space 2;

[0079] Step S3.1.19: After the host Host receives the interrupt signal DEV_RD_ENABLE_INT, it reads the value of the device valid memory register DEV_MEM_VALID_REG. At this time, DEV_MEM_VALID_REG = 1, indicating that the sub-storage space that can be read currently is the sub-storage space 2 pointed to by DEV_BAR2_ADDR. The DMA controller of the host Host moves the data to the host in the "direct memory access" mode according to the BAR address DEV_BAR2_ADDR. The host Host configures the BAR address as:

[0080] SSD1_BAR_ADDR=DEV_BAR2_ADDR

[0081] SSD2_BAR_ADDR=DEV_BAR2_ADDR+1MB

[0082] SSD3_BAR_ADDR=DEV_BAR2_ADDR+2MB

[0083] SSD4_BAR_ADDR=DEV_BAR2_ADDR+3MB

[0084] Step S3.1.20: The host Host initiates NVMe SSD file write events through four data write sub-threads respectively. The NVMe controllers of the four NVMe SSDs immediately call their own DMA controllers to read data from the host Host's BAR addresses: SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, SSD4_BAR_ADDR to their own internal non-volatile memories.

[0085] Step S3.1.21: After the NVMe SSD file write events of the four data writing sub-threads are executed, the host Host sets the signal acquisition device read completion flag register DEV_RD_DONE_REG to 1 to notify the high-speed signal acquisition device that the transmission is completed;

[0086] Step S3.1.22: After the high-speed signal acquisition device detects that the read completion flag register DEV_RD_DONE_REG=1, the sub-storage space 2 empty flag DEV_MEM2_EMPTY is set to 1, and the completion flag register DEV_RD_DONE_REG is set to 0;

[0087] Step S3.1.23: Repeat steps S3.1.12 to S3.1.22 until all data of the specified file size is stored in the non-volatile memory of the NVMe SSD;

[0088] Step S3.1.24: The main process control thread of the host Host controls the high-speed signal acquisition device to stop acquisition, closes and releases the four data writing sub-threads;

[0089] Step S3.1.25: The host closes the file in the file system, closes and releases the main process control thread, and exits the data storage software;

[0090] Step S3.2: NVMe SSD readout

[0091] The NVMe controllers of the four NVMe solid-state drives NVMe SSD1, 2, 3, and 4 call their own DMA controllers to transfer the storage data to the physical memory of the host in a "direct memory access" manner according to the BAR addresses SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, and SSD4_BAR_ADDR;

[0092] After the stored data is moved to the physical memory of the host, under the control of the multi-threaded CPU, the kernel driver of the high-speed signal generating device calls the DMA controller of the host to move the data to the high-speed cache inside the high-speed signal generating device in a "direct memory access" manner according to the BAR address DEV_BAR_ADDR;

[0093] The writing of sampled data and the reading of stored data are completed based on files.

[0094] In this embodiment, the NVMe solid state drive end reads out, that is, the data transmission steps from the NVMe SSD to the high-speed signal generating device are:

[0095] Step S3.2.1: Start the Host data reading software;

[0096] Step S3.2.2: Query whether there are at least 4 NVMe solid-state drives and at least 1 high-speed signal generating device in the PTP data transmission system based on the PCIe bus;

[0097] Step S3.2.3: Create file systems in the four NVMe solid-state drives in turn and mount drive letters;

[0098] Step S3.2.4: Initialize the high-speed signal generating device to put it into a generating ready state;

[0099] Step S3.2.5: When the high-speed signal generating device enters the generating preparation state, an 8MB storage space is planned in its internal cache to realize the PTP data transmission operation. In the host Host, the 8MB storage space in the internal cache of the high-speed signal generating device is mapped to the host Host physical memory in the form of BAR address. This 8MB storage space is defined as two end-to-end continuous sub-storage spaces 1 and 2 for "ping-pong cache" access. The BAR address of sub-storage space 1 is defined as DEV_BAR1_ADDR, and the BAR address of sub-storage space 2 is defined as DEV_BAR2_ADDR;

[0100] Step S3.2.6: Define the initial mapping BAR addresses of the four NVMe solid state drives in the host Host memory as SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, and SSD4_BAR_ADDR, where:

[0101] SSD1_BAR_ADDR=DEV_BAR1_ADDR

[0102] SSD2_BAR_ADDR=DEV_BAR1_ADDR+1MB

[0103] SSD3_BAR_ADDR=DEV_BAR1_ADDR+2MB

[0104] SSD4_BAR_ADDR=DEV_BAR1_ADDR+3MB

[0105] Step S3.2.7: Create a main process control thread on the host Host, and bind the main process control thread to any thread CPU;

[0106] Step S3.2.8: In the main process control thread, the file name and file path of the data file to be read are respectively passed into the four NVMe solid-state drive file systems, so that the four NVMe solid-state drives simultaneously open the file with the same file name in the same path;

[0107] Step S3.2.9: Create four data reading sub-threads in the main process control thread, and bind these four data reading sub-threads to different thread CPUs respectively;

[0108] Step S3.2.10: The BAR addresses SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, and SSD4_BAR_ADDR of the four NVMe solid-state drives are respectively passed to the four data reading sub-threads as mapping binding address variables of the four NVMe solid-state drives during direct memory access transmission;

[0109] Step S3.2.11: In the main process control thread, control the high-speed signal generating device to start signal generation. At this time, the high-speed signal generating device initializes the internal valid memory register DEV_MEM_VALID_REG = 0, the current writable sub-storage space is the sub-storage space 1 pointed to by DEV_BAR1_ADDR, the write completion flag register DEV_WR_DONE_REG = 0, that is, the current write operation is not completed, the sub-storage space 1 empty flag DEV_MEM1_EMPTY = 1, that is, the sub-storage space 1 is empty, and the sub-storage space 2 empty flag DEV_MEM2_EMPTY = 1, that is, the sub-storage space 2 is empty;

[0110] Step S3.2.12: The high-speed signal generating device determines the value of the internal sub-storage space 1 empty flag DEV_MEM1_EMPTY. If it is 0, the device waits. If it is 1, the internal valid memory register DEV_MEM_VALID_REG is set to 0, and a write enable interrupt signal DEV_WR_ENABLE_INT is sent to the host Host to notify the host Host to start writing data to the sub-storage space 1.

[0111] Step S3.2.13: After the host Host receives the interrupt signal DEV_WR_ENABLE_INT, it reads the value of the valid memory register DEV_MEM_VALID_REG. At this time, DEV_MEM_VALID_REG = 0, indicating that the sub-storage space that can be written currently is the sub-storage space 1 pointed to by DEV_BAR1_ADDR. Then the host Host configures the BAR address as:

[0112] SSD1_BAR_ADDR=DEV_BAR1_ADDR

[0113] SSD2_BAR_ADDR=DEV_BAR1_ADDR+1MB

[0114] SSD3_BAR_ADDR=DEV_BAR1_ADDR+2MB

[0115] SSD4_BAR_ADDR=DEV_BAR1_ADDR+3MB

[0116] Step S3.2.14: The host Host initiates NVMe SSD file read events through four data reading sub-threads respectively, and the NVMe controllers of the four NVMe SSDs immediately call their own DMA controllers to read data from their own internal non-volatile memories to the BAR addresses of the host Host: SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, SSD4_BAR_ADDR;

[0117] Step S3.2.15: After the NVMe SSD file read events of the four data read sub-threads are executed, the host Host sets the signal generating device write completion flag register DEV_WR_DONE_REG to 1 to notify the high-speed signal generating device that the transmission is completed;

[0118] Step S3.2.16: After the high-speed signal generating device detects that the write completion flag register DEV_WR_DONE_REG=1, it immediately sets the write completion flag register DEV_WR_DONE_REG to 0, and sets the sub-storage space 1 empty flag DEV_MEM1_EMPTY to 0;

[0119] Step S3.2.17: The high-speed signal generating device determines the value of the internal sub-storage space 2 empty flag DEV_MEM2_EMPTY. If it is 0, the device waits. If it is 1, the internal valid memory register DEV_MEM_VALID_REG is set to 1, and a write enable interrupt signal DEV_WR_ENABLE_INT is sent to the host Host to notify the host that the host can start writing data to the sub-storage space 2.

[0120] Step S3.2.18: After the high-speed signal generating device detects that the internal sub-storage space 1 empty flag DEV_MEM1_EMPTY=0, the internal signal generating circuit reads data from the sub-storage space 1 until all 4MB of data are read, and then sets the internal sub-storage space 1 empty flag DEV_MEM1_EMPTY to 1;

[0121] Step S3.2.19: After the host Host receives the interrupt signal DEV_WR_ENABLE_INT, it reads the value of the valid memory register DEV_MEM_VALID_REG. At this time, DEV_MEM_VALID_REG = 1, indicating that the sub-storage space that can be written is the sub-storage space 2 pointed to by DEV_BAR2_ADDR. Then the Host configures the BAR address of the host Host as:

[0122] SSD1_BAR_ADDR=DEV_BAR2_ADDR

[0123] SSD2_BAR_ADDR=DEV_BAR2_ADDR+1MB

[0124] SSD3_BAR_ADDR=DEV_BAR2_ADDR+2MB

[0125] SSD4_BAR_ADDR=DEV_BAR2_ADDR+3MB

[0126] Step S3.2.20: The host Host initiates NVMe SSD file read events through four data reading sub-threads respectively, and the NVMe controllers of the four NVMe SSDs immediately call their own DMA controllers to read data from their own internal non-volatile memories to the BAR addresses of the host Host: SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, SSD4_BAR_ADDR;

[0127] Step S3.2.21: After the NVMe SSD file read events of the four data read sub-threads are executed, the host Host sets the signal generating device write completion flag register DEV_WR_DONE_REG to 1 to notify the high-speed signal generating device that the transmission is completed;

[0128] Step S3.2.22: After the high-speed signal generating device detects that the write completion flag register DEV_WR_DONE_REG=1, it immediately sets the write completion flag register DEV_WR_DONE_REG to 0, and sets the sub-storage space 2 empty flag DEV_MEM2_EMPTY to 0;

[0129] Step S3.2.23: After the high-speed signal generating device detects that the internal sub-storage space 2 empty flag DEV_MEM2_EMPTY=0, the internal signal generating circuit reads data from the sub-storage space 2 until all 4MB of data are read, and then sets the internal sub-storage space 2 empty flag DEV_MEM2_EMPTY to 1;

[0130] Step S3.2.24: Repeat steps S3.2.12 to S3.2.23 until all data of the specified file size is read out from the non-volatile memories of the four NVMe solid state drives;

[0131] Step S3.2.25: The main process control thread of the host controls the high-speed signal generating device to stop generating, closes and releases the four data writing sub-threads;

[0132] Step S3.2.26: The host Hos end closes the file in the file system, closes and releases the main process control thread, and exits the data reading software.

[0133] Although the above describes the illustrative specific embodiments of the present invention to facilitate those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations using the concept of the present invention are protected.

Claims

1. A PTP data transmission method for high-speed signal acquisition / generation equipment, It is characterized in that The following steps are involved: (1) Construct a PTP data transmission system based on PCIe bus, which includes: The host, which includes a DMA controller, a multi-threaded CPU, a BAR address space, and physical memory; Two PCIe switches PCIe Switch 1 and 2, wherein PCIe switch PCIe Switch 1 includes at least 3 PCIe interfaces, and the configuration of the 3 PCIe interfaces is not less than PCIe3.0 x8, wherein 1 PCIe interface is connected to the host, 1 PCIe interface is connected to PCIe switch PCIe Switch 2, and 1 PCIe interface is connected to a high-speed signal acquisition / generation device; PCIe switch PCIe Switch 2 includes at least 5 PCIe interfaces, and 1 interface is configured not less than PCIe3.0 x8, and the other 4 interfaces are configured not less than PCIe3.0 x4, the interface configured not less than PCIe3.0 x8 is used to connect to PCIe switch PCIeSwitch 1, and the other 4 interfaces configured not less than PCIe3.0 x4 are used to connect to 4 NVMe solid-state drives NVMeSSD1, 2, 3, and 4 respectively; 4 NVMe solid state drives NVMe SSD1, 2, 3, and 4, each NVMe solid state drive includes an NVMe controller, a DMA controller, a BAR address space, and a non-volatile memory; A high-speed signal acquisition / generation device including a PCIe controller, a BAR address space, and a cache; (2) Memory Mapping For a high-speed signal acquisition / generation device, a storage space with a storage capacity of C is planned in its cache, and the storage space is mapped to the host physical memory in the BAR address mode according to the BAR address DEV_BAR_ADDR in the BAR address space, so as to obtain a physical memory with a storage capacity of C on the host. On the host side, the BAR address space of the physical memory with a storage capacity of C is equally divided into four sub-address spaces of the same size, and the BAR addresses SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, and SSD4_BAR_ADDR of the four sub-address spaces are recorded and used for the direct memory access start addresses of the NVMe controllers of the NVMe solid-state drives NVMe SSD1, 2, 3, and 4 connected to the four PCIe3.0x4 interfaces, respectively. Among them: SSD1_BAR_ADDR=DEV_BAR_ADDR SSD2_BAR_ADDR=DEV_BAR_ADDR+C / 4 SSD3_BAR_ADDR=DEV_BAR_ADDR+C / 2 SSD4_BAR_ADDR=DEV_BAR_ADDR+3C / 4 (3) Data access 3.1) Writing to NVMe SSD When the high-speed signal acquisition device samples the data, it stores the data in the storage space planned by the internal cache, and generates an MSI interrupt to notify the kernel driver of the high-speed signal acquisition device on the host to access the cache. After receiving the MSI interrupt notification, the kernel driver, under the control of the multi-threaded CPU, moves the data to the host in the form of "direct memory access" according to the BAR address DEV_BAR_ADDR through the host's DMA controller; After the sampled data is moved to the physical memory of the host, the NVMe controllers of the four NVMe solid-state drives NVMe SSD1, 2, 3, and 4 call their respective DMA controllers according to the BAR addresses SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, and SSD4_BAR_ADDR in a "direct memory access" manner to transfer the data to the non-volatile memories of the four NVMe solid-state drives NVMe SSD1, 2, 3, and 4 for storage; 3.2) Reading from NVMe SSD The NVMe controllers of the four NVMe solid-state drives NVMe SSD1, 2, 3, and 4 call their own DMA controllers to transfer the storage data to the physical memory of the host in a "direct memory access" manner according to the BAR addresses SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, and SSD4_BAR_ADDR; When the stored data is moved to the physical memory of the host, under the control of the multi-threaded CPU, the kernel driver of the high-speed signal generating device calls the DMA controller of the host to move the data to the high-speed cache inside the high-speed signal generating device in the form of "direct memory access" according to the BAR address DEV_BAR_ADDR; The writing of sampled data and the reading of stored data are completed based on files.

2. The PTP data transmission method of the high-speed signal acquisition / generation device according to claim 1, It is characterized in that The storage capacity is C=4MB. Two storage spaces with a storage capacity of C are planned in the cache of the high-speed signal acquisition / generation device, that is, 8MB of storage space is planned in the cache of the high-speed signal acquisition / generation device. The 8MB of storage space in the internal cache of the high-speed signal acquisition device is mapped to the host physical memory in the form of a BAR address. This 8MB of storage space is defined as two end-to-end continuous sub-storage spaces for "ping-pong cache" access. The BAR address of sub-storage space 1 is defined as DEV_BAR1_ADDR, and the BAR address of sub-storage space 2 is defined as DEV_BAR2_ADDR. The NVMe solid state drive end writing, i.e. the high-speed signal acquisition device to NVMe SSD data transmission steps are: Step 3.1.1): Start the Host data storage software; Step 3.1.2): Check whether there are at least 4 NVMe solid-state drives and at least 1 high-speed signal acquisition device in the PTP data transmission system based on the PCIe bus; Step 3.1.3): Create file systems in the four NVMe SSDs in turn and mount drive letters; Step 3.1.4): Initialize the high-speed signal acquisition device to make it enter the acquisition preparation state; Step 3.1.5): When the high-speed signal acquisition device enters the acquisition preparation state, an 8MB storage space is planned in its internal cache to implement the PTP data transmission operation. In the host Host, the 8MB storage space in the internal cache of the high-speed signal acquisition device is mapped to the host Host physical memory in the form of a BAR address. This 8MB storage space is defined as two end-to-end continuous sub-storage spaces 1 and 2. The BAR address of sub-storage space 1 is defined as DEV_BAR1_ADDR, and the BAR address of sub-storage space 2 is defined as DEV_BAR2_ADDR; Step 3.1.6): Define the initial mapping BAR addresses of the four NVMe solid state drives in the host host memory as SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, SSD4_BAR_ADDR, where: SSD1_BAR_ADDR=DEV_BAR1_ADDR SSD2_BAR_ADDR=DEV_BAR1_ADDR+1MB SSD3_BAR_ADDR=DEV_BAR1_ADDR+2MB SSD4_BAR_ADDR=DEV_BAR1_ADDR+3MB Step 3.1.7): Create a main process control thread on the host host and bind the main process control thread to any thread CPU; Step 3.1.8): In the main process control thread, the file name and file path of the data file to be stored are respectively passed into the four NVMe solid-state drive file systems, so that the four NVMe solid-state drives simultaneously create files with the same file name in the same path; Step 3.1.9): Create four data writing sub-threads in the main process control thread, and bind these four data writing sub-threads to different thread CPUs respectively; Step 3.1.10): The BAR addresses SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, and SSD4_BAR_ADDR of the four NVMe solid-state drives are respectively passed to the four data writing sub-threads as mapping binding address variables of the four NVMe solid-state drives during direct memory access transmission; Step 3.1.11): In the main process control thread, control the high-speed signal acquisition device to start signal acquisition. At this time, the high-speed signal acquisition device initializes the internal read completion flag register DEV_RD_DONE_REG = 0, that is, the internal storage space read operation is not completed, the sub-storage space 1 empty flag DEV_MEM1_EMPTY = 1, that is, the sub-storage space 1 is empty, and the sub-storage space 2 empty flag DEV_MEM2_EMPTY = 1, that is, the sub-storage space 2 is empty; Step 3.1.12): The high-speed signal acquisition device determines the value of the empty flag DEV_MEM1_EMPTY of the sub-storage space 1. If it is 0, wait. If it is 1, set it to 0 and store the acquired data into the sub-storage space 1 with DEV_BAR1_ADDR as the starting address inside the device. Step 3.1.13): When the 4MB data of sub-storage space 1 is full, the high-speed signal acquisition device determines the value of the empty flag DEV_MEM2_EMPTY of sub-storage space 2. If it is 0, it waits. If it is 1, it sets it to 0, and immediately switches the collected data to be stored in the sub-storage space 2 with DEV_BAR2_ADDR as the starting address inside the device. At the same time, the high-speed signal acquisition device sets the internal valid memory register DEV_MEM_VALID_REG to 0, indicating that the currently readable sub-storage space is the sub-storage space 1 pointed to by DEV_BAR1_ADDR, and sends a read enable interrupt signal DEV_RD_ENABLE_INT to the host Host to notify the host Host to start reading data from sub-storage space 1; Step 3.1.14): After the host receives the interrupt signal DEV_RD_ENABLE_INT, it reads the value of the device valid memory register DEV_MEM_VALID_REG. At this time, DEV_MEM_VALID_REG = 0, indicating that the sub-storage space that can be read is the sub-storage space 1 pointed to by DEV_BAR1_ADDR. The DMA controller of the host moves the data to the host in the "direct memory access" mode according to the BAR address DEV_BAR1_ADDR. The host configures the BAR address as follows: SSD1_BAR_ADDR=DEV_BAR1_ADDR SSD2_BAR_ADDR=DEV_BAR1_ADDR+1MB SSD3_BAR_ADDR=DEV_BAR1_ADDR+2MB SSD4_BAR_ADDR=DEV_BAR1_ADDR+3MB Step 3.1.15): The host Host initiates NVMe SSD file write events through four data writing sub-threads respectively, and the NVMe controllers of the four NVMe SSDs immediately call their own DMA controllers to read data from the host Host's BAR address: SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, SSD4_BAR_ADDR to their own internal non-volatile memories; Step 3.1.16): After the NVMe SSD file write events of the four data writing sub-threads are executed, the host Host sets the signal acquisition device read completion flag register DEV_RD_DONE_REG to 1 to notify the high-speed signal acquisition device that the transmission is completed; Step 3.1.17): After the high-speed signal acquisition device detects that the read completion flag register DEV_RD_DONE_REG = 1, the sub-storage space 1 empty flag DEV_MEM1_EMPTY is set to 1, and the completion flag register DEV_RD_DONE_REG is set to 0; Step 3.1.18): After the 4MB data in sub-storage space 2 is filled, the high-speed signal acquisition device determines the value of the empty flag DEV_MEM1_EMPTY of sub-storage space 1. If it is 0, wait. If it is 1, set it to 0, and immediately switch the acquisition data to the sub-storage space 1 with DEV_BAR1_ADDR as the starting address inside the device. At the same time, the high-speed signal acquisition device sets the internal valid memory register DEV_MEM_VALID_REG to 1, indicating that the currently readable sub-storage space is the word storage space 2 pointed to by DEV_BAR2_ADDR, and sends the read enable interrupt signal DEV_RD_ENABLE_INT to the Host again to notify the Host to start reading data from sub-storage space 2; Step 3.1.19): After the host receives the interrupt signal DEV_RD_ENABLE_INT, it reads the value of the device valid memory register DEV_MEM_VALID_REG. At this time, DEV_MEM_VALID_REG = 1, indicating that the sub-storage space that can be read is the sub-storage space 2 pointed to by DEV_BAR2_ADDR. The DMA controller of the host moves the data to the host in the "direct memory access" mode according to the BAR address DEV_BAR2_ADDR. The host configures the BAR address as follows: SSD1_BAR_ADDR=DEV_BAR2_ADDR SSD2_BAR_ADDR=DEV_BAR2_ADDR+1MB SSD3_BAR_ADDR=DEV_BAR2_ADDR+2MB SSD4_BAR_ADDR=DEV_BAR2_ADDR+3MB Step 3.1.20): The host Host initiates NVMe SSD file write events through four data writing sub-threads. The NVMe controllers of the four NVMe SSDs immediately call their own DMA controllers to read data from the host Host's BAR address: SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, SSD4_BAR_ADDR to their own internal non-volatile memory. Step 3.1.21): After the NVMe SSD file write events of the four data writing sub-threads are executed, the host Host sets the signal acquisition device read completion flag register DEV_RD_DONE_REG to 1 to notify the high-speed signal acquisition device that the transmission is completed; Step 3.1.22): After the high-speed signal acquisition device detects that the read completion flag register DEV_RD_DONE_REG = 1, the sub-storage space 2 empty flag DEV_MEM2_EMPTY is set to 1, and the completion flag register DEV_RD_DONE_REG is set to 0; Step 3.1.23): Repeat steps 3.1.12) to 3.1.22) until all data of the specified file size is stored in the non-volatile memory of the NVMe SSD; Step 3.1.24): The main process control thread of the host Host controls the high-speed signal acquisition device to stop acquisition, closes and releases the four data writing sub-threads; Step 3.1.25): The host closes the file in the file system, closes and releases the main process control thread, and exits the data storage software.

3. The PTP data transmission method of the high-speed signal acquisition / generation device according to claim 2, It is characterized in that The NVMe solid state drive end reads out, that is, the data transmission from the NVMe SSD to the high-speed signal generating device is as follows: Step 3.2.1): Start the Host data reading software; Step 3.2.2): Check whether there are at least 4 NVMe solid-state drives and at least 1 high-speed signal generating device in the PTP data transmission system based on the PCIe bus; Step 3.2.3): Create file systems in the four NVMe SSDs in turn and mount drive letters; Step 3.2.4): Initialize the high-speed signal generating device to make it ready for generation; Step 3.2.5): When the high-speed signal generating device enters the generating preparation state, an 8MB storage space is planned in its internal cache to realize the PTP data transmission operation. In the host Host, the 8MB storage space in the internal cache of the high-speed signal generating device is mapped to the host Host physical memory in the form of BAR address. This 8MB storage space is defined as two end-to-end continuous sub-storage spaces 1 and 2 for "ping-pong cache" access. The BAR address of sub-storage space 1 is defined as DEV_BAR1_ADDR, and the BAR address of sub-storage space 2 is defined as DEV_BAR2_ADDR; Step 3.2.6): Define the initial mapping BAR addresses of the four NVMe solid state drives in the host memory as SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, SSD4_BAR_ADDR, where: SSD1_BAR_ADDR=DEV_BAR1_ADDR SSD2_BAR_ADDR=DEV_BAR1_ADDR+1MB SSD3_BAR_ADDR=DEV_BAR1_ADDR+2MB SSD4_BAR_ADDR=DEV_BAR1_ADDR+3MB Step 3.2.7): Create a main process control thread on the host host and bind the main process control thread to any thread CPU; Step 3.2.8): In the main process control thread, the file name and file path of the data file to be read are respectively passed into the four NVMe solid-state drive file systems, so that the four NVMe solid-state drives simultaneously open the file with the same file name in the same path; Step 3.2.9): Create four data reading sub-threads in the main process control thread, and bind these four data reading sub-threads to different thread CPUs respectively; Step 3.2.10): The BAR addresses SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, and SSD4_BAR_ADDR of the four NVMe solid-state drives are respectively passed to the four data reading sub-threads as mapping binding address variables of the four NVMe solid-state drives during direct memory access transmission; Step 3.2.11): In the main process control thread, control the high-speed signal generating device to start signal generation. At this time, the high-speed signal generating device initializes the internal valid memory register DEV_MEM_VALID_REG=0, the current writable sub-storage space is the word storage space 1 pointed to by DEV_BAR1_ADDR, the write completion flag register DEV_WR_DONE_REG=0, that is, the current write operation is not completed, the sub-storage space 1 empty flag DEV_MEM1_EMPTY=1, that is, the sub-storage space 1 is empty, the sub-storage space 2 empty flag DEV_MEM2_EMPTY=1, that is, the sub-storage space 2 is empty; Step 3.2.12): The high-speed signal generating device determines the value of the internal sub-storage space 1 empty flag DEV_MEM1_EMPTY. If it is 0, it waits. If it is 1, it sets the internal valid memory register DEV_MEM_VALID_REG to 0 and sends a write enable interrupt signal DEV_WR_ENABLE_INT to the host Host to notify the host Host to start writing data to the sub-storage space 1. Step 3.2.13): After the host Host receives the interrupt signal DEV_WR_ENABLE_INT, it reads the value of the valid memory register DEV_MEM_VALID_REG. At this time, DEV_MEM_VALID_REG = 0, indicating that the sub-storage space that can be written is the sub-storage space 1 pointed to by DEV_BAR1_ADDR. Then the host Host configures the BAR address as: SSD1_BAR_ADDR=DEV_BAR1_ADDR SSD2_BAR_ADDR=DEV_BAR1_ADDR+1MB SSD3_BAR_ADDR=DEV_BAR1_ADDR+2MB SSD4_BAR_ADDR=DEV_BAR1_ADDR+3MB Step 3.2.14): The host Host initiates NVMe SSD file read events through four data reading sub-threads respectively. The NVMe controllers of the four NVMe SSDs immediately call their own DMA controllers to read data from their own internal non-volatile memories to the BAR addresses of the host Host: SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, SSD4_BAR_ADDR; Step 3.2.15): After the NVMe SSD file read events of the four data read sub-threads are executed, the host Host sets the signal generating device write completion flag register DEV_WR_DONE_REG to 1 to notify the high-speed signal generating device that the transmission is completed; Step 3.2.16): After the high-speed signal generating device detects that the write completion flag register DEV_WR_DONE_REG = 1, it immediately sets the write completion flag register DEV_WR_DONE_REG to 0, and sets the sub-storage space 1 empty flag DEV_MEM1_EMPTY to 0; Step 3.2.17): The high-speed signal generating device determines the value of the internal sub-storage space 2 empty flag DEV_MEM2_EMPTY. If it is 0, it waits. If it is 1, it sets the internal valid memory register DEV_MEM_VALID_REG to 1 and sends a write enable interrupt signal DEV_WR_ENABLE_INT to the host Host to notify the host Host that it can start writing data to the sub-storage space 2. Step 3.2.18): After the high-speed signal generating device detects that the internal sub-storage space 1 empty flag DEV_MEM1_EMPTY=0, the internal signal generating circuit reads data from the sub-storage space 1 until all 4MB of data are read, and then sets the internal sub-storage space 1 empty flag DEV_MEM1_EMPTY to 1; Step 3.2.19): After the host Host receives the interrupt signal DEV_WR_ENABLE_INT, it reads the value of the valid memory register DEV_MEM_VALID_REG. At this time, DEV_MEM_VALID_REG = 1, indicating that the sub-storage space that can be written is the sub-storage space 2 pointed to by DEV_BAR2_ADDR. Then the host Host configures the BAR address as: SSD1_BAR_ADDR=DEV_BAR2_ADDR SSD2_BAR_ADDR=DEV_BAR2_ADDR+1MB SSD3_BAR_ADDR=DEV_BAR2_ADDR+2MB SSD4_BAR_ADDR=DEV_BAR2_ADDR+3MB Step 3.2.20): The host Host initiates NVMe SSD file read events through four data reading sub-threads respectively. The NVMe controllers of the four NVMe SSDs immediately call their own DMA controllers to read data from their own internal non-volatile memories to the BAR addresses of the host Host: SSD1_BAR_ADDR, SSD2_BAR_ADDR, SSD3_BAR_ADDR, SSD4_BAR_ADDR; Step 3.2.21): After the NVMe SSD file read events of the four data read sub-threads are executed, the host Host sets the signal generating device write completion flag register DEV_WR_DONE_REG to 1 to notify the high-speed signal generating device that the transmission is completed; Step 3.2.22): After the high-speed signal generating device detects that the write completion flag register DEV_WR_DONE_REG = 1, it immediately sets the write completion flag register DEV_WR_DONE_REG to 0, and sets the sub-storage space 2 empty flag DEV_MEM2_EMPTY to 0; Step 3.2.23): After the high-speed signal generating device detects that the internal sub-storage space 2 empty flag DEV_MEM2_EMPTY=0, the internal signal generating circuit reads data from the sub-storage space 2 until all 4MB of data are read, and then sets the internal sub-storage space 2 empty flag DEV_MEM2_EMPTY to 1; Step 3.2.24): Repeat steps 3.2.12) to 3.2.23) until all data of the specified file size is read out from the non-volatile memories of the four NVMe solid state drives; Step 3.2.25): The main process control thread of the host controls the high-speed signal generating device to stop generating, closes and releases the four data writing sub-threads; Step 3.2.26): The host Hos end closes the file in the file system, closes and releases the main process control thread, and exits the data reading software.

Images