Data transmission circuit and method, storage device and storage medium

Abstract

The invention discloses a data transmission circuit and method, a storage device and a storage medium, and the data transmission circuit comprises a data comparison module which is used for receiving transmission data, comparing the digit of data in a first level state with the digit of data in a second level state in the transmission data, outputting a first enable signal based on the comparison result; wherein the transmission data comprises N bits; n is an integer greater than 1; and the data transmission module is used for receiving the first enable signal and selecting a corresponding transmission path based on the first enable signal to transmit the transmission data.

Description

Technical Field

[0001] The present application relates to the field of semiconductor storage technology, and in particular to a data transmission circuit, method, storage device and storage medium. Background Art

[0002] In the storage array area of ​​a semiconductor storage device, the data transmission current on the data line corresponding to the read and write operations is an important performance indicator of the power consumption of the semiconductor storage device. As semiconductor storage devices are continuously iterated and updated, the requirements for the data transmission current on the data line corresponding to the read and write operations are constantly increasing. Summary of the invention

[0003] Based on this, the present application provides a data transmission circuit, method, storage device and storage medium, which can effectively reduce the transmission current corresponding to the data transmission path.

[0004] To achieve the above object, the present application provides a data transmission circuit, comprising:

[0005] A data comparison module, configured to receive transmission data, compare the number of bits of data in the first level state and the number of bits of data in the second level state in the transmission data, and output a first enable signal based on the comparison result; wherein the transmission data includes N bits; and N is an integer greater than 1;

[0006] A data transmission module is used to receive and select a corresponding transmission path based on the first enable signal to transmit the transmission data.

[0007] In some embodiments, the data comparison module includes:

[0008] A comparison unit is used to receive the transmission data and compare the number of bits of data in the first level state and the number of bits of data in the second level state in the transmission data to obtain the comparison result; an enable signal generation unit is used to receive the comparison result and a read / write operation command, and output the first enable signal based on the comparison result and the read / write operation command.

[0009] In some embodiments, the enable signal generating unit is a trigger, the data end of the trigger is used to receive the comparison result; the clock end of the trigger is used to receive the read and write operation command; the output end of the trigger is used to output the first enable signal based on the comparison result and the read and write operation command.

[0010] In some embodiments, the data transmission module includes: a first path selection unit, used to receive the first enable signal and the transmission data, and generate first intermediate data; a first transmission unit, used to receive the first intermediate data and output it to a second path selection unit; and the second path selection unit, used to receive the first intermediate data and the first enable signal, and generate target data.

[0011] In some embodiments, the first path selection unit includes: a first inverting unit, used to receive the transmission data, and when the first enable signal is invalid, conduction generates the first intermediate data that is inverted with the transmission data; a first buffer unit, used to receive the transmission data, and when the first enable signal is valid, conduction generates the first intermediate data that is in phase with the transmission data.

[0012] In some embodiments, the second path selection unit includes: a second inverting unit, used to receive the first intermediate data, and when the first enable signal is invalid, conduct to generate the target data that is inverted with the first intermediate data; a second buffer unit, used to receive the first intermediate data, and when the first enable signal is valid, conduct to generate the target data that is in phase with the first intermediate data.

[0013] In some embodiments, the first inverting unit and the second inverting unit are both odd numbers of first inverters connected in series; the first buffer unit and the second buffer unit are both even numbers of second inverters connected in series; wherein the enable end of the first inverter receives the first enable signal, and the enable end of the second inverter receives the first enable signal.

[0014] In some embodiments, the enable end of the first inverter is the source of the first PMOS tube, connected to the first switch unit; wherein the first switch unit is turned on and connected to the power supply end when the first enable signal is invalid; the enable end of the second inverter is the source of the second PMOS tube, connected to the second switch unit; wherein the second switch unit is turned on and connected to the power supply end when the first enable signal is valid.

[0015] In some embodiments, the first switch unit and the second switch unit are two transistors of the same conductivity type; wherein a gate of one of the two transistors receives the first enable signal, and a gate of the other transistor receives a complementary signal of the first enable signal.

[0016] In some embodiments, the first switch unit and the second switch unit are two transistors of different conductivity types; wherein the gates of the two transistors receive the first enable signal simultaneously.

[0017] The present application also provides a data storage device, comprising any data transmission circuit described in any embodiment of the present application, for transmitting data for read and write operations.

[0018] The present application also provides a data transmission method, including:

[0019] receiving transmission data, and comparing the number of bits of data in a first level state and the number of bits of data in a second level state in the transmission data, and determining a first enable signal based on the comparison result;

[0020] A corresponding transmission path is selected based on the first enable signal to transmit the transmission data.

[0021] In some embodiments, the receiving of transmission data and comparing the number of bits of data in the transmission data in a first level state with the number of bits of data in a second level state, and determining a first enable signal based on the comparison result, includes: receiving the transmission data and comparing the number of bits of data in the transmission data in a first level state with the number of bits of data in a second level state to obtain the comparison result; and outputting the first enable signal based on the comparison result and the read / write operation command.

[0022] In some embodiments, selecting a corresponding transmission path to transmit the transmission data based on the first enable signal includes: generating and transmitting first intermediate data based on the first enable signal and the transmission data; generating and transmitting target data based on the first intermediate data and the first enable signal.

[0023] The present application also provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the data transmission method described in any one of the embodiments of the present application are implemented.

[0024] The embodiments of the present application provide a data transmission circuit, method, storage device and storage medium, wherein the data transmission circuit includes: a data comparison module, which is used to receive transmission data, and compare the number of bits of data in a first level state and the number of bits of data in a second level state in the transmission data, and output a first enable signal based on the comparison result; wherein the transmission data includes N bits; and N is an integer greater than 1; a data transmission module, which is used to receive and select a corresponding transmission path to transmit the transmission data based on the first enable signal; in this way, the number of bits of data in a first level state and the number of bits of data in a second level state in the transmission data are compared through the data comparison module, and the first enable signal is output based on the comparison result, and then the corresponding transmission path is selected through the data transmission module based on the first enable signal to transmit the transmission data in the same phase or inverse phase; in this way, the transmission current corresponding to the transmission data on the data line can be adaptively reduced.

[0025] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions provided in the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology description are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work:

[0027] Figure 1 A schematic diagram showing the composition structure of a data transmission circuit on a data line in the related art;

[0028] Figure 2 A schematic diagram showing the composition structure of a first data transmission circuit provided in an embodiment of the present application is shown;

[0029] Figure 3 A schematic diagram showing the structure of a second data transmission circuit provided in an embodiment of the present application is shown;

[0030] Figure 4 A schematic diagram showing the composition structure of a third data transmission circuit provided in an embodiment of the present application is shown;

[0031] Figure 5 A schematic diagram showing a partial circuit composition corresponding to data transmission of a read operation or a write operation using a data transmission circuit provided in an embodiment of the present application;

[0032] Figure 6 A schematic diagram of the structure of a data storage device provided in an embodiment of the present application;

[0033] Figure 7 A flowchart of a data transmission method provided in an embodiment of the present application;

[0034] Description of reference numerals:

[0035] 1-data storage device; 10-data transmission circuit; 11-data comparison module; 111-comparison unit; 112-enable signal generation unit; 12-data transmission module; 121-first path selection unit; 122-transmission unit; 123-second path selection unit; 1211-first inverting unit; 1212-first buffer unit; 1231-second inverting unit; 1232-second buffer unit. DETAILED DESCRIPTION

[0036] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. It is understandable that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only the parts related to the present application but not all structures are shown in the accompanying drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0037] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0038] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0039] In order to better understand the embodiments of the present application, the shortcomings existing in the related art are first described.

[0040] In the related art, in the storage array area of ​​the semiconductor storage device, the data transmission circuit corresponding to the read and write operations is as follows: Figure 1As shown, a schematic diagram of the composition structure of the data transmission circuit on the data line in the related art is shown; wherein, the data transmission circuit in the related art usually includes a data buffer unit set at both ends and a transmission unit in the middle part, and the data buffer unit is usually composed of two inverters; at the same time, the transmission unit usually includes a plurality of data buffer units; wherein, the data buffer unit can be composed of an even number of inverters connected in series; further, the transmission unit can also include a primary reference clock (PRC), and then the transmission unit can also be composed of the PRC and the data buffer unit arranged in sequence; illustratively, the data transmitted on the data line here can be the data corresponding to the read and write operation link, and with the continuous iteration and update of the semiconductor storage device, the transmission current requirements of the data transmission path corresponding to the read and write operation are constantly increasing, and the above transmission current can no longer meet the requirements; as shown in Table 1 below, it is the data transmitted on the data line in the related art, and the data transmitted on the data line here is taken as a binary system; wherein, for data 2 in Table 1, relative to data 1 in Table 1, the flipped dynamic current Idd (the current required to rise from logic 0 to logic 1) = 8*4 times; for data 3 in Table 1, the dynamic current Idd flipped is 0 times relative to data 2 in Table 1; for data 4 in Table 1, the dynamic current Idd flipped is 3*4 times relative to data 3 in Table 1; for data 5 in Table 1, the dynamic current Idd flipped is 5*4 times relative to data 4 in Table 1; and when data 1 to data 5 in Table 1 are transmitted in sequence, the corresponding number of dynamic current flips is: total = 16*4 times Idd, here only taking the rising current (Idd rising) as an example, those skilled in the art can understand that the current required to rise from logic 0 to logic 1 is generally greater than the current required to discharge from logic 1 to logic 0.

[0041] Table 1 Data transmitted on data line in related technology

[0042]

[0043] Based on the above problems, the present application provides the following embodiments:

[0044] First embodiment,

[0045] The present application embodiment provides a data transmission circuit 10, referring to Figure 2 As shown, a schematic diagram of the composition structure of the first data transmission circuit provided in an embodiment of the present application is shown; wherein, Figure 2 In the figure, a data transmission circuit 10 including a data comparison module 11 and a data transmission module 12 is taken as an example for illustration.

[0046] The data transmission circuit 10 comprises:

[0047] A data comparison module 11 is used to receive transmission data, compare the number of bits of data in the first level state and the number of bits of data in the second level state in the transmission data, and output a first enable signal based on the comparison result; wherein the transmission data includes N bits; and N is an integer greater than 1;

[0048] The data transmission module 12 is used to receive and select a corresponding transmission path to transmit the transmission data based on the first enable signal.

[0049] Here, the data transmission circuit 10 may refer to a related data transmission circuit located inside the data storage device 1; illustratively, the data transmission circuit 10 is located in the peripheral area of ​​the data storage device 1 and may be used to transmit data on the data line generated during data read and write operations.

[0050] Here, the transmitted data can be expressed in binary, such as: 1Byte=8bit; which corresponds to N bits, that is, N is 8; in the following other embodiments of the present application, the transmitted data is expressed in binary; wherein the first level state and the second level state can respectively refer to the high and low data in the transmitted data, for example, the data in the first level state can be "1"; the data in the second level state can be "0".

[0051] In other embodiments of the present application, data in the first level state refers to "1" in binary, and data in the second level state refers to "0" in binary.

[0052] Exemplarily, when the transmitted data is 10101011, the number of bits of data in the first level state and the number of bits of data in the second level state in the transmitted data are 5 and 3, respectively; the corresponding comparison result is: the number of bits of data in the first level state is greater than the number of bits of data in the second level state.

[0053] Here, the data comparison module 11 is used to receive the transmission data, and compare the number of 0 bits and the number of 1 bits in the transmission data, and then generate and output a first enable signal based on the comparison result and the received read / write operation command.

[0054] Here, the data transmission module 12 is used to receive and select a corresponding transmission path to transmit the transmission data based on the first enable signal, that is, to determine a transmission path for data flipping or data buffering of the transmission data, that is, based on the first enable signal, determine a transmission path for reducing the transmission current of the transmission data; further, the data transmission module 12 can determine whether to perform data flipping on the transmission data based on the first enable signal; wherein, either data flipping is performed or not, that is, normal data buffering is performed; here, data flipping can refer to changing data from "0" to "1", or from "1" to "0".

[0055] Among them, the data transmission module 12 determines a first transmission path for performing data flipping on the transmission data, or a second transmission path for performing data buffering on the transmission data, based on the first enable signal obtained by the data comparison module 11, and then correspondingly uses the first transmission path or the second transmission path to transmit the transmission data.

[0056] It should be noted that the implementation basis of this embodiment is: in a semiconductor storage device, when the number of "1" bits in a byte is more than "0", the data bus inversion function (Data Bus Inversion, DBI) can be used to invert the "0" and "1" of the entire byte, so that there are more "0" than "1", which is more power-saving than the original (before inversion) transmission signal, that is, it saves more corresponding current; here, because 0 refers to grounding and 1 refers to connecting to the power supply VDD, because it must be maintained at VDD, 1 consumes more power than 0.

[0057] The data transmission circuit provided by the embodiment of the present application comprises: a data comparison module, which is used to receive transmission data, and compare the number of bits of data in the transmission data in a first level state with the number of bits of data in a second level state, and output a first enable signal based on the comparison result; wherein the transmission data comprises N bits, and N is an integer greater than 1; a data transmission module, which is used to receive and select a corresponding transmission path to transmit the transmission data based on the first enable signal; in this way, by comparing the number of bits of data in the transmission data in a first level state with the number of bits of data in a second level state, and outputting a first enable signal based on the comparison result, and then selecting a corresponding transmission path based on the first enable signal to transmit the transmission data, such as: a transmission path for data flipping or data buffering of the transmission data, and then using the corresponding transmission path to transmit the transmission data in the same phase or inverse phase; in this way, the transmission current of the data transmitted on the data line can be adaptively reduced.

[0058] In some embodiments, the data transmission circuit 10 includes a data comparison module 11, which correspondingly includes: a comparison unit 111 and an enable signal generation unit 112; Figure 3 As shown, a schematic diagram of the composition structure of a second data transmission circuit provided in an embodiment of the present application is shown; wherein:

[0059] A comparing unit 111, configured to receive the transmission data, and compare the number of bits of data in the first level state and the number of bits of data in the second level state in the transmission data to obtain the comparison result;

[0060] The enable signal generating unit 112 is configured to receive the comparison result and the read / write operation command, and output the first enable signal based on the comparison result and the read / write operation command.

[0061] In some embodiments, the comparison unit 111 and the enable signal generation unit 112 are electrically connected to each other and are used to implement the relevant data comparison operation and the enable signal generation operation in the data comparison module 11 respectively.

[0062] In some embodiments, the comparison result can be expressed by using the fact that the number of bits of data in the first level state is greater than the number of bits of data in the second level state, or, the number of bits of data in the first level state is less than the number of bits of data in the second level state; or, the number of bits of data in the first level state is equal to the number of bits of data in the second level state.

[0063] Here, the enable signal generating unit 112 is used to receive the read-write operation command and the comparison result output by the comparison unit, and then output the first enable signal based on the comparison result and the read-write operation command; wherein, the enable signal generating unit 112 can be a flip-flop (Flip-Flop, FF), and the comparison unit 111 can be a data bus flip circuit.

[0064] Here, when the enable signal generating unit 112 is a trigger, the data end of the trigger is used to receive the comparison result output by the comparison unit 111; the clock end of the trigger is used to receive the read-write operation command; and the output end of the trigger is used to output the first enable signal based on the comparison result and the read-write operation command.

[0065] In some embodiments, when the first enable signal is valid at a high level by default, the enable signal generating unit 112 may generate and output a first enable signal of 1 accordingly when a read / write operation command is received and a comparison result indicates that the number of 0 bits in the transmission data is greater than the number of 1 bits. Then, in the data transmission module 12, based on the validity of the first enable signal, a first transmission path for buffering the transmission data may be selected to transmit the transmission data. Conversely, when the number of 0 bits in the transmission data is less than or equal to the number of 1 bits, a first enable signal of 0 may be generated and output accordingly. Then, in the data transmission module 12, based on the invalidity of the first enable signal, a second transmission path for flipping the transmission data may be selected to transmit the transmission data.

[0066] Correspondingly, when the first enable signal is valid at a low level, the enable signal generating unit 112, upon receiving a read / write operation command and a comparison result indicating that the number of 0 bits in the transmission data is greater than the number of 1 bits, correspondingly generates and outputs a first enable signal of 0, and then in the data transmission module 12, based on the validity of the first enable signal, a first transmission path for data buffering the transmission data can be selected to transmit the transmission data; conversely, when the number of 0 bits in the transmission data is less than or equal to the number of 1 bits, a first enable signal of 1 can be correspondingly generated and output, and then in the data transmission module 12, based on the invalidity of the first enable signal, a second transmission path for data flipping the transmission data can be selected to transmit the transmission data.

[0067] Among them, the first enable signal can be that a high level is valid and a corresponding low level is invalid; or, the first enable signal is that a low level is valid and a corresponding high level is invalid; this is not limited in any way in the embodiments of the present application.

[0068] Further, if Figure 4 FIG. 1 is a schematic diagram showing a composition structure of a third data transmission circuit provided in an embodiment of the present application, wherein the data transmission module 12 includes:

[0069] A first path selection unit 121, configured to receive the first enable signal and the transmission data, and generate first intermediate data;

[0070] The transmission unit 122 is used to receive the first intermediate data and output it to the second path selection unit 123;

[0071] The second path selection unit 123 is used to receive the first intermediate data and the first enable signal, and generate target data.

[0072] Here, the data transmission module 12 includes: a first path selection unit 121, a transmission unit 122 and a second path selection unit 123, which is used to generate first intermediate data that is inversely phase or in phase with the transmission data based on the invalidity or validity of the first enable signal, and then transmit the first intermediate data in the transmission unit 122 and output it to the second path selection unit 123, and synchronously generate target data that is inversely phase or in phase with the first intermediate data based on the invalidity or validity of the first enable signal; in this way, based on the comparison result between the number of bits of data in the first level state and the number of bits of data in the second level state in the transmission data, and the received read and write operation commands, determine the valid or invalid first enable signal, and then based on the valid or invalid first enable signal, adaptively flip or buffer the transmission data during the transmission process, thereby reducing the transmission current corresponding to the transmission data during the transmission process.

[0073] In some embodiments, the first path selection unit 121 may include: a first inverting unit 1211, configured to receive the transmission data and, when the first enable signal is invalid, conduct to generate the first intermediate data which is inverted with the transmission data;

[0074] The first buffer unit 1212 is used to receive the transmission data and, when the first enable signal is valid, conduct to generate the first intermediate data in phase with the transmission data.

[0075] Here, in the first path selection unit 121, if the first enable signal is invalid, the first inverting unit 1211 inside it is selected to be turned on, that is, the transmission path for flipping the transmission data is selected, and the transmission data is transmitted to obtain first intermediate data that is inverted to the transmission data; if the first enable signal is valid, the first buffer unit 1212 inside it is selected to be turned on, that is, the transmission path for buffering the transmission data is selected, and the transmission data is transmitted to obtain first intermediate data that is in phase with the transmission data.

[0076] In some embodiments, the second path selection unit 123 may include: a second inverting unit 1231, configured to receive the first intermediate data and, when the first enable signal is invalid, conduct to generate the target data inverted with the first intermediate data;

[0077] The second buffer unit 1232 is used to receive the first intermediate data, and when the first enable signal is valid, turn on to generate the target data in the same phase as the first intermediate data.

[0078] Here, in the second path selection unit 123, if the first enable signal is invalid, the second inverting unit 1231 inside it is selected to be turned on, that is, the transmission path for performing data flipping on the first intermediate data is selected, and the first intermediate data is transmitted to obtain target data that is inverted with the first intermediate data; if the first enable signal is valid, the second buffer unit 1232 inside it is selected to be turned on, that is, the transmission path for performing data buffering on the first intermediate data is selected, and the first intermediate data is transmitted to obtain target data that is in phase with the first transmission data.

[0079] In some embodiments, the first inverting unit 1211 and the second inverting unit 1231 are both odd numbers of first inverters connected in series;

[0080] The first buffer unit 1212 and the second buffer unit 1232 are both second inverters connected in series in an even number;

[0081] The enable terminal of the first inverter receives the first enable signal, and the enable terminal of the second inverter receives the first enable signal.

[0082] Here, the first inverting unit 1211 included in the first path selection unit 121 and the second inverting unit 1231 included in the second path selection unit 123 may be the same odd number of first inverters connected in series, or different odd numbers of first inverters connected in series.

[0083] Correspondingly, the first buffer unit 1212 included in the first path selection unit 121 and the second buffer unit 1232 included in the second path selection unit 123 may both be the same even number of second inverters connected in series, or may be different even numbers of second inverters connected in series.

[0084] It should be noted that the enable end of the first inverter and the enable end of the second inverter can both receive the first enable signal; here, the first inverter and the second inverter can be inverters of the same type or inverters of different types.

[0085] It should be noted that the first inverter and the second inverter may both be devices that invert the phase of the input signal by 180 degrees.

[0086] In some embodiments, the first inverter and the second inverter may both be conventional complementary metal oxide semiconductor (CMOS) inverters, that is, the first inverter and the second inverter are both composed of PMOS field effect transistors and NMOS field effect transistors in a symmetrical and complementary form.

[0087] Here, in the case where both the first inverter and the second inverter are inverters composed of a PMOS field effect transistor and an NMOS field effect transistor, the enable terminals of the first inverter and the second inverter may be the following specific examples:

[0088] The enable terminal of the first inverter is the source of the first PMOS tube, connected to the first switch unit; wherein the first switch unit is turned on and connected to the power supply terminal when the first enable signal is invalid;

[0089] The enable terminal of the second inverter is the source of the second PMOS tube, which is connected to the second switch unit; wherein the second switch unit is turned on and connected to the power supply terminal when the first enable signal is valid.

[0090] In some embodiments, the first switch unit and the second switch unit are two transistors of the same conductivity type;

[0091] The gate of one of the two transistors receives the first enable signal, and the gate of the other transistor receives a complementary signal of the first enable signal.

[0092] Here, the first switch unit and the second switch unit can be MOS tubes of the same type, wherein the gate of the first switch unit receives a first enable signal, and the gate of the second switch unit receives a complementary signal of the first enable signal, that is, its corresponding inverted signal.

[0093] In some embodiments, the first switch unit and the second switch unit are two transistors of different conductivity types; wherein the gates of the two transistors receive the first enable signal simultaneously.

[0094] Here, when the first switch unit and the second switch unit are MOS tubes of different conductivity types, the gate of the first switch unit and the gate of the second switch unit can receive the first enable signal at the same time.

[0095] In the above embodiments, in the data transmission circuit 10, a data comparison module 11 is used to compare the number of bits of data in the first level state and the number of bits of data in the second level state in the transmission data on the data line in the read and write operation links, and based on the comparison result and the read and write operation command, a corresponding transmission path is selected to transmit the transmission data, that is, a transmission path for data flipping or data buffering of the transmission data is selected, so as to realize in-phase transmission or anti-phase transmission of the transmission data, which can realize adaptive reduction of the transmission current of the transmission data on the transmission line in the read and write operation links.

[0096] The data transmission circuit 10 provided in this embodiment is applied to a semiconductor storage device to transmit data on a data line corresponding to a read / write operation. The corresponding data transmission circuit 10 is as follows: Figure 5 As shown, a schematic diagram of the partial circuit composition corresponding to the data transmission of the read and write operation data by the data transmission circuit provided in the embodiment of the present application is shown; wherein, during the data transmission process, the number of bits of "1" and "0" in the transmission data on the data line (taking binary as an example) is first compared, and a first enable signal is generated based on the comparison result and the read and write operation command, and then based on the generated first enable signal, it is determined whether the transmission data needs to be flipped, that is, the corresponding Figure 5 1211 shown in the figure, the first inverting unit; or, data buffering, that is, corresponding to Figure 5 1212 shown in the figure is the first buffer unit; and then correspondingly, after passing through 1211 or 1212, it passes through the transmission unit, that is, 122, and then adaptively synchronizes through the second inverting unit 1231, or the second buffer unit 1232. Corresponding to the embodiment of the present application, when the number of bits of 1 in the transmission data on the data line is more than 0, the transmission data can be flipped (read operation or write operation is not limited here). Table 2 shows the data at different nodes in the data transmission circuit provided in the embodiment of the present application. Among them, the data corresponding to the data flipping or data buffering of the transmission data can be referred to Table 2; here, for data 2 in Table 2, because the number of bits of 1 in data 2 is more than 0, the data is flipped during the transmission process, so that the dynamic current Idd (the current required for the rise from logic 0 to logic 1) of the flipping of data 2 in Table 2 is 0 times relative to data 1 in Table 2; for data 3 in Table 2, there are also more bits of 1 than 0, and the data is flipped during the transmission process, so that the dynamic current Idd of the flipping of data 3 in Table 2 is 3*2 times relative to data 2 in Table 2; for data 4 in Table 2, the number of bits of 1 is less than 0, and the data is buffered during the transmission process, so that The data 4 in Table 2 has a flipped dynamic current Idd of 0 times relative to the data 3 in Table 2; for the data 5 in Table 2, the number of 1 bits is greater than that of 0 bits, and thus the data is flipped during the transmission process, so that the data 5 in Table 2 has a flipped dynamic current Idd of 0 times relative to the data 4 in Table 2; and then when the data 1 to the data 5 in Table 2 are transmitted in sequence, the corresponding flipped dynamic current times are: total = 3*2 times Idd; relative to the same data 1 to the data 5 transmitted on the data line in the above related technology (refer to Table 1 and the corresponding description, the required flipped dynamic current times are: total = 16*4 times Idd), the transmission current corresponding to the data transmitted on the data line is significantly reduced.

[0097] Table 2 Data at different nodes in the data transmission circuit provided by the embodiment of the present application

[0098]

[0099] Second embodiment,

[0100] The present application embodiment provides a data storage device 1, referring to Figure 6 As shown, it is a schematic diagram of the composition structure of a data storage device provided in an embodiment of the present application; wherein, the data storage device 1 includes any of the data transmission circuits 10 provided in the examples of the present application, which is used to transmit data for read and write operations.

[0101] Here, the relevant definitions or descriptions about the data storage device 1 can refer to the specific definitions about the data transmission circuit 10 in the above embodiment, which will not be repeated here.

[0102] The third embodiment,

[0103] The present application provides a data transmission method, referring to Figure 7 FIG. 1 is a flow chart of a data transmission method provided in an embodiment of the present application, referring to FIG. Figure 7 The steps shown are explained below:

[0104] Step S101, receiving transmission data, and comparing the number of bits of data in a first level state and the number of bits of data in a second level state in the transmission data, and determining a first enable signal based on the comparison result; wherein the transmission data includes N bits; and N is an integer greater than 1;

[0105] Step S102: Select a corresponding transmission path based on the first enable signal to transmit the transmission data.

[0106] In some embodiments, a transmission path for reducing transmission power consumption of the transmission data may be determined based on the first enable signal, and the transmission path may be used to transmit the transmission data.

[0107] Here, for the specific implementation process, reference may be made to the detailed description of the data transmission circuit 10 in the above embodiment, which will not be described in detail here.

[0108] In some embodiments, the above step S101 may be implemented by the following steps S1011 and S1012 (not shown in the figure):

[0109] Step S1011, receiving the transmission data, and comparing the number of bits of data in the first level state and the number of bits of data in the second level state in the transmission data to obtain the comparison result;

[0110] Step S1012: output the first enable signal based on the comparison result and the read / write operation command.

[0111] Meanwhile, the above step S102 can be implemented by the following steps S1021 and S1022 (not shown in the figure):

[0112] Step S1021 : Generate and transmit first intermediate data based on the first enable signal and the transmission data.

[0113] Step S1022: Generate and transmit target data based on the first intermediate data and the first enable signal.

[0114] In addition, the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the data transmission method provided in any of the above embodiments are implemented.

[0115] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0116] The features disclosed in several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0117] The above are only some embodiments of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A data transmission circuit, characterized in that: The data transmission circuit comprises: A data comparison module, configured to receive transmission data, compare the number of bits of data in the first level state and the number of bits of data in the second level state in the transmission data, and output a first enable signal based on the comparison result; wherein the transmission data includes N bits; and N is an integer greater than 1; A data transmission module is used to receive and select a corresponding transmission path based on the first enable signal to transmit the transmission data.

2. The data transmission circuit according to claim 1, characterized in that: The data comparison module comprises: a comparing unit, configured to receive the transmission data, and compare the number of bits of data in the first level state and the number of bits of data in the second level state in the transmission data to obtain the comparison result; The enable signal generating unit is used to receive the comparison result and the read / write operation command, and output the first enable signal based on the comparison result and the read / write operation command.

3. The data transmission circuit according to claim 2, characterized in that: The enable signal generating unit is a trigger, The data terminal of the trigger is used to receive the comparison result; The clock terminal of the trigger is used to receive the read and write operation command; The output end of the trigger is used to output the first enable signal based on the comparison result and the read / write operation command.

4. The data transmission circuit according to claim 1, characterized in that: The data transmission module comprises: A first path selection unit, configured to receive the first enable signal and the transmission data, and generate first intermediate data; A transmission unit, configured to receive the first intermediate data and output the data to a second path selection unit; The second path selection unit is used to receive the first intermediate data and the first enable signal to generate target data.

5. The data transmission circuit according to claim 4, characterized in that: The first path selection unit comprises: a first inverting unit, configured to receive the transmission data and, when the first enable signal is invalid, conduct to generate the first intermediate data which is inverted with the transmission data; The first buffer unit is configured to receive the transmission data and, when the first enable signal is valid, conduct to generate the first intermediate data in phase with the transmission data.

6. The data transmission circuit according to claim 5, characterized in that: The second path selection unit includes: a second inverting unit, configured to receive the first intermediate data, and, when the first enable signal is invalid, conduct to generate the target data which is inverted with respect to the first intermediate data; The second buffer unit is used to receive the first intermediate data and, when the first enable signal is valid, conduct to generate the target data in phase with the first intermediate data.

7. The data transmission circuit according to claim 6, characterized in that: The first inverting unit and the second inverting unit are both an odd number of first inverters connected in series; The first buffer unit and the second buffer unit are both second inverters connected in series in an even number; The enable terminal of the first inverter receives the first enable signal, and the enable terminal of the second inverter receives the first enable signal.

8. The data transmission circuit according to claim 7, characterized in that: The enable terminal of the first inverter is the source of the first PMOS tube, connected to the first switch unit; wherein the first switch unit is turned on and connected to the power supply terminal when the first enable signal is invalid; The enable terminal of the second inverter is the source of the second PMOS tube, which is connected to the second switch unit; wherein the second switch unit is turned on and connected to the power supply terminal when the first enable signal is valid.

9. The data transmission circuit according to claim 8, characterized in that: The first switch unit and the second switch unit are two transistors of the same conductivity type; The gate of one of the two transistors receives the first enable signal, and the gate of the other transistor receives a complementary signal of the first enable signal.

10. The data transmission circuit according to claim 8, characterized in that: The first switch unit and the second switch unit are two transistors of different conductivity types; wherein the gates of the two transistors receive the first enable signal simultaneously.

11. A storage device, characterized in that: include: The data transmission circuit according to any one of claims 1 to 10, used for transmitting data of read and write operations.

12. A data transmission method, characterized in that: include: Receive transmission data, and compare the number of bits of data in the first level state and the number of bits of data in the second level state in the transmission data, and determine a first enable signal based on the comparison result; wherein the transmission data includes N bits; and N is an integer greater than 1; A corresponding transmission path is selected based on the first enable signal to transmit the transmission data.

13. The data transmission method according to claim 12, characterized in that: The receiving transmission data, and comparing the number of bits of data in the first level state and the number of bits of data in the second level state in the transmission data, and determining the first enable signal based on the comparison result, comprises: receiving the transmission data, and comparing the number of bits of data in the first level state and the number of bits of data in the second level state in the transmission data to obtain the comparison result; The first enable signal is output based on the comparison result and the read / write operation command.

14. The data transmission method according to claim 12, characterized in that: The selecting a corresponding transmission path based on the first enable signal to transmit the transmission data includes: Based on the first enable signal and the transmission data, generate and transmit first intermediate data; Based on the first intermediate data and the first enable signal, target data is generated and transmitted.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the data transmission method according to any one of claims 12 to 14 are implemented.

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