Capacitor assembly

Abstract

The present disclosure provides a capacitor assembly. The capacitor assembly includes a substrate having a first surface and a second surface opposite to each other; a first intermediate layer disposed on the first surface of the substrate, the first intermediate layer including a first trench; a first trench capacitor disposed in the first trench; a second intermediate layer disposed on the second surface of the substrate, the second intermediate layer including a second trench; a second trench capacitor disposed in the second trench; and a through via passing through the substrate to connect the first trench capacitor and the second trench capacitor to each other.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0074866 filed on June 12, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a capacitor assembly. Background Art

[0003] Recently, the thickness of portable IT products such as smartphones and wearable devices has been reduced, resulting in an increased demand for reducing the thickness of passive components to reduce the thickness of the entire package. For this reason, research on thin-film silicon capacitors that can achieve further reduced thickness compared to multilayer ceramic capacitors (MLCCs) has been actively conducted.

[0004] Such thin film silicon capacitors have a disadvantage of having lower capacitance relative to mounting area compared to multilayer ceramic capacitors according to the prior art. Therefore, it is necessary to conduct research on thin film silicon capacitors having high capacitance relative to the same mounting area. Summary of the invention

[0005] One aspect of the present disclosure provides a capacitor assembly having high capacitance per unit area.

[0006] Aspects of the present disclosure are not limited to those set forth herein and will be more readily understood during the description of specific example embodiments.

[0007] According to one aspect of the present disclosure, a capacitor assembly is provided, comprising: a substrate having a first surface and a second surface opposite to each other; a first intermediate layer disposed on the first surface of the substrate, the first intermediate layer comprising a first groove; a first trench capacitor disposed in the first groove; a second intermediate layer disposed on the second surface of the substrate, the second intermediate layer comprising a second groove; a second trench capacitor disposed in the second groove; and a through-hole passing through the substrate to connect the first trench capacitor and the second trench capacitor to each other.

[0008] According to example embodiments of the present disclosure, a capacitor assembly may have a high capacitance per unit area. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a schematic plan view of a capacitor assembly according to an example embodiment of the present disclosure;

[0011] Figure 2 It is along Figure 1 A schematic cross-sectional view taken along line II' of ;

[0012] Figure 3 It is along Figure 2 A schematic cross-sectional view taken along line II-II';

[0013] Figure 4 yes Figure 3 Variations of;

[0014] Figure 5 yes Figure 2 Variations of;

[0015] Figure 6 is a schematic plan view of a capacitor assembly according to another example embodiment of the present disclosure;

[0016] Figure 7 It is along Figure 6 A schematic cross-sectional view taken along line III-III';

[0017] Figure 8 It is along Figure 6 A schematic cross-sectional view taken along line IV-IV' of ; and

[0018] Figures 9 to 15 is a cross-sectional view of main processes of a method of manufacturing a capacitor assembly according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Hereinafter, example embodiments of the present disclosure are described with reference to the accompanying drawings. However, the present disclosure may be illustrated in many different forms and should not be construed as being limited to the specific example embodiments set forth herein. In addition, example embodiments of the present disclosure may be provided to more fully describe the present disclosure to those skilled in the art. Therefore, for clarity of description, the shapes and sizes of the elements in the accompanying drawings may be exaggerated, and the elements indicated by the same reference numerals in the accompanying drawings may be the same elements.

[0020] In order to clearly illustrate the present disclosure, parts irrelevant to the description are omitted, and the size is exaggerated to clearly indicate layers and regions, and similar parts having the same function in the same scope are represented by similar reference numerals throughout the specification. Throughout the specification, unless otherwise specifically stated, the term "comprising" or "including" will be understood to include the described elements but not exclude other elements.

[0021] Figure 1 is a schematic plan view of a capacitor assembly according to an example embodiment of the present disclosure. Figure 2 It is along Figure 1 Schematic cross-sectional view taken along line II'. Figure 3 It is along Figure 2 Schematic cross-sectional view taken along line II-II'. Figure 4 yes Figure 3 variants.

[0022] Reference Figure 1 and Figure 2 , the capacitor assembly 100 according to example embodiments of the present disclosure may include a substrate 110 , intermediate layers 121 and 122 , trench capacitors 140 and 160 , and through vias 151 and 152 .

[0023] The substrate 110 may have a first surface 101 and a second surface 102 opposite to each other in a first direction DR1. The substrate 110 may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-IV compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 110 may be formed using, for example, a bulk wafer, but the present disclosure is not limited thereto.

[0024] The first intermediate layer 121 may be disposed on the first surface 101 of the substrate 110 and may include a first trench TR1. The second intermediate layer 122 may be disposed on the second surface 102 of the substrate 110 and may include a second trench TR2. The intermediate layers 121 and 122 may include an insulating material such as an oxide, a nitride, or a combination thereof. The intermediate layers 121 and 122 may include, for example, an oxide film of the substrate 110 or a natural oxide film of the substrate 110.

[0025] The intermediate layers 121 and 122 including oxide and / or nitride may have an etching rate higher than that of the substrate 110, and the etching amount may be more accurately controlled. Therefore, the trenches TR1 and TR2 may be formed in the intermediate layers 121 and 122 using an etching process or the like, thereby ensuring process ease and process accuracy compared to the trenches TR1 and TR2 formed in the substrate 110.

[0026] The first trench TR1 may extend from one surface of the first intermediate layer 121 toward the first surface 101 of the substrate 110 in the first direction DR1. The second trench TR2 may extend from one surface of the second intermediate layer 122 toward the second surface 102 of the substrate 110 in the first direction DR1.

[0027] The number or arrangement of the first trench TR1 and the second trench TR2 does not need to be particularly limited. It is sufficient to provide at least one of the first trench TR1 and the second trench TR2. However, the first intermediate layer 121 may preferably include a plurality of first trenches TR1, and the second intermediate layer 122 may preferably include a plurality of second trenches TR2. The height of each of the first trench TR1 and the second trench TR2 in the first direction DR1 does not need to be particularly limited, and may be tens of nm to tens of μm depending on the size or target capacitance of the capacitor assembly 100.

[0028] It is shown that the first trench TR1 and the second trench TR2 include a cross section having a rectangular shape, but the present disclosure is not limited thereto. The first trench TR1 and the second trench TR2 may include a cross section having various shapes such as a circular, elliptical, and trapezoidal shape. In addition, the first trench TR1 and the second trench TR2 may have inclined side surfaces so that their widths decrease toward the first surface 101 and the second surface 102 of the substrate 110, respectively. The first trench TR1 and the second trench TR2 may have lower surfaces protruding toward the first surface 101 and the second surface 102, respectively, but the present disclosure is not limited thereto.

[0029] Reference Figure 3 , the plurality of first trenches TR1 may be disposed to be spaced apart from each other in a second direction DR2 perpendicular to the first direction DR1, and each of the plurality of first trenches TR1 may extend along a third direction DR3 perpendicular to the first direction DR1 and the second direction DR2. However, the present disclosure is not limited thereto. For example, Figure 4 As shown in , in example embodiments, a plurality of first trenches TR1 may be disposed spaced apart from each other in the second direction DR2 and the third direction DR3. In addition, the second trenches TR2 may be symmetrical with the first trenches TR1 in the first direction DR1, and thus the above description of the shape of the first trenches TR1 may be applied to the second trenches TR2 in the same manner.

[0030] Reference Figure 2 , the first trench capacitor 140 may be disposed in the first trench TR1, and the second trench capacitor 160 may be disposed in the second trench TR2. The shapes of the first trench capacitor 140 and the second trench capacitor 160 do not need to be particularly limited, but for example, the first trench capacitor 140 may include a first dielectric layer 143 and a first electrode 141 and a second electrode 142, and the first dielectric layer 143 is interposed between the first electrode 141 and the second electrode 142, and the second trench capacitor 160 may include a second dielectric layer 163 and a third electrode 161 and a fourth electrode 162, and the second dielectric layer 163 is interposed between the third electrode 161 and the fourth electrode 162.

[0031] The first electrode 141 may conformally cover one surface of the first intermediate layer 121 and the inner walls of the plurality of first trenches TR1, and the third electrode 161 may conformally cover one surface of the second intermediate layer 122 and the inner walls of the plurality of second trenches TR2. The first electrode 141 and the second electrode 142 may be disposed opposite to each other, and the first dielectric layer 143 is interposed between the first electrode 141 and the second electrode 142, and the third electrode 161 and the fourth electrode 162 may be disposed opposite to each other, and the second dielectric layer 163 is interposed between the third electrode 161 and the fourth electrode 162, thereby forming the first trench capacitor 140 and the second trench capacitor 160 having a metal-insulator-metal (MIM) structure. Voltages having different polarities may be applied between the first electrode 141 and the second electrode 142, and voltages having different polarities may be applied between the third electrode 161 and the fourth electrode 162, thereby forming the capacitances of the first trench capacitor 140 and the second trench capacitor 160, respectively.

[0032] The first electrode 141, the second electrode 142, the third electrode 161 and the fourth electrode 162 may include, for example, metal, metal oxide, metal nitride, metal oxynitride, doped polysilicon and some other suitable conductive material or a combination thereof. The first electrode 141, the second electrode 142, the third electrode 161 and the fourth electrode 162 may include, for example, copper (Cu), titanium (Ti), titanium nitride (Ti), tantalum (Ta) and tantalum nitride (Ta). However, the present disclosure is not limited thereto.

[0033] The first dielectric layer 143 and the second dielectric layer 163 may include, for example, at least one of silicon oxide, zirconium oxide, hafnium oxide, niobium oxide, titanium oxide, lanthanum oxide, tantalum oxide, lithium oxide, and aluminum oxide. However, the present disclosure is not limited thereto. In addition, the first dielectric layer 143 and the second dielectric layer 163 may be formed as a composite layer in which a plurality of metal oxides are stacked to improve leakage characteristics. For example, the first dielectric layer 143 and the second dielectric layer 163 may be a composite layer in which zirconium oxide-aluminum oxide-zirconium oxide are sequentially stacked.

[0034] In example embodiments, the capacitor assembly 100 may include a first cover layer 131 covering the first trench capacitor 140 and a second cover layer 132 covering the second trench capacitor 160. The first cover layer 131 and the second cover layer 132 may be mainly used to protect the first trench capacitor 140 and the second trench capacitor 160, respectively. Figures 2 to 4 , the empty space inside the first trench TR1 may be filled with the first capping layer 131 , and the empty space inside the second trench TR2 may be filled with the second capping layer 132 .

[0035] The cover layers 131 and 132 may include the same material as that of the intermediate layers 121 and 122, but the present disclosure is not limited thereto. As desired, the first intermediate layer 121 and the first cover layer 131 may include different materials, and the second intermediate layer 122 and the second cover layer 132 may include different materials. As will be described below, the first cover layer 131 may be formed integrally with the first dielectric layer 143, and the second cover layer 132 may be formed integrally with the second dielectric layer 163. That is, the first cover layer 131 and the first dielectric layer 143 may include the same material, and the second cover layer 132 and the second dielectric layer 163 may include the same material. Therefore, in order to ensure high κ (dielectric constant) characteristics, the cover layers 131 and 132 may include a high κ (dielectric constant) dielectric material having a dielectric constant higher than that of the intermediate layers 121 and 122. That is, the dielectric constant of the same material of the first capping layer 131 and the first dielectric layer 143 may be higher than the dielectric constant of the first intermediate layer 121, and the dielectric constant of the same material of the second capping layer 132 and the second dielectric layer 163 may be higher than the dielectric constant of the second intermediate layer 122. As an example, the intermediate layers 121 and 122 may include silicon oxide, and the capping layers 131 and 132 may include hafnium oxide, but the present disclosure is not limited thereto.

[0036] Reference Figure 2 , the through vias 151 and 152 may pass through the substrate 110 to connect the first trench capacitor 140 and the second trench capacitor 160 to each other. More specifically, the through vias 151 and 152 may include a first through via 151 connecting the first electrode 141 and the third electrode 161 to each other and a second through via 152 connecting the second electrode 142 and the fourth electrode 162 to each other, the second through via 152 being disposed to be spaced apart from the first through via 151.

[0037] The through vias 151 and 152 may be filled with the conductive materials 181 and 182 (i.e., the conductive materials 181 and 182 are part of the through vias 151 and 152), so that the first trench capacitor 140 and the second trench capacitor 160 may be electrically connected to each other in parallel. That is, the capacitance of the capacitor assembly 100 may be the sum of the respective capacitances of the first trench capacitor 140 and the second trench capacitor 160 electrically connected to each other in parallel, thereby increasing the capacitance per unit area.

[0038] The through vias 151 and 152 may have inclined side surfaces so that their widths increase or decrease from the first surface 101 to the second surface 102, but the present disclosure is not limited thereto. It is sufficient as long as the conductive materials 181 and 182 include metal or other suitable conductive materials, and the conductive materials 181 and 182 may include copper (Cu), titanium (Ti), titanium nitride (TiN), etc., but the present disclosure is not limited thereto. In addition, the conductive materials 181 and 182 may fill the through vias 151 and 152. In addition, the first dielectric layer 143 and the second dielectric layer 163 may be spaced apart from the through vias 151 and 152.

[0039] In example embodiments, the capacitor assembly 100 may further include: first and second connection vias CV1 and CV2, which pass through the first intermediate layer 121, the first and second connection vias CV1 and CV2 are disposed to be spaced apart from each other, and a first trench TR1 is interposed between the first and second connection vias CV1 and CV2; and third and fourth connection vias CV3 and CV4, which pass through the second intermediate layer 122, the third and fourth connection vias CV3 and CV4 are disposed to be spaced apart from each other, and a second trench TR2 is interposed between the third and fourth connection vias CV3 and CV4. The first through-via 151 may connect the first trench capacitor 140 and the second trench capacitor 160 to each other through the first and third connection vias CV1 and CV3, and the second through-via 152 may connect the first trench capacitor 140 and the second trench capacitor 160 to each other through the second and fourth connection vias CV2 and CV4.

[0040] Specifically, the first electrode 141 and the second electrode 142 may extend to the inside of the first connection via CV1 and the inside of the second connection via CV2, respectively, and the third electrode 161 and the fourth electrode 162 may extend to the inside of the third connection via CV3 and the inside of the fourth connection via CV4, respectively. In this case, the first through-hole 151 may connect the first electrode 141 disposed in the first connection via CV1 and the third electrode 161 disposed in the third connection via CV3 to each other. The second through-hole 152 may connect the second electrode 142 disposed in the second connection via CV2 and the fourth electrode 162 disposed in the fourth connection via CV4 to each other. Although not shown, conductive pads that connect the trench capacitors 140 and 160 and the conductive materials 181 and 182 to each other may be disposed at the upper and lower ends of the through-holes 151 and 152.

[0041] like Figure 2 and Figure 3As shown in FIG. 1 , the first electrode 141 may be disposed on the inner wall of the first connection via hole CV1, and a portion of the inside of the first connection via hole CV1 except a space in which the first electrode 141 is disposed may be filled with the first cover layer 131. The second electrode 142 may be disposed on the inner wall of the second connection via hole CV2, and a portion of the inside of the second connection via hole CV2 except a space in which the second electrode 142 is disposed may be filled with the first cover layer 131.

[0042] In addition, according to the process to be described below, the second connection via CV2 may be formed after the first dielectric layer 143 and the second electrode 142 are formed, so that the height of the second connection via CV2 in the first direction may be greater than the height of the first connection via CV1 in the first direction. That is, one end of the first connection via CV1 may be disposed at a height closer to the first surface 101 than one end of the second connection via CV2. Here, one end of the first connection via CV1 and one end of the second connection via CV2 may refer to ends spaced apart from the first surface 101. From the same perspective, the height of the fourth connection via CV4 in the first direction DR1 may be greater than the height of the third connection via CV3 in the first direction DR1. That is, one end of the third connection via CV3 may be disposed at a height closer to the second surface 102 than one end of the fourth connection via CV4. Here, one end of the third connection via CV3 and one end of the fourth connection via CV4 may refer to ends spaced apart from the second surface 102.

[0043] like Figure 3 As shown in , the first connection via CV1 and the second connection via CV2 may both have a shape extending along the third direction DR3, but the present disclosure is not limited thereto. Figure 4 As shown in , a plurality of first connection vias CV1 and a plurality of second connection vias CV2 may be provided, the plurality of first connection vias CV1 may be provided to be spaced apart from each other in the third direction DR3, and the plurality of second connection vias CV2 may be provided to be spaced apart from each other in the third direction DR3.

[0044] A first external electrode 191 connected to the first electrode 141 and a second external electrode 192 connected to the second electrode 142 may be disposed on the first cover layer 131. The first external electrode 191 may be electrically connected to the first electrode 141 through a first interconnection layer 171 disposed in the first cover layer 131, and the second external electrode 192 may be electrically connected to the second electrode 142 through a second interconnection layer 172 disposed in the first cover layer 131. Materials included in the external electrodes 191 and 192 and the interconnection layers 171 and 172 do not need to be particularly limited, but may suffice as long as they include metal or other suitable conductive materials.

[0045] The number, size, and aspect ratio of the interconnection layers 171 and 172 do not need to be particularly limited. It is sufficient as long as the lower surface of the first external electrode 191 and the lower surface of the second external electrode 192 are arranged to be coplanar with each other. However, according to the process to be described below, the end of the second electrode 142 may be arranged at a height closer to the lower surfaces of the external electrodes 191 and 192 than the end of the first electrode 141, so that the height of the lower surface of the second interconnection layer 172 in the first direction DR1 may be smaller than the height of the lower surface of the first interconnection layer 171 in the first direction DR1 relative to the lower surface of the first external electrode 191 and the lower surface of the second external electrode 192. The interconnection layers 171 and 172 may each have the same configuration as the through vias 151 and 152.

[0046] Figure 5 yes Figure 2 Variant of . Figure 5 , the capacitor assembly 100' according to the example embodiment may include a molding part 190 covering at least a portion of the outer surface of the substrate 110. More preferably, the molding part 190 may cover the outer surface of the substrate 110, the outer surfaces of the intermediate layers 121 and 122, the outer surfaces of the cover layers 131 and 132, and the lower surface of the second cover layer 132. The molding part 190 may be used to protect the substrate 110, the intermediate layers 121 and 122, and the cover layers 131 and 132. The molding part 190 may be formed, for example, by transfer molding a resin such as an epoxy resin.

[0047] Figure 6 is a schematic plan view of a capacitor assembly according to another example embodiment of the present disclosure. Figure 7 It is along Figure 6 Schematic cross-sectional view taken along line III-III'. Figure 8 It is along Figure 6 Schematic cross-sectional view taken along line IV-IV'.

[0048] Reference Figures 6 to 8 , a plurality of first external electrodes 191" and a plurality of second external electrodes 192" may be provided respectively. Figure 7 As shown in , a plurality of first external electrodes 191" may be connected to one first electrode 141. In addition, as Figure 8 As shown in the figure, multiple second external electrodes 192" can be connected to one second electrode 142. In this way, the number of first external electrodes 191" and second external electrodes 192" can be increased to reduce the distance between the first external electrodes 191" in the third direction DR3 and the distance between the second external electrodes 192" in the third direction DR3, thereby reducing the ESL (equivalent series inductance) of the capacitor assembly 100".

[0049] Figures 9 to 15is a cross-sectional view of the main process of the method for manufacturing a capacitor assembly according to an exemplary embodiment of the present disclosure. Figures 9 to 15 An example method of manufacturing the capacitor assembly 100 according to an example embodiment of the present disclosure is described.

[0050] First, refer to Fig. 9 , the substrate 110 may be prepared, and then through holes may be formed using laser drilling, etc. Subsequently, conductive materials 181 and 182 may be deposited in the through holes using a plating method or a sputtering method to form through vias 151 and 152 .

[0051] Then, if Fig.10 As shown in , a first intermediate layer 121 and a second intermediate layer 122 may be formed on the first surface 101 and the second surface 102 of the substrate 110, respectively. The intermediate layers 121 and 122 may be formed by depositing an insulating material, or may be formed as an oxide film of the substrate 110. Thereafter, a portion of the intermediate layers 121 and 122 may be etched using a mask pattern and an etching device to form a first trench TR1 and a second trench TR2 extending along a first direction DR1 toward the substrate 110. In addition, the first connection via CV1 and the third connection via CV3 may be formed by etching portions of the intermediate layers 121 and 122 formed on the first through via 151 until the first conductive material 181 is exposed.

[0052] Then, if Fig.11 As shown in , the first electrode 141 and the third electrode 161 may be formed using an atomic layer deposition (ALD) or atomic vapor deposition (AVD) process. The first electrode 141 may be conformally formed along one surface of the first intermediate layer 121, the inner wall of the first trench TR1, and the inner wall of the first connection via CV1, and the third electrode 161 may be conformally formed along one surface of the second intermediate layer 122, the inner wall of the second trench TR2, and the inner wall of the third connection via CV3.

[0053] Then, if Fig.12 As shown in , an insulating material that is the same as or different from the insulating material of the intermediate layers 121 and 122 may be deposited on the first intermediate layer 121 and the second intermediate layer 122, respectively, to partially form the first capping layer 131 and the second capping layer 132. In this case, the first capping layer 131 and the second capping layer 132, respectively disposed on the first electrode 141 and the third electrode 161, may be later used as a dielectric layer for forming a capacitor. However, the present disclosure is not limited thereto, and a material different from that of the capping layers 131 and 132 may be deposited on the intermediate layers 121 and 122 to form a dielectric layer.

[0054] Then, if Fig.13As shown in FIG. 1 , portions of the capping layers 131 and 132 filled in the first trench TR1 and the second trench TR2 and portions of the capping layers 131 and 132 deposited on the second through via 152 may be etched. In this case, portions of the capping layers 131 and 132 deposited on the second through via 152 may be etched until the second conductive material 182 is exposed to form the second and fourth connection vias CV2 and CV4.

[0055] Then, if Fig.14 As shown in , the second electrode 142 and the fourth electrode 162 may be formed using an atomic layer deposition (ALD) or atomic vapor deposition (AVD) process. In this case, the first capping layer disposed between the first electrode 141 and the second electrode 142 may be used as the first dielectric layer 143, and the second capping layer disposed between the third electrode 161 and the fourth electrode 162 may be used as the second dielectric layer 163. Therefore, the first dielectric layer 143 and the first capping layer 131 may be formed integrally, and the second dielectric layer 163 and the second capping layer 132 may be formed integrally, but the present disclosure is not limited thereto.

[0056] Then, if Fig.15 As shown in FIG. 1 , as previously designed, the capping layers 131 and 132 may be formed by further depositing insulating materials. Figure 2 As shown in FIG. 1 , a portion of the capping layers 131 and 132 may be etched to form a first interconnection layer 171 connected to the first electrode 141 and a second interconnection layer 172 connected to the second electrode 142, and a first external electrode 191 and a second external electrode 192 may be formed on the first interconnection layer 171 and the second interconnection layer 172, respectively, to manufacture Figure 2 A capacitor assembly 100 is provided.

[0057] However, the present disclosure is not limited thereto. A first intermediate layer 121, a first trench capacitor 140, and a first cover layer 131 may be formed on the first surface 101 of the substrate 110. Then, the substrate 110 may be flipped to form a second intermediate layer 122, a second trench capacitor 160, and a second cover layer 132 on the substrate 110. Specific processes and their order may vary depending on the arrangement type of each component.

[0058] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

[0059] In addition, the term "exemplary embodiment" used herein does not refer to the same exemplary embodiment, but is provided to emphasize a specific feature or characteristic that is different from a specific feature or characteristic of another exemplary embodiment. However, the exemplary embodiments provided herein are considered to be able to be implemented by combining with each other in whole or in part. For example, unless a contrary or contradictory description is provided therein, an element described in a specific exemplary embodiment may be understood as a description related to another exemplary embodiment even if it is not described in another exemplary embodiment.

[0060] As used herein, the term "connection" may refer not only to "direct connection" but also to "indirect connection" by means of an adhesive layer or the like. The term "electrical connection" may include both a case where components are "physically connected" and a case where components are "not physically connected". In addition, the terms "first", "second", etc. may be used to distinguish one component from another, and may not limit the order and / or importance associated with the components, etc. In some cases, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the example embodiments.

Claims

1. A capacitor assembly, comprising: a substrate having a first surface and a second surface opposite to each other; A first intermediate layer, disposed on the first surface of the substrate, wherein the first intermediate layer comprises a first groove; a first trench capacitor disposed in the first trench; A second intermediate layer is disposed on the second surface of the substrate, wherein the second intermediate layer comprises a second groove; a second trench capacitor disposed in the second trench; as well as A through via passes through the substrate to connect the first trench capacitor and the second trench capacitor to each other.

2. The capacitor assembly according to claim 1, wherein: The first trench capacitor includes a first dielectric layer and a first electrode and a second electrode, and the first dielectric layer is interposed between the first electrode and the second electrode, and The second trench capacitor includes a second dielectric layer and third and fourth electrodes, and the second dielectric layer is interposed between the third and fourth electrodes.

3. The capacitor assembly according to claim 2, wherein: The through hole comprises: a first through hole connecting the first electrode and the third electrode to each other; and The second through via connects the second electrode and the fourth electrode to each other.

4. The capacitor assembly according to claim 2, wherein: The first dielectric layer and the second dielectric layer are spaced apart from the through via.

5. The capacitor assembly according to claim 1, wherein: The through via is filled with a conductive material.

6. The capacitor assembly according to claim 3, further comprising: A first connection via and a second connection via, passing through the first intermediate layer, the first connection via and the second connection via are arranged to be spaced apart from each other, and the first groove is between the first connection via and the second connection via; as well as The third connection via and the fourth connection via pass through the second intermediate layer, the third connection via and the fourth connection via are arranged to be spaced apart from each other, and the second groove is interposed between the third connection via and the fourth connection via.

7. The capacitor assembly according to claim 6, wherein: The first electrode and the second electrode extend to the inside of the first connection via hole and the inside of the second connection via hole respectively, The third electrode and the fourth electrode extend to the inside of the third connection via hole and the inside of the fourth connection via hole, respectively. The first through via connects the first electrode disposed in the first connection via and the third electrode disposed in the third connection via to each other, and The second through via connects the second electrode provided in the second connection via and the fourth electrode provided in the fourth connection via to each other.

8. The capacitor assembly of claim 1, further comprising: A first cover layer covers the first trench capacitor and a second cover layer covers the second trench capacitor.

9. The capacitor assembly according to claim 8, wherein: The first intermediate layer and the first cover layer include different materials, and The second intermediate layer and the second cover layer include different materials.

10. The capacitor assembly according to claim 1, wherein: The first surface and the second surface are opposite to each other in a first direction, The first intermediate layer includes a plurality of first grooves, The plurality of first grooves are arranged to be spaced apart from each other in a second direction perpendicular to the first direction, and Each of the plurality of first trenches extends along a third direction perpendicular to the first direction and the second direction.

11. The capacitor assembly of claim 1, wherein: The first surface and the second surface are opposite to each other in a first direction, The first intermediate layer includes a plurality of first grooves, and The plurality of first grooves are disposed to be spaced apart from each other in a second direction perpendicular to the first direction, and are disposed to be spaced apart from each other in a third direction perpendicular to the first direction and the second direction.

12. The capacitor assembly of claim 2, further comprising: a first covering layer, covering the first trench capacitor; as well as A first external electrode and a second external electrode are disposed on the first cover layer, and the first external electrode and the second external electrode are connected to the first electrode and the second electrode, respectively.

13. The capacitor assembly of claim 12, wherein: The first external electrode and the second external electrode include a plurality of external electrodes, respectively.

14. The capacitor assembly of claim 12, wherein: The first capping layer and the first dielectric layer include the same material.

15. The capacitor assembly of claim 14, wherein: The dielectric constant of the same material of the first capping layer and the first dielectric layer is higher than the dielectric constant of the first intermediate layer.

16. The capacitor assembly of claim 1, further comprising: The molding portion covers at least a portion of the outer surface of the substrate.

17. The capacitor assembly of claim 1, wherein: The through via is filled with conductive material.

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