Nano vacuum channel transistor and preparation method thereof

Abstract

The invention provides a nano vacuum channel transistor and a preparation method thereof, in the nano vacuum channel transistor, an emitter is provided with a tip arranged opposite to a collector, and a nano gap is defined between the emitter and the collector, so that a nano channel can be realized, the influence of the vacuum degree on a field emission transistor is reduced, and the yield of the field emission transistor is improved. And the gate electrode is arranged on at least one of the upper part, the lower part and the two sides of the emitter and the collector, so that the device is endowed with the required gate control capability, and the high-speed on-off of the device under a relatively low working voltage is realized. According to the preparation method, after the step of forming the emitter by adopting a mature photoetching technology, the sacrificial side wall structure is formed on the side wall of the emitter, and the nano gap between the emitter and the collector is limited by utilizing the sacrificial side wall structure, so that the nano-scale processing precision of the vacuum channel is ensured, and the preparation method can be highly compatible with a CMOS (Complementary Metal Oxide Semiconductor) process; and the manufacturing cost of the device is greatly reduced, and the process consistency is high.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for preparing the same, and in particular to a vacuum transistor and a method for preparing the same. Background Art

[0002] With the rapid development of the integrated circuit industry, integrated circuit manufacturing technology has entered the 5nm technology node, and the continuous miniaturization of the characteristic size of semiconductor devices has approached the physical limit of size. Limited by the fact that the carrier mobility in silicon-based solid-state devices is essentially affected by lattice scattering or impurities, silicon-based devices can no longer meet the growing demand for high frequency or fast response. Compared with the situation in solid-state devices, the electron movement rate under vacuum conditions is theoretically 3×10 10 cm / s, which is about 3 orders of magnitude faster than its movement speed in semiconductors, and is not affected by collisions or scattering. In addition, in extreme environments (high temperature, high radiation, etc.), the performance of nano vacuum channel transistors (NVCTs) based on the field emission principle is more stable, and therefore has received widespread attention.

[0003] The emission voltage of electrons is closely related to the size of the vacuum channel. As the operating voltage continues to decrease, if it is desired to achieve high-speed switching of the device under low voltage and non-vacuum conditions, the size of the vacuum channel needs to be at the nanometer level. Simply relying on existing photolithography technology is difficult to ensure the control accuracy of the nanometer size, so it is not easy to prepare highly integrated NVCT chips.

[0004] Therefore, it is necessary to provide a new type of nano vacuum channel transistor and a preparation method thereof.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a nano vacuum channel transistor and a preparation method thereof, which are used to solve the problems that the processing accuracy and stability of the nano gap in the existing process of vacuum channel transistors are difficult to meet application requirements and are incompatible with CMOS processes.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a nano vacuum channel transistor, comprising the following steps:

[0008] Providing an SOI substrate, the SOI substrate comprising a back substrate, an insulating layer and a top functional layer, and performing a first patterning on the top functional layer to form a first electrode portion;

[0009] forming a first sacrificial spacer structure on a sidewall of the first electrode portion;

[0010] A first electrode material layer is formed covering the first electrode portion and the first sacrificial sidewall structure, the first electrode material layer is patterned to form a first gate electrode portion, and the top functional layer is patterned for a second time, and an emitter with a tip is formed based on the first electrode portion, wherein the first gate electrode portion has an end portion adjacent to the tip of the emitter;

[0011] Forming a second sacrificial spacer structure on the sidewall with a pointed tip of the emitter and the sidewall of the first gate electrode portion to intersect with the first sacrificial spacer structure;

[0012] A collector is formed from the intersection of the first sacrificial spacer structure and the second sacrificial spacer structure in a direction away from the emitter, the collector is formed adjacent to the first sacrificial spacer structure and the second sacrificial spacer structure at a diagonal position of the emitter tip, and a second gate electrode portion is formed adjacent to an end of the emitter tip and opposite to the first gate electrode portion;

[0013] The first sacrificial spacer structure and the second sacrificial spacer structure are removed to release the nanogap between the emitter and the collector.

[0014] Optionally, after the step of forming the first electrode material layer, the emitter and the first gate electrode portion are synchronously formed by the following steps: the first electrode material layer is planarized so that the top surface of the obtained first electrode material layer is flush with the top surface of the first electrode portion; the first electrode portion and the first electrode material layer are anisotropically etched based on a patterned mask layer, and the patterned mask layer is formed on the first electrode portion and the first electrode material layer in a manner such that a side wall is chamfered on the two, so that the etched end surfaces of the emitter and the first gate electrode portion are coplanar.

[0015] Optionally, the step of forming the second sacrificial sidewall structure includes: forming a second sacrificial dielectric material layer covering the exposed surface of the insulating layer; performing an anisotropic etching process on the second sacrificial dielectric material layer to form a second sacrificial sidewall structure on the etched end surfaces of the emitter and the first gate electrode portion, the second sacrificial sidewall structure intersecting with the first sacrificial sidewall structure.

[0016] Optionally, after the step of forming the second sacrificial sidewall structure, the step includes: forming a third electrode material layer covering the insulating layer; flattening the third electrode material layer to form a collector at a diagonal position of the emitter tip, and forming a second gate electrode portion opposite to the first gate electrode portion.

[0017] Optionally, after the step of forming the collector, a gate electrode is formed by performing the following steps, including: removing the first gate electrode portion and the second gate electrode portion; forming a third electrode material layer covering the insulating layer; and flattening the third electrode material layer so that the top surface of the third electrode material layer is flush with the top surfaces of the emitter and the collector, thereby forming gate electrodes on both sides of the emitter and the collector.

[0018] Optionally, before the step of forming the gate electrode, the step includes: forming a gate dielectric material layer covering the emitter and the collector; performing an anisotropic etching process on the gate dielectric material layer, and forming the gate dielectric material layer retained on the side walls of the first sacrificial sidewall structure and the second sacrificial sidewall structure into a gate dielectric layer.

[0019] The present invention also provides a method for preparing a nano vacuum channel transistor, comprising the following steps:

[0020] Providing a substrate layer, forming a first insulating layer, a polycrystalline semiconductor layer, a second insulating layer and a top functional layer on the substrate layer, and patterning the top functional layer to form an emitter with a pointed tip;

[0021] forming a sacrificial sidewall structure on the sidewall of the emitter;

[0022] A collector is formed by using the sacrificial sidewall structure as a spacer and being spaced apart from the emitter, wherein the collector has an end portion adjacent to the tip of the emitter;

[0023] Forming a gate structure, comprising the following steps: forming a gate dielectric layer based on the second insulating layer; forming a gate electrode based on the polycrystalline semiconductor layer; wherein the emitter and the collector are formed on a first main surface of the second insulating layer, and the polycrystalline semiconductor layer is formed on a second main surface of the second insulating layer opposite to the first main surface;

[0024] The sacrificial sidewall structure is removed to release the nano-gap between the collector and the emitter.

[0025] Optionally, the step of forming the sacrificial sidewall structure includes: forming a sacrificial dielectric material layer covering the patterned top functional layer; removing a portion of the sacrificial dielectric material layer by an anisotropic etching process, and retaining the sacrificial dielectric material layer covering the emitter sidewall to form the sacrificial sidewall structure.

[0026] Optionally, the step of forming the collector includes: forming an electrode material layer covering the emitter and the sacrificial sidewall structure; and flattening the electrode material layer so that the top surface of the obtained electrode material layer is flush with the top surfaces of the emitter and the sacrificial sidewall structure.

[0027] Optionally, a cross section of the sacrificial spacer structure perpendicular to its extension direction is formed into a rectangle, a parallelogram or an inverted trapezoid.

[0028] Optionally, it also includes: forming metal contacts between the emitter and the collector and metal electrodes for realizing electrical extraction.

[0029] On the other hand, the present invention also provides a nano vacuum channel transistor, comprising:

[0030] substrate layer;

[0031] an insulating layer, located on the substrate layer, the insulating layer having a first main surface and a second main surface opposite to each other, an emitter and a collector spaced apart from each other and opposite to each other are arranged on the first main surface of the insulating layer, an end of the emitter opposite to the collector is arranged to be a pointed tip, and a nano-gap is defined between the tip of the emitter and the end of the collector to provide a channel region for the emitter to emit electrons to the collector;

[0032] A gate electrode is disposed on the first main surface or the second main surface of the insulating layer and is located at a side adjacent to the nanogap.

[0033] Optionally, the sidewall of the collector extending toward the emitter is configured to have a concave profile substantially complementary to the emitter tip to define a nanogap between opposite sidewalls of the emitter and the collector, wherein a size of the nanogap ranges from 0.1 nm to 50 nm.

[0034] Optionally, the ends of the emitter and the collector extending toward each other are respectively configured to form sharp-angled tip structures, and a nanogap is defined between the opposite tips of the emitter and the collector, wherein a size of the nanogap ranges from 0.1 nm to 50 nm.

[0035] Optionally, the gate electrode is located on both sides of the emitter and the collector and is spaced apart from the emitter and the collector respectively.

[0036] Optionally, it also includes: a gate dielectric layer, which is arranged on the bottom surface and side walls of the gate electrode to reduce the leakage current of the gate electrode, and the cross-section of the nanogap between the emitter and the collector perpendicular to its extension direction is rectangular, parallelogram or inverted trapezoidal.

[0037] As described above, the nano vacuum channel transistor and the method for preparing the same according to the present invention have the following beneficial effects:

[0038] In the nano vacuum channel transistor of the present invention, the emitter has a tip arranged opposite to the collector, and a nano gap is defined between the emitter and the collector, so that a nano-scale channel can be realized, so that the influence of the vacuum degree on the field emission transistor is reduced. The gate electrode is arranged at least one of the top, bottom and both sides of the emitter and the collector, giving the device the required gate control capability, thereby realizing high-speed switching of the device at a lower operating voltage.

[0039] In the preparation method of the nano vacuum channel transistor of the present invention, a mature photolithography technology is used to form an emitter with a pointed end, replacing the conventional electron beam lithography or focused ion beam etching technology. After the step of forming the emitter and / or the collector, a sacrificial sidewall structure is formed on the sidewall of the sacrificial sidewall structure. The sacrificial sidewall structure is used to define the nano gap between the emitter and the collector, thereby ensuring the nanoscale processing accuracy of the vacuum channel. It is highly compatible with the CMOS process, greatly reducing the manufacturing cost of the device, and has the advantages of high process consistency, further releasing the application potential of the nano channel transistor, and is conducive to the realization of a highly integrated NVCT chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 Shown is a process flow chart of a method for preparing a nano vacuum channel transistor in Embodiment 1 of the present invention.

[0041] 2 to 9 are schematic diagrams showing structures obtained in various steps during the preparation of a nano vacuum channel transistor in Embodiment 1 of the present invention; wherein: Figures 2b to 9b Shown as Figures 2a to 9a The structure shown is a cutaway view along section AA'. Figure 2c Display as Figure 2a Isometric view of the structure shown.

[0042] Figures 10 to 14 It is a schematic diagram showing the structure obtained during the vacuum packaging process of the nano vacuum channel transistor in the first embodiment of the present invention.

[0043] Figure 15 to Fig.17 It is a schematic diagram showing the definition of nanogaps of different cross-sectional shapes during the preparation process of the nano vacuum channel transistor in the first embodiment of the present invention; wherein, Fig.15b for Fig.15a The structure shown is a cross-sectional view along section AA'.

[0044] Fig.18 It shows a process flow chart of a method for preparing a nano vacuum channel transistor in the second embodiment of the present invention.

[0045] 19 to 29 are schematic diagrams showing structures obtained in various steps during the preparation of the nano vacuum channel transistor according to the second embodiment of the present invention; wherein, Figures 19b to 24b Shown as Figures 19a to 24a A cutaway view of the structure shown along section SS';

[0046] Fig.19c and Fig.24c They are Fig.19a and Fig.24a Isometric view of the structure shown; Figure 25b to Figure 29b They are Figures 25a to 29a A cutaway view of the structure shown along section AA'; Figure 25c to Figure 29c They are Figures 19a to 24a A cutaway view of the structure shown along section BB'; Figure 25d to Figure 29d They are Figures 25a to 29a A cutaway view of the structure shown along section CC'; Figure 25e to Figure 29e They are Figures 25a to 29a A cutaway view of the structure shown along section DD'; Fig.25f , Figure 28f and Fig.29f They are 25a, Fig.28a and Fig.29a Isometric view of the structure shown.

[0047] 30 to 35 are schematic diagrams showing the structures of the various stages of forming a gate electrode using the first gate electrode portion and the second gate electrode portion as dummy gates during the preparation process of the nano vacuum channel transistor according to the second embodiment of the present invention; wherein, Figure 30b to Figure 35b They are Figures 30a to 35a A cutaway view of the structure shown along section AA'; Figure 30c to Figure 35c They are Figures 30a to 35a A cutaway view of the structure shown along section BB'; Figures 30d to 35d They are Figures 30a to 35a A cutaway view of the structure shown along section CC'; Figure 30e to Figure 35e They are Figures 30a to 35a A cutaway view of the structure shown along section DD'; Figure 35f for Fig.35a A cutaway view of the structure shown along section EE'; Fig.30f , Figure 34f and Figure 35g They are 30a, Fig.34a and Fig.35a Isometric view of the structure shown.

[0048] 36 to 38 are schematic diagrams showing the definition of nanogaps of different cross-sectional shapes during vacuum packaging of the nano vacuum channel transistor in the second embodiment of the present invention; wherein, Figure 36b to Figure 38b They are Figures 36a to 38a A cutaway view of the structure shown along section AA'; Figures 36c to 38c They are Figures 36a to 38aA cutaway view of the structure shown along section BB'; Figure 36d to Figure 38d They are Figures 36a to 38a A cutaway view of the structure shown along section CC'; Figure 36e to Figure 38e They are Figures 36a to 38a A cutaway view of the structure shown along section DD'; Figure 36f to Figure 38f They are Figures 36a to 38a The structure shown is a cross-sectional view along section EE'.

[0049] 39 to 42 are cross-sectional views of a nano vacuum channel transistor in the third embodiment of the present invention; wherein, Fig.39b for Fig.39a A cutaway view of the structure shown along section AA'; Fig.40 and a schematic diagram of partially retaining a sacrificial dielectric material layer in a nano vacuum channel transistor as shown in FIG42 ; Figure 42b to Figure 42f for Fig.42a The structure shown is a cross-sectional view along sections AA', BB', CC', DD' and EE'.

[0050] Component number description

[0051] 110 substrate layer

[0052] 120 First insulation layer

[0053] 130 Polycrystalline semiconductor layer

[0054] 140 Second insulation layer

[0055] 150 Top functional layer

[0056] 152 electrode material layer

[0057] 2520 First electrode material layer

[0058] 2530 Second electrode material layer

[0059] 2540 first sacrificial dielectric material layer

[0060] 2541 First Sacrificial Side Wall Structure

[0061] 2542 second sacrificial dielectric material layer

[0062] 2545 Second sacrificial side wall structure

[0063] 310 Back gate electrode

[0064] 510 emitter

[0065] 520 Collector

[0066] 1540 Sacrificial dielectric material layer

[0067] 1541 Sacrificial side wall structure

[0068] 550 nm gap

[0069] 560 Gate electrode

[0070] 561a, 561b gate dielectric layer

[0071] 5610 Gate dielectric material layer

[0072] 2510 First electrode part

[0073] 2560 First gate electrode part

[0074] 2562 Second gate electrode portion

[0075] 610 Metal Connection

[0076] 620 Passivation layer

[0077] 650 Top passivation layer

[0078] Steps S11~S15, S21~S26 DETAILED DESCRIPTION

[0079] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0080] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "above", "below", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0081] Compared with conventional solid-state transistors whose carrier migration is restricted by drift-diffusion mechanism, the channel contained in the vacuum transistor of the present invention is in a vacuum state, and the potential barrier on the surface of the vacuum emitter can be greatly reduced by increasing the temperature, electric field, light, etc. In the case of an external strong electric field, the height and width of the potential barrier on the emitter surface are reduced, making it possible for electrons to jump into the vacuum.

[0082] In the preparation process of planar nano vacuum channel transistors (NVCTs), electron beam lithography or focused ion beam etching is typically used to form a micro-needle structure emitter and / or collector. The preparation method of the nano vacuum channel transistor provided by the present invention can use mature lithography technology such as ultraviolet lithography to form an emitter with a tip based on the top functional layer of the SOI substrate, and a collector with an end opposite to the tip of the emitter, so that a nano gap is defined between the emitter and the collector, ensuring the nano-level processing accuracy of the vacuum channel, and being highly compatible with the CMOS process, thereby realizing high-speed switching of the field emission transistor at low voltage, and even high-speed switching under non-vacuum conditions.

[0083] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0084] Embodiment 1

[0085] First, see Figure 1 , perform step S11, provide a substrate layer, on which a first insulating layer, a polycrystalline semiconductor layer, a second insulating layer and a top functional layer are formed, and pattern the top functional layer to form an emitter with a pointed tip.

[0086] Figure 2a It is a schematic diagram showing the structure after forming a top functional layer on the substrate layer. Figure 2b for Figure 2aThe structure shown is a cross-sectional view along the AA' section. In step S11, a first insulating layer 120, a polycrystalline semiconductor layer 130, a second insulating layer 140 and a top functional layer 150 are sequentially formed on the substrate layer 110, wherein the material of the polycrystalline semiconductor layer includes, but is not limited to, for example, silicon, germanium, silicon carbide, and gallium nitride; the top functional layer 150 can be made of conventional semiconductor materials in the art, including but not limited to semiconductor materials of the IV main group, such as Si, Ge, and SiC; or, III-V compound semiconductor materials, such as GaN; the second insulating layer can be made of suitable gate dielectric materials, including insulating materials, such as silicon dioxide, zirconium dioxide, hafnium dioxide, aluminum oxide, hafnium aluminum oxide, and lanthanum aluminum oxide; or, wide bandgap semiconductor materials; in some cases, the second insulating layer includes a cavity located therein or at the interface. The composition of the material layer to be formed and its formation process can be determined according to the required device performance, including but not limited to: chemical vapor deposition process, plasma enhanced chemical vapor deposition process, atomic layer deposition process or similar process. In this embodiment, the second insulating layer 140 has a thickness smaller than that of the first insulating layer 120 .

[0087] See also Figure 3a to Figure 3b , Figure 3a Shown is a top view of the structure obtained after patterning the top functional layer. Figure 3b for Figure 3a The structure shown is a cross-sectional view along the AA' section. At step S11, the step of patterning the top functional layer 150 includes: etching the top functional layer 150 based on the patterned mask layer until the surface of the second insulating layer 140 is exposed, forming a patterned area that penetrates the top functional layer 150, and the resulting patterned area is formed as an emitter 510, and the emitter 510 is formed with a tip.

[0088] The patterned mask layer may include a photoresist pattern formed based on lithography technology. In this embodiment, the patterned mask layer includes a photoresist pattern formed by a photolithography process. The standard photolithography process may include processing steps such as photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, development, and hard baking. Under the premise of ensuring the required emission performance, the morphology of the emitter is adjusted by adjusting the shape and / or size of the pattern defined by the photolithography. Figure 3a As shown, the resulting patterned region is formed into a sharp tip with an acute top angle, which can improve the field enhancement factor.

[0089] Next, step S12 is performed to form a sacrificial spacer structure on the sidewall of the emitter.

[0090] Specifically, see Figure 4a to Figure 4bThe step of forming a sacrificial sidewall structure 1541 includes: forming a sacrificial dielectric material layer 1540 covering the patterned area, wherein the sacrificial dielectric material layer 1540 can be conformally deposited on the second insulating layer 140, and the sacrificial dielectric material layer can have a nanometer-level thickness. The sacrificial dielectric material layer can be deposited by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a similar process, wherein the sacrificial dielectric material includes but is not limited to: SiO x 、SiN x 、SiN x O y and one of Al2O3.

[0091] Further, see Figure 5a to Figure 5b In step S12, the sacrificial dielectric material layer is anisotropically etched to remove the sacrificial dielectric material layer 1540 covering the emitter and the top surface of the second insulating layer, and the sacrificial dielectric material layer covering the side wall of the emitter is retained to form a sacrificial sidewall structure 1541. Since the sacrificial dielectric material layer may have a nanometer-level thickness, the sacrificial dielectric material layer is anisotropically etched, that is, the longitudinal etching rate is greater than the lateral etching rate, so the sacrificial sidewall structure obtained by etching may also have a nanometer-level thickness, for example, a thickness between 0.1nm-50nm.

[0092] In some examples, the cross section of the sacrificial sidewall structure 1541 perpendicular to its extension direction is formed into a rectangle, a parallelogram or an inverted trapezoid. Ideally, based on the patterned mask layer, the top functional layer is anisotropically etched to form an emitter with a vertical sidewall; in actual processes, the anisotropic etching process can be a non-ideal anisotropic etching process, such as an inductively coupled plasma (ICP) etching process or a reactive ion etching (RIE) process, so that the emitter has an inclined sidewall, and the resulting sacrificial sidewall structure 1541 is formed into a cross section having at least one oblique side perpendicular to its extension direction.

[0093] Next, step S13 is performed to form a collector separated from the emitter by using the sacrificial spacer structure as a spacer, wherein the collector is formed adjacent to the tip of the emitter.

[0094] Specifically, step S13 includes: covering the emitter and the sacrificial sidewall structure to form an electrode material layer; flattening the electrode material layer, so that the top surface of the obtained electrode material layer is flush with the top surfaces of the emitter and the sacrificial sidewall structure; patterning the electrode material layer to form a collector in a manner in which the sacrificial sidewall structure is spaced from the emitter, and the tip of the emitter is separated from the collector by the sacrificial sidewall structure.

[0095] See also Figure 6a to Figure 6b , is a schematic diagram of the structure obtained after the electrode material layer is formed in step S13. Figure 6a As shown, the electrode material can be conformally deposited on the substrate 110 to cover the emitter 510 and the sacrificial spacer structure 1541 to form an electrode material layer 152 . The deposited electrode material layer 152 has good step coverage.

[0096] The electrode material layer 152 may be made of the same or different material as the top functional layer, and the material of the electrode material layer includes, but is not limited to, one of polysilicon, Pt, Ru, Ir, Mo, Ti, Al, W, Co, Cr, Au, Cu, and Ag. As an example, the electrode material layer 152 may be deposited by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a similar process.

[0097] In some examples, the surface of the electrode material layer is planarized, wherein the method of planarizing the electrode material layer includes, for example, a chemical mechanical polishing (CMP) process or a similar process. Figure 7a to Figure 7b , Figure 7a It is a top view of the structure obtained after the electrode material layer is planarized in step S13. Figure 7b for Figure 7a The structure shown is a cutaway view along section AA'. Figure 7b As shown, the emitter, the sacrificial spacer structure and the top surface of the electrode material layer are made flush.

[0098] When the obtained emitter 510 is formed into an inclined side wall, a sacrificial sidewall structure 1541 is formed on the side wall of the emitter; the cross section of the sacrificial sidewall structure 1541 perpendicular to its extension direction is formed into a parallelogram, which can prevent the passivation layer from entering the gap during the vacuum packaging of the nano vacuum channel transistor; or, the sacrificial sidewall structure 1541 is formed into an inverted trapezoid in the cross section perpendicular to its extension direction in the following manner, including but not limited to, when performing the deposition step of the sacrificial dielectric material layer, the substrate layer formed with the emitter is tilted at a preset angle, so that in the subsequent process of removing the sacrificial sidewall structure, the etchant or corrosive liquid can more easily enter the gap, thereby improving the production yield of the device.

[0099] In applications with vacuum requirements, the device can be vacuum packaged to ensure the surface cleanliness of the emitter and the stability of the device. Figures 10 to 13 , for vacuum packaging the nano vacuum channel transistor manufactured according to this embodiment. Figures 10 to 13 As shown, in Figure 6a to Figure 6bAfter the step of forming the electrode material layer as shown, the electrode material layer 152 is patterned, and the electrode material layer 152 covering the sacrificial sidewall structure may have a top surface higher than the collector; a passivation layer 620 is formed covering the emitter 510 and the patterned electrode material layer, as shown in FIG. Fig.12 As shown, the top surface of the passivation layer is higher than the top surface of the patterned electrode material layer; then, as Fig.13 As shown, the passivation layer 620 is planarized, wherein the method of planarizing the passivation layer 620 includes, for example, a CMP process or a similar process, so that the top surface of the resulting collector is flush with the top surface of the emitter, and the sacrificial sidewall structure 1541 is exposed, so as to facilitate the removal of the sacrificial sidewall structure in the subsequent process.

[0100] Next, step S14 is performed to remove the sacrificial sidewall structure to release the nano-gap between the collector and the emitter.

[0101] See also Figure 8a to Figure 8b , Figure 8a The top view of the structure obtained after the nanogap is released in step S14 is shown. Figure 8b for Figure 8a The structure shown is a cross-sectional view along the AA' section. Ideally, the sacrificial spacer structure 1541 is formed into a rectangular cross section along the orthogonal plane of its extension direction, that is, the ends of the emitter and the collector are arranged at approximately equal intervals.

[0102] For other examples, see Figure 16 to Figure 17 , is a schematic diagram of forming nanogaps with different cross-sectional shapes during the manufacturing process of the nano vacuum channel transistor according to the present embodiment. The cross-section of the sacrificial spacer structure 1541 perpendicular to its extension direction is formed into a parallelogram or an inverted trapezoid. After removing the sacrificial spacer structure 1541, the released nanogap 550 has a shape basically consistent with it.

[0103] Next, step S15 is performed to form a gate structure, including the following steps: forming a gate dielectric layer based on the second insulating layer; forming a gate electrode based on the polycrystalline semiconductor layer; wherein the emitter and the collector are formed on the first main surface of the second insulating layer, and the polycrystalline semiconductor layer is formed on the second main surface of the second insulating layer opposite to the first main surface.

[0104] Specifically, the step of forming the gate structure may be performed after the step of releasing the nano gap 550 , or before the step of forming the top functional layer 150 .

[0105] like Figure 8a to Figure 8bAs shown, a first insulating layer 120, a polycrystalline semiconductor layer 130, a second insulating layer 140 and a top functional layer 150 are sequentially formed on a substrate layer 110, wherein the polycrystalline semiconductor layer 130 is used as a back gate electrode, and the second insulating layer 140 is located between the gate electrode and the emitter and collector and is used as a back gate dielectric layer.

[0106] exist Figure 8a to Figure 8b In the implementation shown, before the step of forming the top functional layer, a back gate structure is formed, and the back gate structure includes a back gate electrode and a back gate dielectric layer.

[0107] In another implementation, after the step of releasing the nanogap 550, a top gate structure is formed on the emitter 510 and the collector 520; wherein the step of forming the top gate structure includes: forming a second insulating layer 140 and a polycrystalline semiconductor layer 130 on the emitter 510 and the collector 520, and forming a gate dielectric layer based on the second insulating layer 140; forming a top gate electrode based on the polycrystalline semiconductor layer 130, the top gate electrode is located on the first main surface of the second insulating layer, and the top functional layer is located on the second main surface of the second insulating layer.

[0108] In a specific example, the step of forming the top gate structure includes: providing a supporting substrate, on which a polycrystalline semiconductor layer 130 and a second insulating layer 140 are sequentially formed, and transferring the polycrystalline semiconductor layer 130 and the second insulating layer 140 onto the substrate by bonding the second insulating layer 140 to the top surfaces of the emitter and the collector, wherein the polycrystalline semiconductor layer 130 can be used as a top gate electrode, and the second insulating layer 140 can be used as a gate dielectric layer.

[0109] Optionally, after step S15, the obtained nano vacuum channel transistor is packaged.

[0110] In the application scenario of low vacuum or air environment, after the step of releasing the nano gap 550 in step S15, as shown in FIG. Figure 9a to Figure 9b As shown, a metal lead 610 may be formed at the gate electrode, the emitter 510 and the collector 520 , and the metal lead 610 forms metal contacts with the gate electrode, the emitter 510 and the collector respectively.

[0111] In the application scenario with vacuum requirements, vacuum packaging can be used. After the step of releasing the nano gap 550, the resulting structure is as follows: Fig.15a and Fig.15bAs shown, a top passivation layer 650 may be formed on the emitter 510 and the collector 520 ; subsequently, openings are formed above the gate electrode, the emitter and the collector to form metal contacts and metal wiring.

[0112] As an example, the top passivation layer 650 is formed by processes including but not limited to chemical vapor deposition (CVD) or thin film bonding.

[0113] The metal connection is formed by common technical means in the art, including but not limited to etching and metal stripping.

[0114] Fig.15b , Figure 16 to Figure 17 The schematic diagrams of several structures of nano vacuum channel transistors using vacuum packaging are shown. In an ideal state, the cross section of the sacrificial sidewall structure 1541 perpendicular to its extension direction is formed into a rectangular shape, and the resulting nano gap 550 can be seen in FIG. Fig.15b , that is, the ends of the emitter and the collector are arranged at substantially equal intervals. In some cases, the cross section of the sacrificial sidewall structure 1541 perpendicular to its extension direction is formed into a parallelogram or an inverted trapezoid, and the resulting nanogap 550 can be seen in Fig.16 and Fig.17 shown.

[0115] It should be noted that the above sequence does not strictly represent the execution sequence of the method for preparing the nano vacuum channel transistor protected by the present invention, and those skilled in the art may change the sequence of steps according to the actual process.

[0116] Embodiment 2

[0117] This embodiment provides a method for preparing a nano vacuum channel transistor. Fig.18 , after which the preparation method of the nano vacuum channel transistor in this embodiment is described in detail.

[0118] First, step S21 is performed to provide an SOI substrate, wherein the SOI substrate includes a back substrate, an insulating layer and a top functional layer, and the top functional layer is patterned for the first time to form a first electrode portion.

[0119] See also Figures 19a to 19c , Fig.19a A top view of the SOI substrate used in step S21 is shown. Fig.19c An isometric view of the SOI substrate used in step S21 is shown. Fig.19b for Fig.19a The structure shown is a cutaway view along the SS' section. Fig.19bAs shown, the SOI substrate includes a back substrate 210, an insulating layer 220 and a top functional layer 250. Different from the formation of the emitter 510 by once patterning the top functional layer in step S11, the patterned region of the top functional layer obtained in step S21 is formed as a first electrode portion 2510, which covers the formation region of the emitter. The obtained structure is as shown in FIG. Figure 20a to Figure 20b shown.

[0120] As an example, the patterned region of the top functional layer, i.e., the first electrode portion 2510, may be formed to have vertical sidewalls; or, the first electrode portion 2510 may have inclined sidewalls, i.e., an overall trapezoidal cross-section. Similarly, ideally, based on the patterned mask layer, the top functional layer is anisotropically etched to form a first electrode portion with vertical sidewalls; in actual processes, the anisotropic etching process may be a non-ideal anisotropic etching process, such as an inductively coupled plasma (ICP) etching process, a reactive ion etching (RIE) process, so that the first electrode portion has inclined sidewalls, such as Figure 37f and Figure 38f shown.

[0121] Next, step S22 is performed to form a first sacrificial spacer structure on the sidewall of the first electrode portion.

[0122] Specifically, the step of forming the first sacrificial spacer structure 2541 includes: forming a first sacrificial dielectric material layer 2540 on the insulating layer 220; performing an anisotropic etching process on the first sacrificial dielectric material layer 2540 to form the first sacrificial spacer structure 2541 on the sidewall of the first electrode portion. Figures 21a to 22a , are top views of the structure obtained after forming the first sacrificial dielectric material layer and the first sacrificial sidewall structure in step S22 , respectively.

[0123] Figure 21b for Fig.21a The structure shown is a cross-sectional view along the SS' section, and the first sacrificial dielectric material layer 2540 is formed covering the first electrode portion and the exposed surface of the insulating layer. In this embodiment, the first sacrificial dielectric material layer 2540 can be formed by a formation process similar to that described in the previous embodiment.

[0124] Figure 22b for Fig.22a In some examples, a portion of the first sacrificial dielectric material layer is removed by an anisotropic etching process, such as Figure 22bAs shown, the first sacrificial dielectric material layer covering the first electrode portion and the insulating layer is removed to form the first sacrificial spacer structure 2541, which can define the spacing area between the gate electrode to be formed and the collector and emitter. In a specific example, the first electrode portion has an inclined sidewall, and accordingly the first sacrificial spacer structure 1541 has at least one oblique side in a cross section perpendicular to its extension direction, such as a parallelogram or an inverted trapezoid; wherein, the first sacrificial spacer structure is formed into an inverted trapezoid in a trapezoidal cross section perpendicular to its extension direction in a similar manner to the formation of the sacrificial spacer structure in the previous embodiment.

[0125] Next, step S23 is performed to form a first electrode material layer covering the first electrode portion and the first sacrificial sidewall structure, and the first electrode material layer is patterned to form a first gate electrode portion. At the same time, the top functional layer is patterned for a second time to form an emitter with a pointed tip based on the first electrode portion, and the first gate electrode portion has an end portion adjacent to the emitter tip.

[0126] Figure 23a to Figure 23b , are top views of the structure obtained after the first electrode material layer is formed in step S23. In some examples, the first electrode material layer 2520 is deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD) process, and the first electrode material layer 2520 can be made of a material suitable for making a collector, including but not limited to: one of polysilicon, Pt, Ru, Ir, Mo, Ti, Al, W, Co, Cr, Au, Cu, and Ag.

[0127] After the step of forming the first electrode material layer 2420 , an etching process is synchronously performed on the first electrode material layer 2520 and the first electrode portion, and the etching process stops at the surface of the insulating layer. Figures 25a to 25f , are schematic diagrams of the structures obtained after the emitter and the first gate portion are formed in step S23, wherein Figure 25b to Figure 25e They are Fig.25a The structure shown is cut along the AA', BB', CC', DD' sections. Fig.25f for Fig.25a Isometric view of the structure shown.

[0128] Before the step of patterning the first electrode portion 2510, the first electrode material layer is planarized to expose the top surface of the first electrode portion. The resulting structure is as shown in FIG. Figures 24a to 24c In a specific example, the first electrode material layer 2520 is planarized by, for example, a CMP process or a similar process, so that the top surface of the obtained first electrode material layer is flush with the top surface of the first electrode portion.

[0129] In some examples, the emitter 510 is formed by the following steps: forming a patterned mask layer on the first electrode material layer 2520, the patterned mask layer and the first electrode portion 2510 overlap, etching the first electrode portion 2510 based on the patterned mask layer to form an emitter 510 with a pointed tip, and the resulting structure is as shown in FIG. Fig.25a As shown; preferably, the patterned mask layer includes a photoresist pattern formed by lithography, and the patterned mask layer is formed on the first electrode portion 2510 and the first electrode material layer 2520 in a manner that a side wall is respectively beveled; based on the patterned mask layer, the first electrode material layer 2520 is etched, as shown Fig.25a and Fig.25f As shown, the emitter 510 is formed to have a sharp-angled tip.

[0130] like Fig.25a As shown, based on the patterned mask layer, a portion of the first electrode portion is removed through an anisotropic etching process to form an emitter 510, and at the same time a portion of the first electrode material layer is removed to form a first gate electrode portion 2560, and the first gate electrode portion and the etched end surface of the first electrode portion have overlapping extension surfaces; preferably, the first gate electrode portion and the etched end surface of the first electrode portion are coplanar.

[0131] Next, step S24 is performed to form a second sacrificial spacer structure on the sidewall with a pointed tip of the emitter and the sidewall of the first gate electrode portion to intersect with the first sacrificial spacer structure.

[0132] Specifically, the step of forming the second sacrificial sidewall structure 2545 includes: forming a second sacrificial dielectric material layer 2542 by covering the exposed surface of the insulating layer; performing an anisotropic etching process on the second sacrificial dielectric material layer 2542 to form the second sacrificial sidewall structure 2545. The second sacrificial dielectric material layer 2542 can be formed by a process similar to that of forming the first sacrificial dielectric material layer.

[0133] See also Figures 26a to 26e , are schematic diagrams of the structure obtained after the second sacrificial dielectric material layer is formed in step S24. Fig.26a As shown, the second sacrificial dielectric material layer 2542 also covers the top surface and side walls of the emitter and the first gate electrode portion. After the second sacrificial dielectric material layer covering the top surfaces of the emitter, the first gate electrode portion and the insulating layer is removed by an anisotropic etching process, a second sacrificial sidewall structure is formed on the pointed sidewalls of the emitter and the sidewalls of the first gate electrode portion, and the first sacrificial sidewall and the second sacrificial sidewall structure intersect.

[0134] like Fig.27a As shown, the second sacrificial spacer structure 2545 is formed on the sidewall of the emitter and the first gate electrode portion in the same plane, the first sacrificial spacer structure 2541 and the second sacrificial spacer structure 2545 can define the spacing area between the gate electrode to be formed and the collector and the emitter, and the second sacrificial spacer structure 2545 is also formed to cover the portion of the first sacrificial spacer structure that is not surrounded by the first electrode portion and the first gate electrode portion. By forming the first sacrificial spacer structure and the second sacrificial spacer structure to cross at an angle close to the tip of the emitter, the intersection area of ​​the first sacrificial spacer structure and the second sacrificial spacer structure defines the channel area to be formed, and because the second sacrificial spacer structure is also covered on the exposed portion of the first sacrificial spacer structure away from the emitter, the spacing between one side of the collector to be formed and the gate electrode is greater than the spacing between the other side and the gate electrode.

[0135] Next, step S25 is performed to form a collector from the intersection of the first sacrificial sidewall structure and the second sacrificial sidewall structure in a direction away from the emitter, the collector is adjacent to the first sacrificial sidewall structure and the second sacrificial sidewall structure and is formed at a diagonal position of the emitter tip, and a second gate electrode portion is formed adjacent to the end of the emitter tip and opposite to the first gate electrode portion.

[0136] Specifically, step S25 includes: forming a second electrode material layer 2530 ; and performing a planarization process on the second electrode material layer 2530 to form a collector 520 . Figures 27a to 27e , are schematic diagrams of the structure obtained after the second electrode material layer is formed in step S25.

[0137] The second electrode material layer 2530 may be conformally deposited on the insulating layer 220, and the deposited second electrode material layer 2530 has good step coverage. Fig.27a As shown, the second electrode material layer 2530 covers the emitter 510 , the first gate electrode portion 2560 , the first sacrificial spacer structure 2541 , the second sacrificial spacer structure 2545 , and the insulating layer 220 .

[0138] As an example, the second electrode material layer 2530 can be deposited by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) or a similar process. The material of the second electrode material layer 2530 includes but is not limited to: one of polysilicon, Pt, Ru, Ir, Mo, Ti, Al, W, Co, Cr, Au, Cu, and Ag.

[0139] At step S25, see Figures 28a to 28f, the second electrode material layer 2530 is planarized, wherein the method of planarizing the second electrode material layer 2530 includes, for example, a CMP process or a similar process, so that the top surface of the second electrode material is flush with the top surfaces of the emitter and the first gate electrode portion, and a collector 520 is formed with the emitter separated by the intersection area of ​​the first sacrificial sidewall structure and the second sacrificial sidewall structure as a spacer; that is, the collector 520 and the emitter 510 are diagonally arranged with respect to the intersection area of ​​the first sacrificial sidewall structure and the second sacrificial sidewall structure, and the end of the collector is also formed with a tip, and the collector and the tip of the emitter have approximately equal angles.

[0140] In one implementation, the collector 520 and the second gate electrode portion 2562 may be formed simultaneously, and accordingly, the gate electrode 560 and the collector 520 may be made of the same material, such as Figures 27a to 28a As shown, the second electrode material layer 2530 is planarized, and the top surface of the obtained second electrode material layer 2530 is flush with the top surfaces of the emitter and the first gate electrode portion, and a collector 520 is formed at a diagonal position of the emitter tip. At the same time, a second gate electrode portion 2562 is formed opposite to the first gate electrode portion, thereby forming a gate electrode 560 on both sides of the emitter and the collector. The gate electrode 560 can be separated from the emitter 510 and the collector 520 via the first sacrificial sidewall structure 2541 and the second sacrificial sidewall structure 2545, respectively.

[0141] In other implementations, the step of forming the gate electrode may be performed after the step of forming the collector, the first gate electrode portion 2560 and the second gate electrode portion 2562 may both be used as dummy gates, and the gate electrode and the collector may be made of different conductive materials. Fig.28a and Fig.30a , the gate electrode is formed by performing the following steps: removing the portion of the second electrode material layer (relative to the first sacrificial sidewall structure) located on the same side of the emitter, and the first gate electrode portion 2560. Fig.28a and Figures 31a to 35a It is a schematic diagram of the structure obtained at different stages in the preparation process of a nano vacuum channel transistor using the first gate electrode portion and the second gate electrode portion as dummy gates. Fig.28a and Figures 30a to 33aThe first gate electrode portion 2560 and the second gate electrode portion 2562 are both used as dummy gates. The step of forming the gate electrode 560 includes the following steps: forming a third electrode material layer that at least covers the insulating layer, and flattening the third electrode material layer. The top surface of the third electrode material layer is flush with the top surfaces of the emitter and the collector, thereby forming gate electrodes on both sides of the emitter and the collector.

[0142] Figures 31a to 32a Schematic diagrams of the structures obtained after forming the gate dielectric material layer and the gate dielectric layer, respectively. In some cases, before the step of forming the gate electrode, a gate dielectric layer is formed on the exposed surface of the insulating layer, the exposed sidewalls of the first sacrificial spacer structure and the second sacrificial spacer structure, such as Figures 31a to 32a As shown, before the step of forming the gate electrode, the gate dielectric layers 561a and 561b are formed so that the gate electrode 560 is separated from the first sacrificial sidewall structure 2541 and the second sacrificial sidewall structure 2545 by the gate dielectric layers 561a and 561b to reduce gate leakage and ensure gate stability.

[0143] The steps of forming the gate dielectric layers 561a and 561b include: covering the emitter 510 and the collector 520 to form a gate dielectric material layer 5610; performing an anisotropic etching process on the gate dielectric material layer 5610 to retain only the gate dielectric material layer 5610 covering the side walls of the first sacrificial sidewall structure and the second sacrificial sidewall structure; then, performing an anisotropic etching process on the gate dielectric material layer 5610 to form the gate dielectric layers 561a and 561b on the side walls of the first sacrificial sidewall structure and the second sacrificial sidewall structure.

[0144] Next, step S26 is performed to remove the first sacrificial spacer structure and the second sacrificial spacer structure to release the nanogap between the emitter and the collector.

[0145] See also Figures 29a to 29f, are schematic diagrams of the structures obtained after the first sacrificial sidewall structure and the second sacrificial sidewall structure are removed in step S26. As an example, the first sacrificial sidewall structure 2541 and the second sacrificial sidewall structure 2545 are selectively removed by dry etching or wet etching process to release the nano gap 550 between the emitter and the collector, and the gap between the gate electrode 560 and the emitter 510 and the collector 520. After removing the first sacrificial sidewall structure 2541 and the second sacrificial sidewall structure 2545, the gate dielectric layers 561a and 561b are formed at the sidewalls of the gate electrode 560 facing the emitter and the collector, and the gate dielectric layers 561a and 561b are spaced from the sidewalls of the emitter and the collector. In some cases, when the second sacrificial spacer structure 2545 is also formed to cover the portion of the first sacrificial spacer structure that is not surrounded by the first electrode portion and the first gate electrode portion, after removing the first sacrificial spacer structure and the second sacrificial spacer structure, the distance between the gate dielectric layer 561b and the collector 520 is greater than the distance between the gate dielectric layer 561b and the emitter 510, such as Fig.35c and Fig.35e shown.

[0146] Optionally, after step S26, the obtained nano vacuum channel transistor is packaged.

[0147] In an application scenario with vacuum requirements, the nano vacuum channel transistor is vacuum packaged, and the resulting structure is as follows: Figures 36a to 36f , Figures 37a to 37f and Figures 38a to 38f The packaging method described in the previous embodiment can be used to package the obtained nano vacuum channel transistor. The obtained structure is shown in the figure and will not be described in detail here.

[0148] Embodiment 3

[0149] The present invention further provides a nano vacuum channel transistor, which is preferably prepared by the method for preparing the nano vacuum channel transistor provided in the embodiment of the present invention. Of course, it can also be prepared by other preparation methods.

[0150] Hereinafter, the nano vacuum channel transistor of this embodiment is described in detail. The nano vacuum channel transistor at least comprises: a substrate layer, and an insulating layer and a gate electrode located on the substrate layer, the insulating layer having a first main surface and a second main surface opposite to each other, an emitter electrode and a collector electrode spaced apart and opposite to each other are arranged on the first main surface of the insulating layer, the end of the emitter electrode opposite to the collector electrode is arranged to be a tip, and a nanometer-level gap is defined between the tip of the emitter electrode and the end of the collector electrode to provide a channel region for the emitter electrode to emit electrons to the collector electrode; the gate electrode is arranged on the first main surface or the second main surface of the insulating layer and is located on the adjacent side of the nano gap, and is used to adjust the working state of the device.

[0151] In the vacuum channel transistor shown, the emission of vacuum electrons is achieved through field emission in the following manner: when a bias voltage is applied to the gate, the electric field strength between the emission electrode 510 and the collector electrode 520 is changed, thereby regulating the electron concentration in the emission electrode 510 and the potential barrier for electron emission, so that the gate electrode plays the role of a switch for electron emission, and the current density of the vacuum channel can be regulated by the voltage of the gate electrode.

[0152] The nano vacuum channel transistor is configured as a planar nano channel transistor, and the nano vacuum channel transistor comprises a back gate structure or a top gate structure, and the back gate structure or the top gate structure is configured to be parallel to the plane where the emitter and the collector are located.

[0153] In one implementation, the nano vacuum channel transistor includes a back gate structure, as shown in FIG. Fig.40 As shown, a first insulating layer 120, a back gate electrode 310 and a second insulating layer 140 are stacked on the substrate layer 110 from bottom to top, an emitter 510 and a collector 520 are arranged on the first main surface of the second insulating layer, and a back gate electrode 310 is arranged on the second main surface of the second insulating layer, that is, the back gate electrode 310 is separated from the emitter 510 and the collector 520 by the second insulating layer 140, and the second insulating layer 140 is used as a back gate dielectric layer.

[0154] Furthermore, the geometric shape of the emitter, especially the tip morphology, can be configured to increase the field enhancement factor and reduce the turn-on voltage of the device. Fig.41 and Fig.42aAs shown, the end of the emitter opposite to the collector can be set to a sharp-angled tip, and accordingly, the end of the collector extending toward the emitter is set to a concave profile substantially complementary to the emitter tip, so as to define a nanogap between the ends opposite to the emitter and the collector. By making the channel region defined between the emitter and the collector enter the nanometer level, the nano vacuum channel transistor can achieve high-speed switching of the device under low voltage or even in a non-vacuum environment. In this embodiment, the collector 520 is configured as a sidewall extending along the opening direction of the emitter vertex angle with a substantially constant nanogap, and the nanogap defined between the tip of the emitter and the end of the collector can have a size range of 0.1nm-50nm.

[0155] In other examples, the nano vacuum channel transistor includes a top gate structure, the top gate structure includes a top gate electrode (not shown), the top gate electrode is located on the second main surface of the second insulating layer and is separated from the emitter and the collector by the second insulating layer, and the second insulating layer is used as a gate dielectric layer.

[0156] In another implementation, the nano vacuum channel transistor includes a side gate structure, the side gate structure includes a gate electrode, the gate electrode is arranged on both sides of the emitter and the collector, and the working state of the device can be adjusted by applying different bias voltages to the gates on both sides. Fig.41 As shown in FIG42 , the emitter 510, the collector 520 and the gate electrode 560 are all located on the first main surface of the insulating layer 220. Since the gate electrode can be spaced apart from the emitter and the collector at a preset interval, the side gate structure can only include the gate electrode without the need for a gate dielectric layer, thereby improving the gate control capability.

[0157] In some examples, the side gate structure further includes gate dielectric layers 561a and 561b, which cover the bottom surface and sidewalls of the gate electrode to reduce gate leakage and ensure gate stability. Under the premise of not increasing leakage current, the transfer characteristics of the vacuum channel transistor are improved by reducing the thickness of the gate dielectric layer. Figures 42a to 42f As shown, the nano vacuum channel transistor includes a side gate structure, and the ends of the emitter and the collector extending toward each other are respectively arranged to be sharp-angled tips, and a nano gap is defined between the opposite tips of the emitter and the collector.

[0158] A nanogap 550 is defined between opposite ends of the emitter and the collector, as shown in FIG. Fig.40The cross-section of the nanogap perpendicular to the extension direction is rectangular, and in some cases, the nanogap 550 between the opposite ends of the emitter and the collector can have other cross-sectional shapes, such as a parallelogram or an inverted trapezoid, relative to the nanogap having a rectangular cross-sectional shape, such as Fig.17 , Fig.18 , Figure 37f and Figure 38f The cross section of the nanogap shown is rectangular when perpendicular to the extension direction. The tip of the emitter has an inclined sidewall to form a needle tip at its bottom surface. The emitter has a needle tip end, which can increase the effective emission area and improve the efficiency of electron emission.

[0159] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a nano vacuum channel transistor, characterized in that: The following steps are involved: Providing an SOI substrate, the SOI substrate comprising a back substrate, an insulating layer and a top functional layer, and performing a first patterning on the top functional layer to form a first electrode portion; forming a first sacrificial spacer structure on a sidewall of the first electrode portion; A first electrode material layer is formed covering the first electrode portion and the first sacrificial sidewall structure, the first electrode material layer is patterned to form a first gate electrode portion, and the top functional layer is patterned for a second time, and an emitter with a tip is formed based on the first electrode portion, wherein the first gate electrode portion has an end portion adjacent to the tip of the emitter; Forming a second sacrificial spacer structure on the sidewall with a pointed tip of the emitter and the sidewall of the first gate electrode portion to intersect with the first sacrificial spacer structure; A collector is formed from the intersection of the first sacrificial spacer structure and the second sacrificial spacer structure in a direction away from the emitter, the collector is formed adjacent to the first sacrificial spacer structure and the second sacrificial spacer structure at a diagonal position of the emitter tip, and a second gate electrode portion is formed adjacent to an end of the emitter tip and opposite to the first gate electrode portion; The first sacrificial spacer structure and the second sacrificial spacer structure are removed to release the nanogap between the emitter and the collector.

2. The method for preparing a nano vacuum channel transistor according to claim 1, characterized in that: After the step of forming the first electrode material layer, the emitter and the first gate electrode portion are synchronously formed through the following steps: the first electrode material layer is planarized so that the top surface of the obtained first electrode material layer is flush with the top surface of the first electrode portion; the first electrode portion and the first electrode material layer are anisotropically etched based on a patterned mask layer, and the patterned mask layer is formed on the first electrode portion and the first electrode material layer in a manner such that a side wall of the patterned mask layer respectively bevels the first electrode portion and the first electrode material layer, so that the etched end surfaces of the emitter and the first gate electrode portion are coplanar.

3. The method for preparing a nano vacuum channel transistor according to claim 2, characterized in that: The step of forming the second sacrificial sidewall structure includes: forming a second sacrificial dielectric material layer covering the exposed surface of the insulating layer; performing an anisotropic etching process on the second sacrificial dielectric material layer to form a second sacrificial sidewall structure on the etched end surfaces of the emitter and the first gate electrode portion, wherein the second sacrificial sidewall structure intersects with the first sacrificial sidewall structure.

4. The method for preparing a nano vacuum channel transistor according to claim 1, characterized in that: After the step of forming the second sacrificial sidewall structure, it includes: forming a third electrode material layer covering the insulating layer; flattening the third electrode material layer, forming a collector at a diagonal position of the emitter tip, and forming a second gate electrode portion opposite to the first gate electrode portion.

5. The method for preparing a nano vacuum channel transistor according to claim 1, characterized in that: After the step of forming the collector, a gate electrode is formed by performing the following steps: removing the first gate electrode portion and the second gate electrode portion; forming a third electrode material layer overlying the insulating layer; and flattening the third electrode material layer so that the top surface of the third electrode material layer is flush with the top surfaces of the emitter and the collector, thereby forming gate electrodes on both sides of the emitter and the collector.

6. The method for preparing a nano vacuum channel transistor according to claim 5, characterized in that: Before the step of forming the gate electrode, it includes: forming a gate dielectric material layer covering the emitter and the collector; performing an anisotropic etching process on the gate dielectric material layer, and forming the gate dielectric material layer retained on the side walls of the first sacrificial sidewall structure and the second sacrificial sidewall structure into a gate dielectric layer.

7. A method for preparing a nano vacuum channel transistor, characterized in that: The following steps are involved: Providing a substrate layer, forming a first insulating layer, a polycrystalline semiconductor layer, a second insulating layer and a top functional layer on the substrate layer, and patterning the top functional layer to form an emitter with a pointed tip; forming a sacrificial sidewall structure on the sidewall of the emitter; A collector is formed by using the sacrificial sidewall structure as a spacer and spaced apart from the emitter, wherein the collector is formed adjacent to the tip of the emitter; Forming a gate structure, comprising the following steps: forming a gate dielectric layer based on the second insulating layer; forming a gate electrode based on the polycrystalline semiconductor layer; wherein the emitter and the collector are formed on a first main surface of the second insulating layer, and the polycrystalline semiconductor layer is formed on a second main surface of the second insulating layer opposite to the first main surface; The sacrificial sidewall structure is removed to release the nano-gap between the collector and the emitter.

8. The method for preparing a nano vacuum channel transistor according to claim 7, characterized in that: The steps of forming the sacrificial sidewall structure include: forming a sacrificial dielectric material layer covering the patterned top functional layer; removing a portion of the sacrificial dielectric material layer by an anisotropic etching process, and retaining the sacrificial dielectric material layer covering the emitter sidewall to form the sacrificial sidewall structure.

9. The method for preparing the nano vacuum channel transistor according to claim 7, characterized in that: The step of forming the collector includes: forming an electrode material layer covering the emitter and the sacrificial sidewall structure; and flattening the electrode material layer so that the top surface of the obtained electrode material layer is flush with the top surface of the emitter and the sacrificial sidewall structure.

10. The method for preparing a nano vacuum channel transistor according to claim 7, characterized in that: The cross section of the sacrificial sidewall structure perpendicular to its extension direction is formed into a rectangle, a parallelogram or an inverted trapezoid.

11. The method for preparing a nano vacuum channel transistor according to claim 7, characterized in that: Also includes: Metal contacts are formed on the emitter and the collector as well as metal electrodes for electrical extraction.

12. A nano vacuum channel transistor, characterized in that: include: substrate layer; an insulating layer, located on the substrate layer, the insulating layer having a first main surface and a second main surface opposite to each other, an emitter and a collector spaced apart from each other and opposite to each other are arranged on the first main surface of the insulating layer, an end of the emitter opposite to the collector is arranged to be a pointed tip, and a nano-gap is defined between the tip of the emitter and the end of the collector to provide a channel region for the emitter to emit electrons to the collector; A gate electrode is disposed on the first main surface or the second main surface of the insulating layer and is located at a side adjacent to the nanogap.

13. The nano vacuum channel transistor according to claim 12, characterized in that: The sidewall of the collector extending toward the emitter is configured to have a concave profile substantially complementary to the emitter tip to define a nanogap between opposite sidewalls of the emitter and the collector, wherein the size of the nanogap ranges from 0.1 nm to 50 nm.

14. The nano vacuum channel transistor according to claim 12, characterized in that: The ends of the emitter and the collector extending toward each other are respectively configured to form sharp-angled tip structures, and a nanogap is defined between the opposite tips of the emitter and the collector, wherein the size of the nanogap ranges from 0.1 nm to 50 nm.

15. The nano vacuum channel transistor according to claim 14, characterized in that: The gate electrode is located at both sides of the emitter and the collector and is spaced apart from the emitter and the collector respectively.

16. The nano vacuum channel transistor according to claim 12, characterized in that: Also includes: A gate dielectric layer is disposed on the bottom surface and sidewalls of the gate electrode to reduce leakage current of the gate electrode. The cross section of the nanogap between the emitter and the collector perpendicular to the extension direction thereof is rectangular, parallelogram or inverted trapezoidal.

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