Semiconductor packaging structure and forming method thereof

Abstract

The invention discloses a semiconductor packaging structure and a forming method thereof, and the forming method comprises the steps: providing a substrate; a semiconductor chip is provided, the semiconductor chip comprises an active surface and a back surface which are opposite to each other, the active surface of the semiconductor chip is downwards attached to the upper surface of the substrate, and the semiconductor chip is electrically connected with the substrate; forming a coating layer covering the side surface of the semiconductor chip, wherein the upper surface of the coating layer is flush with the back surface of the semiconductor chip; forming metal films on the back surface of the semiconductor chip and the upper surface of the coating layer; forming a thermal interface material on the upper surface of the metal film; and a heat dissipation cover is mounted on the upper surfaces of the substrate and the thermal interface material. According to the method, the layering defect of the thermal interface material at the edge is prevented, and the heat dissipation effect and efficiency are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging, and in particular to a semiconductor packaging structure and a method for forming the same. Background Art

[0002] Nowadays, electronic devices are rapidly developing towards high integration, high assembly density and high operating speed. As the core of electronic devices, semiconductor chips have been increasing in integration, packaging density and working clock frequency while their size is shrinking. Therefore, the heat generated per unit area of ​​semiconductor chips is increasing. This is especially serious for high-power electronic devices. Excessive temperature may even damage semiconductor chips and even cause safety hazards.

[0003] There are currently a variety of heat dissipation solutions for semiconductor chips, one of which is to dissipate heat from the semiconductor chip through a heat dissipation cover. When using a heat dissipation cover to dissipate heat from a semiconductor chip, the heat dissipation cover is usually attached to the back surface of the semiconductor chip, and a thermal interface material layer (TIM) with high thermal conductivity needs to be coated between the lower surface of the heat dissipation cover and the back of the semiconductor chip to conduct heat. Due to the repeated deformation of the product, this existing heat dissipation method reduces the bonding force between the thermal interface material layer and the back of the semiconductor chip, and the thermal interface material layer is delaminated around the edge of the semiconductor chip, which reduces the effective heat dissipation area of ​​the thermal interface material layer, thereby reducing the effect or efficiency of heat dissipation. Summary of the invention

[0004] The technical problem to be solved by the present application is to provide a semiconductor packaging structure and a method for forming the same, so as to prevent the thermal interface material from generating delamination defects at the edge position and improve the efficiency of heat dissipation.

[0005] To this end, the present application first provides a method for forming a semiconductor packaging structure, comprising:

[0006] providing a substrate;

[0007] Providing a semiconductor chip, the semiconductor chip comprising an active surface and a back surface opposite to each other, mounting the semiconductor chip on the upper surface of the substrate with the active surface facing downward, and the semiconductor chip being electrically connected to the substrate;

[0008] forming a coating layer covering the side surface of the semiconductor chip, wherein the upper surface of the coating layer is flush with the back surface of the semiconductor chip;

[0009] forming a metal film on the back surface of the semiconductor chip and the upper surface of the cladding layer;

[0010] forming a thermal interface material on the upper surface of the metal film;

[0011] A heat dissipation cover is mounted on the upper surface of the substrate and the thermal interface material.

[0012] In an optional embodiment, the material of the metal film is a metal or alloy with high thermal conductivity, and the formation process of the metal film includes sputtering.

[0013] In an optional embodiment, the material of the metal film is one or more of copper, gold, nickel, and titanium, and the thickness of the metal film is 0.4-0.6 microns.

[0014] In an optional embodiment, it also includes: before forming the metal film, performing a first roughening treatment on the back side of the semiconductor chip and the upper surface of the coating layer to increase the roughness of the back side of the semiconductor chip and the upper surface of the coating layer; after performing the first roughening treatment, forming the metal film on the back side of the semiconductor chip and the upper surface of the coating layer.

[0015] In an optional embodiment, it is characterized in that it also includes: before forming the thermal interface material, performing a second roughening treatment on the upper surface of the metal film to increase the roughness of the upper surface of the metal film; after performing the second roughening treatment, forming the thermal interface material on the upper surface of the metal film.

[0016] In an optional embodiment, the first roughening treatment and the second roughening treatment include plasma bombardment, and the plasma is an inert gas element plasma.

[0017] In an optional embodiment, after the first roughening treatment, the roughness of the upper surface of the coating layer is greater than the roughness of the back side of the semiconductor chip; the metal film includes a middle area and an edge area surrounding the middle area, and after the second roughening treatment, the roughness of the upper surface of the edge area of ​​the metal film is greater than the roughness of the upper surface of the middle area.

[0018] In an optional embodiment, the process of forming the coating layer includes: using a dispensing process to form a plastic encapsulation material layer covering the side and back sides of the semiconductor chip; using a grinding process to remove part of the plastic encapsulation material layer to expose the back side of the semiconductor chip, thereby forming a coating layer covering the side sides of the semiconductor chip.

[0019] In an optional embodiment, the thermal interface material is a thermal conductive adhesive; and the material of the coating layer is a plastic packaging material.

[0020] In an optional embodiment, it further includes: mounting a passive component on the surface of a substrate on one side of the semiconductor chip, wherein the passive component is electrically connected to the substrate.

[0021] The present application also provides a semiconductor packaging structure, comprising:

[0022] substrate;

[0023] A semiconductor chip, wherein the semiconductor chip comprises an active surface and a back surface opposite to each other, the active surface of the semiconductor chip is mounted on the upper surface of the substrate with the active surface facing downward, and the semiconductor chip is electrically connected to the substrate;

[0024] A coating layer covering the side surface of the semiconductor chip, wherein the upper surface of the coating layer is flush with the back surface of the semiconductor chip;

[0025] a metal film located on the back side of the semiconductor chip and the upper surface of the cladding layer;

[0026] a thermal interface material located on the upper surface of the metal film;

[0027] A heat dissipation cover is mounted on the upper surface of the substrate and the thermal interface material.

[0028] In an optional embodiment, in a direction perpendicular to the side surface of the semiconductor chip, the width of the coating layer on the side surface of the semiconductor chip is 9%-15% of the distance between two opposite side surfaces of the semiconductor chip.

[0029] In an optional embodiment, an underfill layer is further filled between the active surface of the semiconductor chip and the upper surface of the substrate.

[0030] In an optional embodiment, the material of the metal film is a metal or alloy with high thermal conductivity.

[0031] In an optional embodiment, the material of the metal film is one or more of copper, gold, nickel, and titanium, and the thickness of the metal film is 0.4-0.6 microns.

[0032] In an optional embodiment, the material of the coating layer is a plastic packaging material; and the thermal interface material is a thermal conductive adhesive.

[0033] In an optional embodiment, it further includes: a passive device mounted on the upper surface of the substrate on one side of the semiconductor chip, wherein the passive device is electrically connected to the substrate.

[0034] Compared with the prior art, the advantages of the technical solution of this application are:

[0035] The semiconductor packaging structure and the method for forming the same in the aforementioned embodiments of the present application, in one embodiment, the method for forming the packaging structure includes: providing a substrate; providing a semiconductor chip, the semiconductor chip including a relative active surface and a back surface, mounting the semiconductor chip with the active surface facing down on the upper surface of the substrate, the semiconductor chip being electrically connected to the substrate; forming a coating layer covering the side surface of the semiconductor chip, the upper surface of the coating layer being flush with the back surface of the semiconductor chip; forming a metal film on the back surface of the semiconductor chip and the upper surface of the coating layer; forming a thermal interface material on the upper surface of the metal film; mounting a heat dissipation cover on the upper surfaces of the substrate and the thermal interface material. In the present application, a coating layer is formed to cover the side of the semiconductor chip, and the upper surface of the coating layer is flush with the back side of the semiconductor chip. In addition to protecting the semiconductor chip, the coating layer also widens the support space on the back side of the semiconductor chip, so that the coverage area of ​​the subsequently formed metal film and thermal interface material is larger than the area of ​​the back side of the semiconductor chip, thereby improving the heat dissipation coverage rate of the thermal interface material (the heat dissipation coverage rate is the ratio of the effective heat dissipation area of ​​the thermal interface material and the back side of the semiconductor chip to the area of ​​the back side of the semiconductor chip. Even if there are stratification defects at the edge of the thermal interface material, the heat dissipation coverage rate of the thermal interface material is still relatively high), thereby improving the heat dissipation effect and efficiency. In addition, a metal film is formed on the back side of the semiconductor chip and the upper surface of the coating layer. On the one hand, the metal film can combine the coating layer and the semiconductor chip of different materials into a whole. The thermal interface material is subsequently formed on the surface of the metal film, which can prevent the edge of the thermal interface material from having delamination defects (when the thermal interface material is directly formed on the upper surface of the coating layer and the back side of the semiconductor chip, since the coating layer and the semiconductor chip are not a whole, stress or deformation will be generated between the coating layer and the semiconductor chip, causing delamination defects in the edge of the thermal interface material); on the other hand, the metal film has good adhesion to the subsequently formed thermal interface material, and the metal film itself has high thermal conductivity, which can efficiently transfer the heat from the back side of the semiconductor chip to the thermal interface material, and efficiently conduct the heat to the subsequently mounted heat dissipation cover through the thermal interface material for release.

[0036] Furthermore, in one embodiment, before forming the metal film, a first roughening treatment 11 is performed on the back side of the semiconductor chip and the upper surface of the coating layer to increase the roughness of the back side of the semiconductor chip and the upper surface of the coating layer. When a metal film is subsequently formed on the back side of the semiconductor chip and the upper surface of the coating layer after the first roughening treatment, the contact area between the metal film and the back side of the semiconductor chip and the upper surface of the coating layer can be increased, thereby improving the bonding force between the metal film and the back side of the semiconductor chip and the upper surface of the coating layer, thereby preventing the edge of the metal film from having delamination defects relative to the upper surface of the coating layer, and further preventing the thermal interface material subsequently formed on the upper surface of the metal film and the upper surface of the coating layer from having delamination defects relative to the back side of the semiconductor chip, thereby better improving the heat dissipation effect and efficiency.

[0037] Furthermore, in one embodiment, before forming the thermal interface material, the upper surface of the metal film is subjected to a second roughening treatment to increase the roughness of the upper surface of the metal film. When the thermal interface material is subsequently formed on the upper surface of the metal film after the second roughening treatment, the contact area between the thermal interface material and the upper surface of the metal film is increased, thereby improving the bonding force between the thermal interface material and the upper surface of the metal film, thereby preventing the edge of the thermal interface material from generating delamination defects relative to the upper surface of the metal film, improving the heat dissipation coverage of the thermal interface material, and better improving the heat dissipation effect and efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1-Figure 9 It is a structural schematic diagram of the formation process of the semiconductor packaging structure in some embodiments of the present application. DETAILED DESCRIPTION

[0039] The specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0040] Some embodiments of the present application first provide a method for forming a semiconductor packaging structure. The formation process of the semiconductor packaging structure is described in detail below with reference to the accompanying drawings.

[0041] refer to Figure 1 , providing a substrate 101.

[0042] The substrate 101 serves as a support carrier and a connection carrier in the packaging process. In one embodiment, the upper surface of the substrate 101 has a plurality of discrete first pads 102, the lower surface of the substrate 101 has a plurality of discrete second pads 103, and the substrate 101 has a connection line 104, the connection line 104 may include one or more of a metal layer, a connection plug, a through-hole connection structure (TSV), and a via connection structure, the connection line 104 may be used for the electrical connection between the first pad on the upper surface of the substrate 101 and the corresponding second pad on the lower surface of the substrate 101, the connection line 104 may also be used for the electrical connection between some of the first pads on the upper surface of the substrate 101, and the connection line 104 is also used for the electrical connection between some of the second pads on the lower surface of the substrate 101. The first pads 102 on the upper surface of the substrate 101 are electrically connected to the semiconductor chips and other devices subsequently mounted on the upper surface of the substrate 101, and external protrusions may be formed on the second pads on the lower surface of the substrate 101, and the external protrusions are used to connect with other devices or packaging structures. In one embodiment, the material of the first pad 102, the second pad 103 and the connecting line 104 is metal, specifically one or more of aluminum, copper, nickel, tin, titanium, tungsten, platinum, chromium, tantalum, gold, and silver. The material of the external protrusion is tin or a tin alloy, and the tin alloy is one or more of tin-silver, tin-zinc, tin-lead, tin-indium, tin-gold, tin-copper, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony. In one embodiment, the substrate 101 can be one of a silicon substrate, an RDL substrate (Re-distribution Layer, rewiring), a resin substrate, a printed circuit board (PCB), a ceramic substrate, a glass substrate, or a flexible circuit board (FPC). In one embodiment, the substrate 101 can be a single-layer board or a multi-layer board. In one embodiment, the substrate 101 can be used as an interposer.

[0043] refer to Figure 2 , providing a semiconductor chip 201, wherein the semiconductor chip 201 includes an active surface and a back surface opposite to each other, and mounting the semiconductor chip 201 on the upper surface of the substrate 101 with the active surface facing downward, and the semiconductor chip 201 is electrically connected to the substrate 101.

[0044] The semiconductor chip 201 includes a relative back side and an active side, an integrated circuit (with specific functions) (not shown in the figure) is formed in the semiconductor chip, and a plurality of solder bumps 202 are provided on the active side, and the plurality of solder bumps 202 are electrically connected to the integrated circuit. The solder bumps 202 may be solder bumps or include metal bumps and solder bumps located on the top surface of the metal bumps. In a specific embodiment, the material of the metal bumps is one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver, and the material of the solder bumps is one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony.

[0045] The semiconductor chip 201 includes but is not limited to a signal processing semiconductor chip, a logic control semiconductor chip, a storage semiconductor chip, a sensor semiconductor chip, a power semiconductor chip or a radio frequency semiconductor chip according to different functions.

[0046] In one embodiment, when the semiconductor chip 201 is mounted on the upper surface of the substrate 101 with its active surface facing downward, the soldering protrusions 202 on the active surface of the semiconductor chip 201 are soldered to the corresponding first solder pads 102 on the upper surface of the substrate 101 .

[0047] In one embodiment, an underfill layer 203 is further filled between the active surface of the semiconductor chip 201 and the upper surface of the substrate 101 .

[0048] In one embodiment, it further includes: mounting a passive device 210 on the upper surface of the substrate 101 on one side of the semiconductor chip 201, and the passive device 210 is electrically connected to the substrate 101. The passive device 210 may be one or more. The passive device 210 may be one or more of an inductor, a capacitor, and a resistor. In a specific embodiment, the passive device 210 has a pin, and the pin is soldered to the corresponding first pad 102 on the upper surface of the substrate 101 through solder.

[0049] refer to Figure 3 and Figure 4 , forming a covering layer 204 covering the side surface of the semiconductor chip 201 , wherein the upper surface of the covering layer 204 is flush with the back surface of the semiconductor chip 201 .

[0050] In addition to protecting the semiconductor chip 201, the coating layer 204 also expands the support space on the back of the semiconductor chip 201, so that the metal film 205 and the thermal interface material 206 (see Fig. 9) coverage area is larger than the area of ​​the back side of the semiconductor chip 201, thereby improving the heat dissipation coverage rate of the thermal interface material 206 (the heat dissipation coverage rate is the ratio of the effective heat dissipation area between the thermal interface material and the back side of the semiconductor chip 201 to the area of ​​the back side of the semiconductor chip 201. Even if there are delamination defects at the edge of the thermal interface material, the heat dissipation coverage rate of the thermal interface material is still relatively high), thereby improving the heat dissipation effect and efficiency.

[0051] In one embodiment, the material of the coating layer 204 is a plastic encapsulation material. The plastic encapsulation material is a resin material or resin glue containing fillers. In a specific example, the plastic encapsulation material can be epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin containing fillers; or can also be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol containing fillers. The filler can be an inorganic filler or an organic filler.

[0052] In one embodiment, the process of forming the coating layer 204 includes: referring to Figure 3 , a plastic encapsulation material layer 214 covering the side and back sides of the semiconductor chip 201 is formed by a dispensing process; Figure 4 A grinding process is used to remove part of the plastic packaging material layer to expose the back side of the semiconductor chip 201, thereby forming a coating layer 204 covering the side of the semiconductor chip 201, and the upper surface of the coating layer 204 is flush with the back side of the semiconductor chip 201.

[0053] In one embodiment, in a direction perpendicular to the side of the semiconductor chip 201, the width of the coating layer 204 on the side of the semiconductor chip 201 is 9%-15% of the distance between the two opposite side surfaces of the semiconductor chip 201. Subsequently, a metal film 205 and a thermal interface material 206 located on the upper surface of the metal film 205 are formed on the upper surface of the coating layer 204 and the back surface of the semiconductor chip 201 (refer to Fig. 9 ) when the width of the covering layer 20 is too small, the heat dissipation coverage of the thermal interface material 206 is insufficient; when the width of the covering layer 20 is too large, the covering layer 204 occupies a larger area of ​​the substrate 101, which is not conducive to improving the integration of the packaging structure.

[0054] In one embodiment, reference Figure 5 , further comprising: forming a metal film 205 (reference Figure 6), the back surface of the semiconductor chip 201 and the upper surface of the cladding layer 204 are subjected to a first roughening treatment 11 to increase the roughness of the back surface of the semiconductor chip 201 and the upper surface of the cladding layer 204, and a metal film 205 is subsequently formed on the back surface of the semiconductor chip 201 and the upper surface of the cladding layer 204 after the first roughening treatment 11 (refer to Figure 6 ), the contact area between the metal film and the back side of the semiconductor chip 201 and the upper surface of the coating layer 204 can be increased, thereby improving the bonding force between the metal film 205 and the back side of the semiconductor chip 201 and the upper surface of the coating layer 204, thereby preventing the edge of the metal film 205 from generating delamination defects relative to the upper surface of the coating layer 204, and further preventing the thermal interface material subsequently formed on the upper surface of the metal film 206 from generating delamination defects with the upper surface of the coating layer 204, so as to better improve the heat dissipation effect and efficiency.

[0055] In one embodiment, the first roughening treatment 11 includes plasma bombardment, and the plasma is an inert gas element plasma, such as Ar plasma, He plasma or Xe plasma.

[0056] In one embodiment, after the first roughening treatment 11 , the roughness of the upper surface of the cladding layer 204 and the back surface of the semiconductor chip 201 are the same or equivalent.

[0057] In another embodiment, after the first roughening treatment 11, the roughness of the upper surface of the coating layer 204 is greater than the roughness of the back surface of the semiconductor chip 201. When a metal film 205 is subsequently formed on the upper surface of the coating layer 204 and the back surface of the semiconductor chip 201 after the first roughening treatment 11, the metal film 205 has a stronger bonding force with the upper surface of the coating layer 204, which is more conducive to preventing the edge of the metal film 205 from generating a delamination defect with the coating layer 204, thereby preventing the thermal interface material 206 (refer to Figure 8 ) produces delamination defects at the edges.

[0058] refer to Figure 6 A metal film 205 is formed on the back surface of the semiconductor chip 201 and the upper surface of the cladding layer 204 .

[0059] By forming a metal film 205 on the back side of the semiconductor chip 201 and the upper surface of the coating layer 204, on the one hand, the metal film 205 can combine the coating layer 204 and the semiconductor chip 201 of different materials into a whole, and the thermal interface material is subsequently formed on the surface of the metal film 205, which can prevent the edge of the thermal interface material from having delamination defects (when the thermal interface material is directly formed on the upper surface of the coating layer 204 and the back side of the semiconductor chip 201, since the coating layer 204 and the semiconductor chip 201 are not a whole, stress or deformation will be generated between the coating layer 204 and the semiconductor chip 201, so that the edge of the thermal interface material will have delamination defects); on the other hand, the metal film 205 has good adhesion with the subsequently formed thermal interface material, and the metal film 205 itself has high thermal conductivity, which can efficiently transfer the heat on the back side of the semiconductor chip 201 to the thermal interface material, and efficiently conduct it to the subsequently mounted heat dissipation cover for release through the thermal interface material.

[0060] In one embodiment, the material of the metal film 205 is a metal or alloy with high thermal conductivity, specifically one or more of copper, gold, nickel, and titanium, and the formation process of the metal film 205 includes sputtering. The thickness of the metal film 205 is 0.4-0.6 microns. While the coating layer 204 of different materials and the semiconductor chip 201 are better combined into a whole, the mechanical stability and thermal conductivity of the metal film 205 are improved.

[0061] In one embodiment, the back surface of the semiconductor chip 201 and the upper surface of the cladding layer 204 are subjected to a first roughening treatment 11 (see Figure 5 ), after increasing the roughness of the back surface of the semiconductor chip 201 and the upper surface of the cladding layer 204, the metal film 205 is formed on the back surface of the semiconductor chip 201 and the upper surface of the cladding layer 204 (refer to Figure 6 ).

[0062] In one embodiment, reference Figure 7 , characterized in that it also includes: forming a thermal interface material 206 (reference Figure 8 ), the upper surface of the metal film 205 is subjected to a second roughening treatment 12 to increase the roughness of the upper surface of the metal film 205. When the thermal interface material 206 is subsequently formed on the upper surface of the metal film 205 after the second roughening treatment 12, the contact area between the thermal interface material 206 and the upper surface of the metal film 205 is increased, thereby improving the bonding force between the thermal interface material 206 and the upper surface of the metal film 205, thereby preventing the edge of the thermal interface material 206 from generating delamination defects relative to the upper surface of the metal film 205, improving the heat dissipation coverage of the thermal interface material 206, and better improving the heat dissipation effect and efficiency.

[0063] In one embodiment, the second roughening process 12 includes plasma bombardment, and the plasma is an inert gas element plasma, such as Ar plasma, He plasma or Xe plasma.

[0064] In one embodiment, after the second roughening treatment 12 , the roughness of the upper surface of different regions of the metal film 205 is the same or equivalent.

[0065] In another embodiment, the metal film 205 includes a middle area and an edge area surrounding the middle area. After the second roughening treatment 12, the roughness of the upper surface of the edge area of ​​the metal film 205 is greater than the roughness of the upper surface of the middle area of ​​the metal film 205. When the thermal interface material 206 is subsequently formed on the upper surface of the metal film 205 after the second roughening treatment 12, the bonding force between the thermal interface material 206 and the upper surface of the edge area of ​​the metal film 205 is stronger, which is more conducive to preventing the edge of the thermal interface material 206 from generating delamination defects.

[0066] refer to Figure 8 , a thermal interface material 206 is formed on the upper surface of the metal film 205 .

[0067] The thermal interface material (TIM) 206 can effectively reduce the contact thermal resistance between different structures, and realize the rapid transfer of heat generated by the semiconductor chip to the subsequently mounted heat dissipation cover.

[0068] In one embodiment, the thermal interface material 206 is a thermally conductive adhesive. In one embodiment, the thermal interface material 206 can be formed by a dispensing process, a printing process, a rolling process or a film pasting process.

[0069] In one embodiment, the upper surface of the metal film 205 is subjected to a second roughening treatment 12 (see Figure 7 ), after increasing the roughness of the upper surface of the metal film 205, a thermal interface material 206 is formed on the upper surface of the metal film 205 (refer to Figure 8 ).

[0070] refer to Fig. 9 A heat dissipation cover 208 is mounted on the upper surface of the substrate 101 and the thermal interface material 206 .

[0071] The heat dissipation cover 208 is used to release or dissipate the heat generated by the semiconductor chip 201 to control the semiconductor chip 201 to a suitable temperature. The heat dissipation cover 208 is formed of a material with high thermal conductivity. In some embodiments, the material with high thermal conductivity includes metal (such as copper, aluminum, gold, nickel, steel or stainless steel) or carbon-containing material (such as graphite, graphene or carbon nanotubes).

[0072] In one embodiment, the heat dissipation cover 208 includes a cover top and a cover edge protruding from the lower surface of the edge of the cover top, the lower surface of the cover top of the heat dissipation cover 208 contacts the upper surface of the thermal interface material 206, and the bottom end surface of the cover edge of the heat dissipation cover 208 is adhered to the upper surface of the substrate 101 by an adhesive 207.

[0073] An embodiment of the present application also provides a semiconductor packaging structure, referring to Fig. 9 ,include:

[0074] substrate 101;

[0075] A semiconductor chip 201, wherein the semiconductor chip 201 comprises an active surface and a back surface opposite to each other, and the active surface of the semiconductor chip 201 is mounted on the upper surface of the substrate 101 with the active surface facing downward, and the semiconductor chip 201 is electrically connected to the substrate 101;

[0076] A cladding layer 204 covering the side surface of the semiconductor chip 201, wherein the upper surface of the cladding layer 204 is flush with the back surface of the semiconductor chip 201;

[0077] A metal film 205 located on the back side of the semiconductor chip 201 and the upper surface of the cladding layer 204;

[0078] A thermal interface material 206 located on the upper surface of the metal film 205;

[0079] A heat dissipation cover 208 is mounted on the upper surface of the substrate 101 and the thermal interface material 206 .

[0080] In one embodiment, in a direction perpendicular to the side surface of the semiconductor chip 201 , the width of the cladding layer 204 on the side surface of the semiconductor chip 201 is 9%-15% of the distance between two opposite side surfaces of the semiconductor chip 201 .

[0081] In one embodiment, an underfill layer 203 is further filled between the active surface of the semiconductor chip 201 and the upper surface of the substrate 101 .

[0082] In one embodiment, the material of the metal film 205 is a metal or alloy with high thermal conductivity, the material of the metal film 205 is one or more of copper, gold, nickel, and titanium, and the thickness of the metal film 205 is 0.4-0.6 microns.

[0083] In one embodiment, the upper surface of the cladding layer 204 and the back surface of the semiconductor chip 201 are rough surfaces. In one embodiment, the roughness of the upper surface of the cladding layer 204 is greater than the roughness of the back surface of the semiconductor chip 201 .

[0084] In one embodiment, the upper surface of the metal film 205 is a rough surface. In one embodiment, the roughness of the upper surface of the edge region of the metal film 205 is greater than the roughness of the upper surface of the middle region of the metal film 205.

[0085] In one embodiment, the material of the coating layer 204 is a plastic packaging material. The thermal interface material 206 is a thermal conductive adhesive.

[0086] In one embodiment, it further includes: a passive device 210 mounted on the upper surface of the substrate 101 on one side of the semiconductor chip 201 , and the passive device 210 is electrically connected to the substrate 101 .

[0087] Although the present application has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field can use the methods and technical contents disclosed above to make possible changes and modifications to the technical solution of the present application without departing from the spirit and scope of the present application. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are within the protection scope of the technical solution of the present application.

Claims

1. A method for forming a semiconductor packaging structure, It is characterized in that include: providing a substrate; Providing a semiconductor chip, the semiconductor chip comprising an active surface and a back surface opposite to each other, mounting the semiconductor chip on the upper surface of the substrate with the active surface facing downward, and the semiconductor chip being electrically connected to the substrate; forming a coating layer covering the side surface of the semiconductor chip, wherein the upper surface of the coating layer is flush with the back surface of the semiconductor chip; forming a metal film on the back surface of the semiconductor chip and the upper surface of the cladding layer; forming a thermal interface material on the upper surface of the metal film; A heat dissipation cover is mounted on the upper surface of the substrate and the thermal interface material.

2. The method for forming a semiconductor package structure according to claim 1, It is characterized in that The material of the metal film is a metal or alloy with high thermal conductivity, and the formation process of the metal film includes sputtering.

3. The method for forming a semiconductor package structure according to claim 1 or 2, It is characterized in that The material of the metal film is one or more of copper, gold, nickel and titanium, and the thickness of the metal film is 0.4-0.6 microns.

4. The method for forming a semiconductor package structure according to claim 1 or 2, It is characterized in that Also includes: Before forming the metal film, a first roughening treatment is performed on the back side of the semiconductor chip and the upper surface of the coating layer to increase the roughness of the back side of the semiconductor chip and the upper surface of the coating layer; after the first roughening treatment is performed, the metal film is formed on the back side of the semiconductor chip and the upper surface of the coating layer.

5. The method for forming a semiconductor package structure according to claim 4, It is characterized in that It is characterized in that it also includes: before forming the thermal interface material, performing a second roughening treatment on the upper surface of the metal film to increase the roughness of the upper surface of the metal film; after performing the second roughening treatment, forming the thermal interface material on the upper surface of the metal film.

6. The method for forming a semiconductor package structure according to claim 5, It is characterized in that The first roughening process and the second roughening process include plasma bombardment, and the plasma is an inert gas element plasma.

7. The method for forming a semiconductor package structure according to claim 5, It is characterized in that After the first roughening treatment, the roughness of the upper surface of the coating layer is greater than the roughness of the back side of the semiconductor chip; the metal film includes a middle area and an edge area surrounding the middle area, and after the second roughening treatment, the roughness of the upper surface of the edge area of ​​the metal film is greater than the roughness of the upper surface of the middle area.

8. The method for forming a semiconductor package structure according to claim 1, It is characterized in that The material of the coating layer is a plastic packaging material; and the thermal interface material is a thermal conductive adhesive.

9. The method for forming a semiconductor package structure according to claim 8, It is characterized in that The process of forming the coating layer includes: using a dispensing process to form a plastic packaging material layer covering the side and back of the semiconductor chip; using a grinding process to remove part of the plastic packaging material layer to expose the back of the semiconductor chip to form a coating layer covering the side of the semiconductor chip.

10. The method for forming a semiconductor package structure according to claim 1, It is characterized in that Also includes: A passive component is mounted on the surface of the substrate at one side of the semiconductor chip, and the passive component is electrically connected to the substrate.

11. A semiconductor packaging structure, It is characterized in that include: substrate; A semiconductor chip, wherein the semiconductor chip comprises an active surface and a back surface opposite to each other, the active surface of the semiconductor chip is mounted on the upper surface of the substrate with the active surface facing downward, and the semiconductor chip is electrically connected to the substrate; A coating layer covering the side surface of the semiconductor chip, wherein the upper surface of the coating layer is flush with the back surface of the semiconductor chip; a metal film located on the back side of the semiconductor chip and the upper surface of the cladding layer; a thermal interface material located on the upper surface of the metal film; A heat dissipation cover is mounted on the upper surface of the substrate and the thermal interface material.

12. The semiconductor package structure according to claim 11, It is characterized in that In a direction perpendicular to the side surface of the semiconductor chip, the width of the coating layer on the side surface of the semiconductor chip is 9%-15% of the distance between two opposite side surfaces of the semiconductor chip.

13. The semiconductor package structure according to claim 11, It is characterized in that An underfill layer is also filled between the active surface of the semiconductor chip and the upper surface of the substrate.

14. The semiconductor package structure according to claim 11, It is characterized in that The material of the metal film is a metal or alloy with high thermal conductivity.

15. The semiconductor package structure according to claim 11 or 14, It is characterized in that The material of the metal film is one or more of copper, gold, nickel and titanium, and the thickness of the metal film is 0.4-0.6 microns.

16. The semiconductor package structure according to claim 11, It is characterized in that The material of the coating layer is a plastic packaging material; and the thermal interface material is a thermal conductive adhesive.

17. The semiconductor package structure according to claim 11, It is characterized in that Also includes: A passive device is mounted on the upper surface of the substrate at one side of the semiconductor chip, and the passive device is electrically connected to the substrate.

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