Metal interconnection structure comprising MIM capacitor and manufacturing method thereof
By controlling the contact area between the electrode layer and the metal connection line in the metal interconnect structure of the MIM capacitor, the problem that MIM electricity is prone to hollow defects is solved, and the reliability and yield of the product are improved.
Patent Information
- Application Number
- CN202411218396.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2024-12-13
AI Technical Summary
MIM capacitors are prone to hollow defects in the metal interconnect structure of integrated circuits, resulting in reduced product reliability and yield.
In the metal interconnect structure, the contact area of the metal connecting wire in which the lower electrode layer of the MIM capacitor is in contact is smaller than its bottom area, and a multi-layer dielectric layer and metal connecting wire are adopted, including forming trenches and filling electrode layers and perform planarization to ensure control of contact area.
It reduces the probability of hollow defects in the lower electrode area, reduces the breakdown failure efficiency of MIM capacitors, and improves the reliability and yield of the product.
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Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to a metal interconnect structure including a MIM capacitor and a manufacturing method thereof. Background Art
[0002] Capacitors are often used as electronic passive devices in integrated circuits such as radio frequency and monolithic microwave. Common capacitors include metal-oxide-semiconductor (MOS) capacitors, positive negative junction (PN) capacitors, and metal-insulator-metal (MIM) capacitors. Among them, MIM capacitors are widely used in semiconductor integrated circuit manufacturing because they are easy to integrate into metal interconnect structures.
[0003] Typically, in the metal interconnect structure of an integrated circuit, the entire bottom surface of the lower electrode of the MIM capacitor contacts the metal wiring below it, and the upper electrode of the MIM capacitor contacts the metal wiring above it. Since the contact area between the lower electrode and the metal wiring is large, void defects are easily generated, resulting in capacitor failure and reducing product reliability and yield. Summary of the invention
[0004] The present application provides a metal interconnect structure including a MIM capacitor and a manufacturing method thereof, which can solve the problem that the MIM capacitor provided in the related art is prone to void defects, thereby reducing the reliability and yield of the product.
[0005] On the one hand, an embodiment of the present application provides a method for manufacturing a MIM capacitor, characterized by comprising:
[0006] forming a first metal connection in a first interlayer dielectric layer;
[0007] forming a second interlayer dielectric layer on the first interlayer dielectric layer;
[0008] A MIM capacitor is formed in the second interlayer dielectric layer, wherein the MIM capacitor includes a first electrode layer, a capacitor dielectric layer, and a second electrode layer in sequence from the outside to the inside, wherein the bottom of the first electrode layer contacts the top of the first metal connection line, and the contact area between the first electrode layer and the first metal connection line is smaller than the bottom area of the first electrode layer;
[0009] forming a third interlayer dielectric layer on the second interlayer dielectric layer;
[0010] forming a contact hole in the third interlayer dielectric layer, wherein a bottom of the contact hole contacts a top of the second electrode layer;
[0011] A second metal connection line is formed on the third interlayer dielectric layer, and a bottom of the second metal connection line contacts the top of the contact hole.
[0012] In some embodiments, forming a MIM capacitor in the second interlayer dielectric layer includes:
[0013] forming a trench in the second interlayer dielectric layer, wherein the first metal connection at the bottom of the trench is exposed;
[0014] forming a first electrode layer, a capacitor dielectric layer, and a second electrode layer in sequence to fill the groove;
[0015] A planarization process is performed to remove the first electrode layer, the capacitor dielectric layer and the second electrode layer outside the groove.
[0016] In some embodiments, the capacitor dielectric layer includes a silicon nitride layer and / or a silicon oxynitride layer.
[0017] In some embodiments, the first electrode layer includes.
[0018] In some embodiments, the second electrode layer includes sequentially from bottom to top.
[0019] In some embodiments, the second interlayer dielectric layer includes, from bottom to top, an NDC layer and a silicon dioxide layer.
[0020] In some embodiments, the first metal connection line and the contact hole are included in sequence from the outside to the inside.
[0021] On the other hand, an embodiment of the present application provides a metal interconnect structure including a MIM capacitor, including:
[0022] A first interlayer dielectric layer, wherein a first metal connection line is formed in the first interlayer dielectric layer;
[0023] a second interlayer dielectric layer, wherein a MIM capacitor is formed in the second interlayer dielectric layer, wherein the MIM capacitor includes, from outside to inside, a first electrode layer, a capacitor dielectric layer, and a second electrode layer, wherein the bottom of the first electrode layer contacts the top of the first metal connection, and a contact area between the first electrode layer and the first metal connection is smaller than an area of a bottom of the first electrode layer;
[0024] a third interlayer dielectric layer, wherein a contact hole is formed in the third interlayer dielectric layer, and a bottom of the contact hole contacts a top of the second electrode layer;
[0025] A second metal connection line is formed on the third interlayer dielectric layer, and a bottom of the second metal connection line contacts a top of the contact hole.
[0026] The technical solution of this application has at least the following advantages:
[0027] By making the contact area of the lower electrode layer of the MIM capacitor and the metal connection it contacts smaller than its bottom area in the metal interconnect structure, the probability of generating void defects in the lower electrode area is reduced, the breakdown failure rate of the MIM capacitor is reduced, and the reliability and yield of the product are improved to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0029] Figure 1 is a flow chart of a method for manufacturing a MIM capacitor provided by an exemplary embodiment of the present application;
[0030] Figures 2 to 4 is a schematic diagram of a manufacturing process of a MIM capacitor provided by an exemplary embodiment of the present application;
[0031] Figure 5 It is a schematic diagram of the layout of the MIM capacitor provided in the related art;
[0032] Figure 6 It is a schematic diagram of the layout of a MIM capacitor provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0033] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0034] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0035] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0036] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0037] refer to Figure 1 , which shows a flow chart of a method for manufacturing a MIM capacitor provided by an exemplary embodiment of the present application, such as Figure 1 As shown, the method includes:
[0038] Step S1, forming a first metal connection in a first interlayer dielectric layer.
[0039] refer to Figure 2 , which shows the formation of a first metal connection in the first interlayer dielectric layer. Figure 2 As shown, a first trench may be formed in the first interlayer dielectric (ILD) layer 211 by a photolithography process, and after forming the first metal layer, a planarization process (for example, a planarization process may be performed by a chemical mechanical polishing (CMP) process) is performed to remove the first metal layer outside the first trench, and the first metal layer in the first trench forms a first metal connection. The first metal connection may include at least one of a copper (Cu) metal layer, a tungsten (W) metal layer, and an aluminum (Al) metal layer. Figure 2 In the embodiment, the first metal connection line includes a barrier layer 2211 and a copper metal layer 2212 from the outside to the inside, the barrier layer 2211 may include a tantalum nitride (TaN) layer and / or a tantalum (Ta) layer, and the copper metal layer 2212 may include a copper layer. It should be noted that, Figure 2 Two first metal connections are used as an example for illustration, and in actual applications, the number can be set according to needs (for example, it can be one, two, three or more than three).
[0040] Step S2 , forming a second interlayer dielectric layer on the first interlayer dielectric layer.
[0041] Step S3, forming a MIM capacitor in the second interlayer dielectric layer, the MIM capacitor includes a first electrode layer, a capacitor dielectric layer and a second electrode layer from the outside to the inside, the bottom of the first electrode layer contacts the top of the first metal connection, and the contact area between the first electrode layer and the first metal connection is smaller than the bottom area of the first electrode layer.
[0042] refer to Figure 3 , which shows a cross-sectional schematic diagram after forming a MIM capacitor. Figure 3 As shown, the second interlayer dielectric layer includes, from bottom to top, a nitride doped silicon carbide (NDC) layer 220 (whose thickness is 100 angstroms) to 800 angstroms) and silicon dioxide (SiO 2 ) layer 212 (whose thickness is 1000 angstroms to 5000 angstroms), a second trench can be formed in the second interlayer dielectric layer by a photolithography process, and a first electrode layer 231, a capacitor dielectric layer 232 and a second electrode layer are formed in sequence, and a planarization process is performed to remove the first electrode layer 231, the capacitor dielectric layer 232 and the second electrode layer outside the second trench, and the first electrode layer 231, the capacitor dielectric layer 232 and the second electrode layer in the second trench form a MIM capacitor. Among them, the second electrode layer includes a first adhesion layer 2331 and a first metal layer 2332 from bottom to top, the first electrode layer 231 includes a tantalum nitride layer, and the capacitor dielectric layer 232 includes a silicon nitride (Si 3 N 4 ) layer and / or a silicon oxynitride (SiON) layer, the first adhesion layer 2331 includes a titanium nitride (TiN) layer, and the first metal layer 2332 includes a tungsten layer and / or a copper layer.
[0043] Step S4, forming a third interlayer dielectric layer on the second interlayer dielectric layer.
[0044] Step S5, forming a contact hole in the third interlayer dielectric layer, wherein the bottom of the contact hole contacts the top of the second electrode layer.
[0045] Step S6, forming a second metal connection on the third interlayer dielectric layer, wherein the bottom of the second metal connection contacts the top of the contact hole.
[0046] refer to Figure 4 , which shows a cross-sectional schematic diagram after forming the second metal connection. Figure 4As shown, a third interlayer dielectric layer 213 may be formed on the second interlayer dielectric layer, a through hole may be formed in the third interlayer dielectric layer 213 by a photolithography process, a second metal layer may be formed, a planarization process may be performed to remove the second metal layer outside the through hole, the second metal layer in the through hole may form a contact hole (via), a third metal layer may be formed on the third dielectric layer 213, the third metal layer in other areas outside the area where the second metal connection 223 is located may be removed by a photolithography process, and the remaining third metal layer may constitute the second metal connection 223. The contact hole may include at least one of a copper metal layer, a tungsten metal layer and an aluminum metal layer, Figure 4 In the embodiment, the contact hole includes a second adhesion layer 2221 and a second metal layer 2222 from outside to inside, the second metal connection line 223 includes at least one of a copper layer, a tungsten layer and an aluminum layer, and the second metal layer 2222 includes a tungsten layer and / or a copper layer. It should be noted that, Figure 4 Two contact holes are used as an example for illustration, and the number can be set according to needs in actual applications (for example, it can be three or more).
[0047] refer to Figure 5 , which shows the layout of the MIM capacitor provided in the related art, such as Figure 5 As shown, the top area of the metal layer 221 in contact with the first electrode layer (bottom electrode layer) 331 of the MIM capacitor is larger than the bottom area of the first electrode layer 331 , and the contact surface between the metal layer 221 and the first electrode layer 331 is the entire bottom surface of the first electrode layer 331 .
[0048] Correspondingly, Figure 6 It is a MIM capacitor designed after implementing the embodiment of the present application, such as Figure 6 As shown, the metal layer 421 in contact with the first electrode layer (bottom electrode layer) 431 of the MIM capacitor only contacts the bottom portion of the first electrode layer 431, thereby reducing the contact area between the bottom electrode layer and the metal layer in contact therewith (the contact area is smaller than the bottom area of the bottom electrode layer), thereby reducing the probability of generating void defects in the bottom electrode region. It should be noted that Figure 6 The layout design in the figure is only an example. In practical applications, it can also be designed that multiple column-shaped metal layers are in contact with the bottom electrode layer, or that a U-shaped metal layer is in contact with the bottom electrode, as long as it does not contact the entire bottom surface of the bottom electrode layer.
[0049] To sum up, in the embodiments of the present application, by making the contact area of the lower electrode layer of the MIM capacitor and the metal wire it contacts smaller than its bottom area in the metal interconnect structure, the probability of generating void defects in the lower electrode area is reduced, the breakdown failure rate of the MIM capacitor is reduced, and the reliability and yield of the product are improved to a certain extent.
[0050] refer to Figure 4, which shows a cross-sectional schematic diagram of a metal interconnect structure including a MIM capacitor provided by an exemplary embodiment of the present application, the structure can be manufactured by the above embodiment, and includes:
[0051] The first interlayer dielectric layer 211 has a first metal wiring formed therein.
[0052] The first metal connection line may include at least one of a copper layer, a tungsten layer and an aluminum layer. Figure 4 In the embodiment, the first metal connection line includes a barrier layer 2211 and a copper metal layer 2212 from the outside to the inside. It should be noted that: Figure 2 Two first metal lines are used as an example for illustration, and the number can be set according to needs in actual applications (for example, it can be three or more).
[0053] A second interlayer dielectric layer is formed with a MIM capacitor, which includes a first electrode layer 231, a capacitor dielectric layer 232 and a second electrode layer from the outside to the inside. The bottom of the first electrode layer 231 is in contact with the top of the first metal connection, and the contact area between the first electrode layer 231 and the first metal connection is smaller than the bottom area of the first electrode layer 231.
[0054] Among them, the second interlayer dielectric layer includes, from bottom to top, an NDC layer 220 (whose thickness is 100 angstroms to 800 angstroms) and a silicon dioxide layer 212 (whose thickness is 1000 angstroms to 5000 angstroms), the first electrode layer 231 includes a tantalum nitride layer, the capacitor dielectric layer 232 includes a silicon nitride layer and / or a silicon nitride oxide layer, and the second electrode layer includes, from bottom to top, a first adhesion layer 2331 and a first metal layer 2332, and the first metal layer 2332 includes a tungsten layer and / or a copper layer.
[0055] The third interlayer dielectric layer 213 has a contact hole formed therein, and the bottom of the contact hole contacts the top of the second electrode layer. The second metal wiring 223 includes at least one of a copper layer, a tungsten layer and an aluminum layer.
[0056] The contact hole may include at least one of a copper layer, a tungsten layer and an aluminum layer. Figure 4 In the embodiment, the contact hole includes a second adhesion layer 2221 and a second metal layer 2222 in sequence from outside to inside, and the second metal layer is at least one of a copper layer, a tungsten layer and an aluminum layer. It should be noted that: Figure 4 Two contact holes are used as an example for illustration, and the number can be set according to needs in actual applications (for example, it can be three or more).
[0057] The second metal connection line 223 is formed on the third interlayer dielectric layer 213, and the bottom of the second metal connection line 223 contacts the top of the contact hole. The second metal connection line 223 includes at least one of a copper layer, a tungsten layer and an aluminum layer.
[0058] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A method for manufacturing a MIM capacitor, characterized in that: include: forming a first metal connection in a first interlayer dielectric layer; forming a second interlayer dielectric layer on the first interlayer dielectric layer; A MIM capacitor is formed in the second interlayer dielectric layer, wherein the MIM capacitor includes a first electrode layer, a capacitor dielectric layer, and a second electrode layer in sequence from the outside to the inside, wherein the bottom of the first electrode layer contacts the top of the first metal connection line, and the contact area between the first electrode layer and the first metal connection line is smaller than the bottom area of the first electrode layer; forming a third interlayer dielectric layer on the second interlayer dielectric layer; forming a contact hole in the third interlayer dielectric layer, wherein a bottom of the contact hole contacts a top of the second electrode layer; A second metal connection line is formed on the third interlayer dielectric layer, and a bottom of the second metal connection line contacts the top of the contact hole.
2. The method according to claim 1, characterized in that: The forming of a MIM capacitor in the second interlayer dielectric layer comprises: forming a trench in the second interlayer dielectric layer, wherein the first metal connection at the bottom of the trench is exposed; forming a first electrode layer, a capacitor dielectric layer, and a second electrode layer in sequence to fill the groove; A planarization process is performed to remove the first electrode layer, the capacitor dielectric layer and the second electrode layer outside the groove.
3. The method according to claim 2, characterized in that The capacitor dielectric layer includes a silicon nitride layer and / or a silicon nitride oxide layer.
4. The method according to claim 3, characterized in that The first electrode layer includes.
5. The method according to claim 4, characterized in that The second electrode layer includes the following in order from bottom to top.
6. The method according to any one of claims 1 to 5, characterized in that: The second interlayer dielectric layer includes an NDC layer and a silicon dioxide layer in sequence from bottom to top.
7. The method according to claim 6, characterized in that The first metal connection line and the contact hole are included in sequence from the outside to the inside.
8. A metal interconnect structure comprising a MIM capacitor, characterized in that: include: A first interlayer dielectric layer, wherein a first metal connection line is formed in the first interlayer dielectric layer; a second interlayer dielectric layer, wherein a MIM capacitor is formed in the second interlayer dielectric layer, wherein the MIM capacitor includes, from outside to inside, a first electrode layer, a capacitor dielectric layer, and a second electrode layer, wherein the bottom of the first electrode layer contacts the top of the first metal connection, and a contact area between the first electrode layer and the first metal connection is smaller than an area of a bottom of the first electrode layer; a third interlayer dielectric layer, wherein a contact hole is formed in the third interlayer dielectric layer, and a bottom of the contact hole contacts a top of the second electrode layer; A second metal connection line is formed on the third interlayer dielectric layer, and a bottom of the second metal connection line contacts a top of the contact hole.