Multi-chip packaging structure and packaging method

Abstract

The invention provides a multi-chip packaging structure and packaging method, and the structure comprises a packaging substrate which is provided with a first conductive wire; the first chip is arranged on the packaging substrate, and the first chip is electrically connected with the packaging substrate through the first conductive wire; the TVC conversion plate is arranged on the first chip and is electrically connected with the first chip, and a vertically-through TVC conductive through hole is formed in the position, close to the edge, of the TVC conversion plate; the upper surface of the TVC conversion plate is coated with the BCB dielectric film; the second chip is arranged above the BCB dielectric film and is electrically connected with the TVC conversion plate; the third chip is arranged above the second chip and is electrically connected with the second chip; according to the invention, the transmission loss and time delay can be reduced, and the integrity of signal transmission is ensured; and the heat dissipation effect of the multi-chip packaging body is effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a multi-chip packaging structure and a packaging method. Background Art

[0002] A multi-chip package structure refers to a package that contains at least two chips (the types of chips are not limited and can be arbitrarily matched). It is widely used in various electronic devices, such as mobile phones, tablet computers, laptops, etc.; the multi-chip package structure plays an important role in modern electronic devices and continues to develop with the continuous advancement of technology.

[0003] After searching, a Chinese patent with announcement number CN117766501A discloses a multi-chip packaging structure and a packaging method thereof. The multi-chip packaging structure includes a lead frame, a first chip, a second chip and a filling material. The lead frame includes a chip carrier and lead pins. The first chip is flipped and arranged on the chip carrier, and the first chip is electrically connected to the lead pins. The second chip is upright and arranged on top of the first chip, and the second chip is electrically connected to the lead pins. The filling material is filled between the first chip and the lead frame.

[0004] The multi-chip packaging structure and packaging method of the above patent reduce costs, improve versatility, and achieve high density. However, the above multi-chip packaging is relatively difficult, and there must be enough area and space to realize the mounting and wire bonding of the stacked chips; and the heat dissipation efficiency of the multi-chip packaging structure is not high. During long-term use, the chip is easily damaged by the temperature, which seriously shortens the service life of the chip.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The purpose of the present invention is to provide a multi-chip packaging structure and a packaging method, aiming to solve the technical problem in the prior art that "multi-chip packaging is relatively difficult and the heat dissipation efficiency is low".

[0007] To achieve the above object, an embodiment of the present invention provides a multi-chip packaging structure, the multi-chip packaging structure comprising: A packaging substrate, on which a first conductive line is arranged; a first chip, wherein the first chip is disposed on the packaging substrate, and the first chip is electrically connected to the packaging substrate through the first conductive wire; A TVC conversion board, the TVC conversion board is arranged on the first chip and is electrically connected to the first chip, and the TVC conversion board is provided with a vertically penetrating TVC conductive through hole near an edge position; A BCB dielectric film, the BCB dielectric film is coated on the upper surface of the TVC conversion plate; a second chip, the second chip being disposed above the BCB dielectric film and electrically connected to the TVC conversion board; The third chip is disposed above the second chip and is electrically connected to the second chip.

[0008] Optionally, an RDL rewiring layer is formed on the top surface of the TVC conversion plate, the BCB dielectric film is coated on the upper surface of the RDL rewiring layer, and the RDL rewiring layer is electrically connected to the TVC conductive via.

[0009] Optionally, a conductive connector is disposed in the TVC conductive through hole, a second conductive wire is connected to the conductive connector, and the second conductive wire is electrically connected to the packaging substrate through the conductive connector.

[0010] Optionally, a third conductive wire and a fourth conductive wire are further connected to the upper surface of the conductive connection member, the second chip is electrically connected to the conductive connection member via the third conductive wire, and the third chip is electrically connected to the conductive connection member via the fourth conductive wire.

[0011] Optionally, the conductive connecting member is flush with or exposed on the TVC conversion board, and a cross section of the conductive connecting member is a T-shaped structure.

[0012] Optionally, the first chip is flip-chip mounted on the packaging substrate, and a filling material for fixing the TVC conversion board is provided between the first chip and the TVC conversion board.

[0013] Optionally, the multi-chip packaging structure further includes: A plastic encapsulation layer is disposed above the packaging substrate and is used to plastic encapsulate the first chip, the TVC conversion board, the second chip and the third chip.

[0014] The embodiment of the present invention further provides a multi-chip packaging method, which includes the following steps: S10: providing a packaging substrate, which has an upper surface of the packaging substrate and a lower surface of the packaging substrate that are arranged opposite to each other, and a first conductive line is arranged on the packaging substrate; S20: flipping the first chip onto the upper surface of the packaging substrate, and connecting the first chip to the first conductive wire to achieve electrical connection with the packaging substrate; S30: vertically penetrating TVC conductive through holes are opened at two sides of the TVC conversion board near the edge, and the TVC conversion board is mounted on the side of the first chip away from the packaging substrate, and conductive connectors are filled in the TVC conductive through holes; S40: forming an RDL rewiring layer on the surface of the TVC conversion board by patterned electroplating, wherein the RDL rewiring layer is electrically connected to the TVC conductive through hole; S50: coating a BCB film on the surface of the RDL redistribution layer, and completely curing it in a high-temperature nitrogen atmosphere; S60: installing a second chip on the TVC conversion board, wherein the second chip is electrically connected to the conductive connection member through a third conductive line; S70: installing a third chip on the second chip, wherein the third chip is electrically connected to the conductive connecting member via a fourth conductive line; S80: performing plastic encapsulation on two opposite sides of the packaging substrate to form a plastic encapsulation layer covering the first chip, the TVC conversion board, the second chip and the third chip.

[0015] Optionally, in S20, flipping the first chip onto the upper surface of the packaging substrate includes: Coating an adhesive layer on the bonding surface of the first chip; The first chip is attached to the upper surface of the packaging substrate through the adhesive layer.

[0016] Optionally, in S30 , a filling material is filled in a gap between the first chip and the TVC conversion plate, and the filling material is heated and cured to fix the TVC conversion plate to the upper surface of the first chip.

[0017] The above one or more technical solutions in the multi-chip packaging structure and packaging method provided by the embodiments of the present invention have at least one of the following technical effects: The multi-chip packaging structure and packaging method provided by the present invention, the TVC conversion board can be interconnected with the packaging substrate, and can also shorten the distance of the wiring interconnection between the first chip, the second chip and the third chip, reduce the transmission loss and delay, and ensure the integrity of signal transmission; and make the first chip, the second chip and the third chip on planes at different heights, thereby realizing three-dimensional packaging between multiple chips; and the surface of the TVC conversion board is coated with a BCB dielectric film, and the BCB dielectric film can effectively improve the heat dissipation effect of the multi-chip package. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0019] Figure 1 A schematic diagram of a multi-chip packaging structure provided by an embodiment of the present invention; Figure 2 One of the assembly schematic diagrams of the multi-chip package structure provided by an embodiment of the present invention; Figure 3 A second assembly schematic diagram of a multi-chip package structure provided by an embodiment of the present invention; Figure 4 A schematic flow chart of a multi-chip packaging method provided by an embodiment of the present invention.

[0020] Among them, the reference numerals in the figure are: 10. packaging substrate; 11. first conductive line; 20. First chip; 30. TVC conversion board; 31. TVC conductive via; 32. RDL redistribution layer; 33. conductive connector; 330. second conductive wire; 331. third conductive wire; 332. fourth conductive wire; 40. BCB dielectric film; 50. Second chip; 60. The third chip; 70. Filling materials; 80. Plastic sealing layer. DETAILED DESCRIPTION

[0021] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the embodiments of the present invention, and should not be construed as limiting the present invention.

[0022] In the description of the embodiments of the present invention, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0023] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0024] In the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0025] In one embodiment of the present invention, Figure 1-Figure 3 As shown, a multi-chip packaging structure is provided, which includes a packaging substrate 10 , a first chip 20 , a TVC conversion plate 30 , a BCB dielectric film 40 , a second chip 50 and a third chip 60 .

[0026] Specifically, the packaging substrate 10 of the present invention has an upper surface of the packaging substrate 10 and a lower surface of the packaging substrate 10 that are arranged opposite to each other, and a first conductive line 11 is arranged on the packaging substrate 10. In the embodiment of the present invention, the packaging substrate 10 can be an organic substrate, an inorganic substrate, a ceramic substrate, a circuit board, a carrier board, or a metal substrate, but is not limited thereto, and the present invention does not make any specific limitation.

[0027] Specifically, the first chip 20 is disposed on the packaging substrate 10, and the first chip 20 is electrically connected to the packaging substrate 10 through the first conductive wire 11. In one embodiment of the present invention, the electrical connection method between the first chip 20 and the packaging substrate 10 is not limited to connection through the first conductive wire 11. Of course, in another embodiment of the present invention, the first chip 20 and the packaging substrate 10 can also be electrically connected by wire bonding. In addition, in other embodiments of the present invention, the first chip 20 can also be fixed to the packaging substrate 10 using a die attach film (DAF).

[0028] Specifically, the TVC conversion board 30 is disposed on the first chip 20 and is electrically connected to the first chip 20. A vertically penetrating TVC conductive through hole 31 is disposed near the edge of the TVC conversion board 30. In the present invention, the TVC conversion board 30 is a ceramic conversion board, and the TVC conductive through hole 31 can be laser punched or punched by a precision machine tool on the TVC conversion board 30. The TVC conductive through hole 31 can realize the stacking of each chip while achieving a higher integration and a smaller size, so that the stacking wiring of the chip is denser, can withstand high-power use requirements, and meet production needs.

[0029] Specifically, the BCB dielectric film 40 is coated on the upper surface of the TVC conversion plate 30. By coating the BCB dielectric film 40 on the upper surface of the TVC conversion plate 30, the BCB thin film made by using the low-dielectric BCB dielectric film 40 can significantly reduce signal delay, reduce signal transmission loss, and ensure the integrity of signal transmission.

[0030] Specifically, the second chip 50 is disposed above the BCB dielectric film 40 and is electrically connected to the TVC conversion board 30. The second chip 50 is electrically connected to the conductive connector 33 through the third conductive wire 331. By disposing the conductive connector 33, vertical interconnection between the second chip 50 and the package substrate 10 can be achieved, thereby shortening the connection path.

[0031] Specifically, the third chip 60 is disposed above the second chip 50 and is electrically connected to the second chip 50. The third chip 60 is electrically connected to the conductive connection member 33 through the fourth conductive line 332. By disposing the conductive connection member 33, vertical interconnection between the third chip 60 and the packaging substrate 10 can be achieved, thereby shortening the connection path.

[0032] In the multi-chip packaging structure provided by the present invention, the TVC conversion board 30 can be interconnected with the packaging substrate 10, and can also shorten the distance of the wiring interconnection between the first chip 20, the second chip 50 and the third chip 60, thereby reducing transmission loss and delay, and ensuring the integrity of signal transmission; and the first chip 20, the second chip 50 and the third chip 60 are located on planes at different heights, thereby realizing three-dimensional packaging between multiple chips; and the surface of the TVC conversion board 30 is coated with a BCB dielectric film 40, and the BCB dielectric film 40 can effectively improve the heat dissipation effect of the multi-chip package.

[0033] It should be noted that the multi-chip packaging structure provided by the present invention is a three-layer chip. In other embodiments, the multi-chip packaging structure may also be a chip with four or five layers. In a multi-chip packaging structure with three layers of chips, the multi-chip packaging structure includes at least three chips. In this embodiment, three chips are provided. In other embodiments, four chips or five chips may be provided. The combination of the number of chips of each chip may also be adjusted according to production requirements.

[0034] In an embodiment of the present invention, an RDL rewiring layer 32 is formed on the top surface of the TVC conversion board, the BCB dielectric film 40 is coated on the upper surface of the RDL rewiring layer 32, and the RDL rewiring layer 32 is electrically connected to the TVC conductive via 31. By forming the RDL rewiring layer 32 on the top surface of the TVC conversion board 30, signal transmission can be achieved between the TVC conversion board 30 and the second chip 50. In the present invention, the RDL rewiring layer 32 can be implemented by polymide, or copper interconnection can be implemented by Damascus process, or aluminum interconnection can be used. The above materials can reduce the cost of the product and have strong power supply capacity. In a specific embodiment of the present invention, the RDL rewiring layer 32 can be a single layer or multiple layers.

[0035] Furthermore, a conductive connector 33 is provided in the TVC conductive through hole 31, and a second conductive wire 330 is connected to the conductive connector 33, and the second conductive wire 330 is electrically connected to the package substrate 10 through the conductive connector 33. The conductive connector 33 can realize the connection between chips, and the connection method of wire bonding can be avoided. The conductive connector 33 can shorten the transmission length and the length of the heat conduction path between the first chip 20, the second chip 50 and the third chip 60, reduce the signal transmission delay, effectively reduce the parasitic inductance and resistance of the product, and reduce the adverse effects on high-speed signal transmission and timing. In addition, the present embodiment also uses the setting of the conductive connector 33 to improve the heat dissipation capacity of the multi-chip package. In the embodiment of the present invention, the conductive connector 33 is made of, for example, gold, silver, tin, copper or other alloy materials, but is not limited thereto.

[0036] Furthermore, the upper surface of the conductive connection member 33 is also connected with a third conductive line 331 and a fourth conductive line 332, the second chip 50 is electrically connected to the conductive connection member 33 through the third conductive line 331, and the third chip 60 is electrically connected to the conductive connection member 33 through the fourth conductive line 332. In this embodiment, the second chip 50 is electrically connected to the third conductive line 331, and the third chip 60 is electrically connected to the fourth conductive line 332 through the conductive connection member 33, so that high-density connection can be achieved, signal transmission speed can be increased, signal attenuation can be reduced, and the performance of the multi-chip packaging structure can be improved.

[0037] In an embodiment of the present invention, the conductive connector 33 is exposed on the TVC conversion plate 30, and the cross-section of the conductive connector 33 is a T-shaped structure. Of course, in other embodiments of the present invention, the conductive connector 33 may be flush with the TVC conversion plate 30. No specific limitation is made unless otherwise disclosed. The exposed arrangement of the conductive connector 33 in this application is only a distance and does not represent a limitation. That is, the conductive connector 33 may not be exposed on the TVC conversion plate 30, and other connection structures may be used. The specific connection structure is set by those skilled in the art, and this application does not make any specific limitation, as long as it can meet the requirements of this application.

[0038] Furthermore, a filling material 70 for fixing the TVC conversion board 30 is provided between the first chip 20 and the TVC conversion board 30. By providing the filling material 70 between the first chip 20 and the TVC conversion board 30, the TVC conversion board 30 is fixed to the first chip 20.

[0039] In actual application, the TVC conversion board 30 is placed on the first chip 20. Since there is a gap between the first chip 20 and the TVC conversion board 30, a filling material 70 is injected between the gap between the first chip 20 and the TVC conversion board 30, so that the TVC conversion board 30 is fixed on the first chip 20.

[0040] Furthermore, the multi-chip packaging structure further includes: The plastic encapsulation layer 80 is disposed above the packaging substrate 10 and is used to plastic encapsulate the first chip 20, the TVC conversion board 30, the second chip 50, and the third chip 60. In this embodiment, the plastic encapsulation layer 80 is made of epoxy resin. In other embodiments, the plastic encapsulation layer 80 may also be made of phenolic resin. In this embodiment, the plastic encapsulation layer 80 includes a plastic encapsulation insulating layer. In other embodiments, the plastic encapsulation layer 80 may also be set to two layers of the plastic encapsulation layer 80 or three layers of the plastic encapsulation layer 80, that is, the plastic encapsulation layer 80 may be completed by multiple plastic encapsulations.

[0041] In another embodiment, when the plastic encapsulation layer 80 is set to be multi-layer, the chip model can be distinguished by setting the multi-layer plastic encapsulation material. For example, the first layer is epoxy resin and the second layer is polyimide, and this setting is the first chip model; if the first layer is epoxy resin and the second layer is polyamide resin, this setting is the second chip model. That is, the chip model is set by pre-setting different layers of plastic encapsulation layers 80 corresponding to different materials. This setting requires chip model identification when the chip is damaged, and is suitable for use in scenarios where chip models have to be distinguished and there is no other way to distinguish.

[0042] In another embodiment of the present invention, Figure 4 As shown, a multi-chip packaging method is also provided, and the multi-chip packaging method comprises the following steps: S10: providing a packaging substrate 10, which has an upper surface of the packaging substrate 10 and a lower surface of the packaging substrate 10 that are arranged opposite to each other, and a first conductive line 11 is arranged on the packaging substrate 10; S20 : ​​flipping the first chip 20 onto the upper surface of the packaging substrate 10 , and connecting the first chip 20 to the first conductive wire 11 to achieve electrical connection with the packaging substrate 10 .

[0043] Specifically, the first chip 20 of the present invention can be connected to the packaging substrate 10 not only through the first conductive wire 11. The first chip 20 can also be electrically connected to the packaging substrate 10 by wire bonding. In addition, the first chip 20 can be fixed to the packaging substrate 10 by using a die attach film (DAF), and the first chip 20 can be electrically connected to the packaging substrate 10 by connecting the first conductive wire 11.

[0044] S30: vertically penetrating TVC conductive through holes 31 are opened at both sides of the TVC conversion board 30 near the edge, and the TVC conversion board 30 is mounted on the side of the first chip 20 away from the packaging substrate 10, and conductive connectors 33 are filled in the TVC conductive through holes 31; S40 : forming an RDL rewiring layer 32 on the surface of the TVC conversion plate 30 by patterned electroplating, wherein the RDL rewiring layer 32 is electrically connected to the TVC conductive via 31 .

[0045] Specifically, by forming the RDL rewiring layer 32 on the top surface of the TVC conversion board, the RDL rewiring layer 32 is electrically connected to the TVC conductive via 31 so that signal transmission can be achieved between the TVC conversion board 30 and the second chip 50 .

[0046] S50: Coat a BCB film on the surface of the RDL rewiring layer 32 and completely cure it in a high-temperature nitrogen atmosphere. The present invention utilizes the BCB photosensitive property to make a BCB dielectric film, and again uses a thin film deposition process to make a top film. The BCB film made using the low-dielectric BCB dielectric film 40 can significantly reduce signal delay, reduce signal transmission loss, and ensure the integrity of signal transmission; and the BCB dielectric film 40 can effectively improve the heat dissipation effect of the multi-chip package.

[0047] S60: The second chip 50 is mounted on the TVC conversion board 30, and the second chip 50 is electrically connected to the conductive connection member 33 through the third conductive wire 331. Through the arrangement of the conductive connection member 33, the second chip 50 and the package substrate 10 can be vertically interconnected, thereby shortening the connection path.

[0048] S70: Mounting a third chip 60 on the second chip 50, the third chip 60 is electrically connected to the conductive connection member 33 via a fourth conductive line 332. The provision of the conductive connection member 33 enables vertical interconnection between the third chip 60 and the package substrate 10, thereby shortening the connection path.

[0049] S80 : performing plastic encapsulation on two opposite sides of the packaging substrate 10 to form a plastic encapsulation layer 80 covering the first chip 20 , the TVC conversion board 30 , the second chip 50 and the third chip 60 .

[0050] Furthermore, in S20, flipping the first chip 20 onto the upper surface of the packaging substrate 10 includes: Coating an adhesive layer on the bonding surface of the first chip 20; The first chip 20 is bonded to the upper surface of the packaging substrate 10 through the adhesive layer.

[0051] Furthermore, in S30 , a filling material 70 is filled in the gap between the first chip 20 and the TVC conversion plate 30 , and the filling material 70 is heated and cured to fix the TVC conversion plate 30 on the upper surface of the first chip 20 .

[0052] In summary, in the multi-chip packaging structure and packaging method provided by the present invention, the TVC conversion board 30 can be interconnected with the packaging substrate 10, and can also shorten the distance of the wiring interconnection between the first chip 20, the second chip 50 and the third chip 60, thereby reducing transmission loss and delay, and ensuring the integrity of signal transmission; and the first chip 20, the second chip 50 and the third chip 60 are located on planes at different heights, thereby realizing three-dimensional packaging between multiple chips; and the surface of the TVC conversion board 30 is coated with a BCB dielectric film 40, and the BCB dielectric film 40 can effectively improve the heat dissipation effect of the multi-chip package.

[0053] In another embodiment of the present invention, in S80, the step of performing plastic sealing on two opposite sides of the packaging substrate includes: performing plastic sealing on two opposite sides of the packaging substrate according to a preset weight of plastic sealing material by a preset plastic sealing control device.

[0054] Specifically, the preset weight is pre-set by a person skilled in the art, and the packaging is performed by setting the preset weight, the purpose of which is to achieve the same weight of each of the multi-chip packaging structures after plastic packaging. In addition, after plastic packaging, the weight of each of the multi-chip packaging structures is measured. If the weight is inconsistent, the plastic packaging layer 80 is polished until the weight of each of the multi-chip packaging structures is the same. At this time, when the structure of each of the multi-chip packaging structures is the same, the preset packaging box is used to assemble the preset number of multi-chip packaging structures according to the preset number to form a chipset. Among them, the weight of the preset packaging box is also constant, and the number of multi-chip packaging structures in one of the preset packaging boxes is also pre-set and fixed, that is, the preset number, so that the weight of one of the chipset is determined. Therefore, the chip types in the chipset are distinguished by the difference in weight, that is, this application scenario is suitable for chips that need to be kept confidential, and is used in scenarios where the chip model cannot be etched on the multi-chip packaging structure. When the chip model is no longer marked, the manufacturing entity distinguishes the chip model by weight, that is, a chipset of one weight corresponds to one chip type, which satisfies the confidentiality of the multi-chip packaging structure while enabling the type to be distinguished.

[0055] Based on the above structural design, there are two methods for distinguishing chip types, as follows: The first method is to distinguish by weighing a single chip. This method is suitable for weighing a relatively sophisticated weighing device, which is relatively limited. Therefore, there is a second method of distinguishing by weighing the chipset. The advantage of this method is that it is not limited to relatively sophisticated weighing devices.

[0056] Of course, not marking the chip model will have some impact on the entity that uses the chip later, so the entity that uses the chipset later needs to be able to save different chips in a preset location, and can distinguish them by weighing the chipset before use. Of course, other methods can also be used to ensure that there is no confusion during use. The purpose of this is to avoid confusion during use by not marking the chip model, but after being applied to a specific product and disassembled by other production entities, other production entities cannot distinguish the chip model, thereby achieving the purpose of chip confidentiality. In this way, the confidentiality of the chip model can be achieved at a lower cost. Even if 100% confidentiality is not possible, low-cost confidentiality is achieved.

[0057] In this embodiment, the weights of other structures of the multi-chip packaging structure are limited to be the same, but slight deviations may occur in actual production, so it is necessary to compensate for the weight through the above-mentioned step of "if the weights are inconsistent, polishing the plastic layer 80 until the weights of each of the multi-chip packaging structures are the same".

[0058] In another embodiment, in step S80, after the step of plastic sealing on the opposite sides of the package substrate, the following steps are further included: by etching a marking code on the plastic sealing layer 80, the composition of the identification code is "first marking code-second marking code-third marking code"; wherein the first marking code is a production time mark, specifically the production year, marked with numbers from 1 to 100, wherein 1 represents production in 2001, 2 represents production in 2002, and so on. Among them, 2001 is not the year of establishment of the company or the year of output of the company's production line, but a randomly customized starting year. Considering that it is generally speculated that the starting year is a special time node such as the year of output of the production line or the year of establishment of the company, the starting year is randomly set to play a role in confidentiality. The second marking code is a chip model, marked with numbers from 01 to 99, 01 represents a chip model, 02 represents another chip model, and so on to 99. The corresponding chip model is customized, and the manufacturer can know the specific chip model by querying the pre-set corresponding relationship. The third marking code is used to indicate the person in charge of production, and is replaced by English characters, such as AZ corresponding to different persons in charge of production. The specific correspondence is also preset and stored internally by the production entity. Therefore, the chip model is different from the prior art in the chip model marking and confidentiality is achieved through the setting of "first marking code-second marking code-third marking code".

[0059] Furthermore, when it is necessary to identify the model and other information of the chip, the external image of the plastic layer 80 is obtained, and then the identification code on the external image is identified, specifically, the first marking code-the second marking code-the third marking code is identified, and then the first marking code-the second marking code-the third marking code is parsed according to pre-stored data to obtain the specific information of the chip.

[0060] In another embodiment, The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-chip packaging structure, characterized in that: The multi-chip package structure includes: A packaging substrate, on which a first conductive line is arranged; a first chip, wherein the first chip is disposed on the packaging substrate, and the first chip is electrically connected to the packaging substrate through the first conductive wire; A TVC conversion board, the TVC conversion board is arranged on the first chip and is electrically connected to the first chip, and the TVC conversion board is provided with a vertically penetrating TVC conductive through hole near an edge position; A BCB dielectric film, the BCB dielectric film is coated on the upper surface of the TVC conversion plate; a second chip, the second chip being disposed above the BCB dielectric film and electrically connected to the TVC conversion board; The third chip is disposed above the second chip and is electrically connected to the second chip.

2. The multi-chip package structure according to claim 1, characterized in that: An RDL rewiring layer is formed on the top surface of the TVC conversion plate, the BCB dielectric film is coated on the upper surface of the RDL rewiring layer, and the RDL rewiring layer is electrically connected to the TVC conductive through hole.

3. The multi-chip package structure according to claim 2, characterized in that: A conductive connector is disposed in the TVC conductive through hole, a second conductive line is connected to the conductive connector, and the second conductive line is electrically connected to the packaging substrate through the conductive connector.

4. The multi-chip package structure according to claim 3, characterized in that: The upper surface of the conductive connection member is also connected with a third conductive line and a fourth conductive line, the second chip is electrically connected to the conductive connection member through the third conductive line, and the third chip is electrically connected to the conductive connection member through the fourth conductive line.

5. The multi-chip package structure according to claim 4, characterized in that: The conductive connecting member is flush with or exposed on the TVC conversion board, and the cross section of the conductive connecting member is a T-shaped structure.

6. The multi-chip package structure according to any one of claims 1 to 5, characterized in that: The first chip is flip-mounted on the packaging substrate, and a filling material for fixing the TVC conversion board is arranged between the first chip and the TVC conversion board.

7. The multi-chip package structure according to any one of claims 1 to 5, characterized in that: The multi-chip package structure also includes: A plastic encapsulation layer is disposed above the packaging substrate and is used to plastic encapsulate the first chip, the TVC conversion board, the second chip and the third chip.

8. The packaging method of a multi-chip packaging structure according to any one of claims 1 to 7, characterized in that: The multi-chip packaging method comprises the following steps: S10: providing a packaging substrate, which has an upper surface of the packaging substrate and a lower surface of the packaging substrate that are arranged opposite to each other, and a first conductive line is arranged on the packaging substrate; S20: flipping the first chip onto the upper surface of the packaging substrate, and connecting the first chip to the first conductive wire to achieve electrical connection with the packaging substrate; S30: vertically penetrating TVC conductive through holes are provided at two sides of the TVC conversion board near the edge, and the TVC conversion board is mounted on the side of the first chip away from the packaging substrate, and conductive connectors are filled in the TVC conductive through holes; S40: forming an RDL rewiring layer on the surface of the TVC conversion board by patterned electroplating, wherein the RDL rewiring layer is electrically connected to the TVC conductive through hole; S50: coating a BCB film on the surface of the RDL redistribution layer, and completely curing it in a high-temperature nitrogen atmosphere; S60: installing a second chip on the TVC conversion board, wherein the second chip is electrically connected to the conductive connection member through a third conductive line; S70: installing a third chip on the second chip, wherein the third chip is electrically connected to the conductive connection member via a fourth conductive line; S80: performing plastic encapsulation on two opposite sides of the packaging substrate to form a plastic encapsulation layer covering the first chip, the TVC conversion board, the second chip and the third chip.

9. The multi-chip packaging method according to claim 8, characterized in that: In S20, flipping the first chip onto the upper surface of the packaging substrate includes: coating an adhesive layer on the bonding surface of the first chip; The first chip is attached to the upper surface of the packaging substrate through the adhesive layer.

10. The multi-chip packaging method according to claim 8, characterized in that: In the step S30 , a filling material is filled in the gap between the first chip and the TVC conversion plate, and the filling material is heated and cured to fix the TVC conversion plate to the upper surface of the first chip.

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