Half-bridge drive control circuit

Abstract

The invention provides a half-bridge driving control circuit. The half-bridge driving control circuit comprises a high-side power tube, a low-side power tube, a logic module, a high-side power tube driving module, a high-side power tube turn-off module and a low-side power tube driving module, the logic module is used for converting a PWM input signal into a high-side power tube control signal and a low-side power tube control signal; the high-side power tube driving module controls the conduction of a high-side power tube according to an input high-side power tube control signal; the high-side power tube turn-off module controls the turn-off of a high-side power tube according to an input high-side power tube control signal; the low-side power tube driving module controls the on and off of a low-side power tube according to an input low-side power tube control signal; the high-side power tube control signal and the low-side power tube control signal are opposite in level at the same moment; when the high-side power tube is switched on, the low-side power tube is switched off, and when the high-side power tube is switched off, the low-side power tube is switched on.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a half-bridge drive control circuit. Background Art

[0002] DC motors are small in size, have high torque, and high speed, making them widely used, from mobile phone pop-up cameras, toy cars, and sweeping robots to cars, factory automation robots, and CNC machinery. In particular, with the popularization of automotive electronic control in recent years, H-bridge driver chips have been increasingly used in automobiles. Since automotive chips have extremely high requirements for input voltage range and electromagnetic radiation characteristics, the difficulty of designing automotive full-bridge driver chips has increased.

[0003] Full-bridge motor power stage driver Figure 1 As shown, it is composed of two half-bridge circuits, Q1+Q2 and Q3+Q4, respectively. Among them, Q1 / Q3 is a high-side drive power tube, and Q2 / Q4 is a low-side drive power tube.

[0004] Existing high-voltage automotive half-bridge drive circuits are as follows: Figure 2 As shown in the figure, HSMN and LSMN are the high-side and low-side power tubes of the half-bridge circuit respectively, inverters INV1, INV2, and gates NAND2, NAND3 form the logic control module of the half-bridge drive, and the function of the Level shift module is to convert the logic signal of the low-voltage VDD-GND domain into the logic signal of the VBST-OUT high-voltage domain. When PWM_IN=0, EN_LS_ON=1, EN_HS_ON=0, the high-side power tube HSMN is turned off, the low-side power tube LSMN is turned on, and the OUT terminal is pulled down to a low level. At this time, the voltage VDD charges the off-chip bootstrap capacitor CBST through the on-chip diode D1, so that VBST-OUT≈VDD. When PWM_IN=1, EN_HS_ON=1, EN_LS_ON=0, the high-side power tube HSMN is turned on, the low-side power tube LSMN is turned off, and the OUT terminal is pulled up to the voltage VIN. At this time, the diode D1 is cut off, and the voltage of the external bootstrap capacitor CBST cannot change suddenly, so that the high-side power tube HSMN is turned on, VBST≈VDD+ OUT, and the high-voltage domain power driver module is powered.

[0005] From the above analysis, the existing half-bridge drive circuit has two problems in automotive applications: 1. The EMI characteristics are poor, and it is impossible to optimize the EMI characteristics by adjusting the upper tube turn-on speed; 2. This drive circuit requires an off-chip self-capacitor CBST, which undoubtedly increases the system application cost and further deteriorates the EMI characteristics.

[0006] Therefore, how to improve the electromagnetic radiation characteristics and save the overall system cost is a problem that needs to be solved at present. Summary of the invention

[0007] The purpose of the present invention is to provide a half-bridge drive control circuit, which can improve electromagnetic radiation characteristics and save overall system cost.

[0008] In order to achieve the above object, the present invention provides a half-bridge drive control circuit, comprising: High-side power tube, low-side power tube, logic module, high-side power tube driver module, high-side power tube shutdown module and low-side power tube driver module; The logic module is used to convert the PWM input signal into a high-side power tube control signal and a low-side power tube control signal; The high-side power tube driving module controls the high-side power tube to be turned on according to the input high-side power tube control signal; The high-side power tube shutdown module controls the high-side power tube to shut down according to the input high-side power tube control signal; The low-side power tube driving module controls the low-side power tube to be turned on and off according to the input low-side power tube control signal; The high-side power tube control signal and the low-side power tube control signal are at opposite levels at the same time; when the high-side power tube is turned on, the low-side power tube is turned off, and when the high-side power tube is turned off, the low-side power tube is turned on; The input signal of the high-side power tube driving module also includes: a clock signal and an output signal of the half-bridge driving control circuit, and the high-side power tube driving module outputs a high-side power tube voltage driving signal; When the high-side power tube control signal changes from a low level to a high level, the high-side power tube driving module starts to work, and under the control of the clock signal, the output high-side power tube voltage driving signal is gradually increased, thereby controlling the high-side power tube to be turned on, and the low-side power tube to be turned off; When the high-side power tube control signal changes from a high level to a low level, the high-side power tube shutdown module pulls down the high-side power tube voltage drive signal to shut down the high-side power tube, while turning on the low-side power tube.

[0009] In an optional solution, the input signal of the high-side power tube driving module includes a slope adjustment signal, and the slope adjustment signal is used to adjust the voltage increase speed of the driving signal.

[0010] In an optional solution, the high-side power tube driving module includes: a first NAND gate, a second NAND gate, a third NAND gate, a first inverter, a second inverter, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first capacitor, and a second capacitor; One input end of the first NAND gate is used to input the high-side power tube control signal, the other input end is used to input the clock signal, and the output end is connected to the input end of the first inverter; the output end of the first inverter is connected to the input end of the second inverter and one input end of the second NAND gate; the other input end of the second NAND gate is connected to the output end of the third NAND gate; the output end of the second inverter is connected to one input end of the third NAND gate, and the other input end of the third NAND gate is connected to the output end of the second NAND gate; The output end of the second NAND gate is connected to the gate of the first NMOS tube and the gate of the first PMOS tube; the source of the first PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the first NMOS tube and one end of the first capacitor; the source of the first NMOS tube is grounded through the first resistor, connected to the drain of the fourth NMOS tube through the second resistor, connected to the drain of the third NMOS tube through the third resistor, and connected to the drain of the second NMOS tube through the fourth resistor; the sources of the second NMOS tube, the third NMOS tube, and the fourth NMOS tube are all grounded; the gates of the second NMOS tube, the third NMOS tube, and the fourth NMOS tube are used to input the slope adjustment signal; The output end of the third NAND gate is connected to the gate of the fifth NMOS tube and the gate of the second PMOS tube; the source of the second PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the fifth NMOS tube and one end of the second capacitor; the source of the fifth NMOS tube is grounded through the fifth resistor, connected to the drain of the sixth NMOS tube through the sixth resistor, connected to the drain of the seventh NMOS tube through the seventh resistor, and connected to the drain of the eighth NMOS tube through the eighth resistor; the sources of the sixth NMOS tube, the seventh NMOS tube, and the eighth NMOS tube are all grounded; the gate of the sixth NMOS tube is connected to the gate of the fourth NMOS tube; the gate of the seventh NMOS tube is connected to the gate of the third NMOS tube; the gate of the eighth NMOS tube is connected to the gate of the second NMOS tube; The other end of the first capacitor is connected to the gate of the third PMOS tube, the gate of the ninth NMOS tube, the drain of the fourth PMOS tube and the drain of the tenth NMOS tube; the source of the ninth NMOS tube and the source of the tenth NMOS tube are connected to the high-side power tube shutdown module and serve as the output end of the half-bridge drive control circuit; the drain of the ninth NMOS tube is connected to the gate of the third PMOS tube, the gate of the fourth PMOS tube, the gate of the tenth NMOS tube and the other end of the second capacitor; the source of the third PMOS tube and the source of the fourth PMOS tube are connected to the gate of the high-side power tube and output the drive signal of the high-side power tube.

[0011] In an optional solution, the high-side power tube driver module further includes a first buffer and a second buffer; The first buffer is connected between the output end of the second NAND gate and the gate of the first PMOS tube; The second buffer is connected between the output end of the third NAND gate and the gate of the second PMOS tube.

[0012] In an optional solution, the logic module includes: a fourth inverter, a fifth inverter, a fourth NAND gate and a fifth NAND gate; The input end of the fourth inverter is used to input the PWM input signal, and the output end is connected to the input end of the fifth inverter and one input end of the fifth NAND gate; the other input end of the fifth NAND gate is connected to the output end of the fourth NAND gate; the output end of the fifth inverter is connected to one input end of the fourth NAND gate; the other input end of the fourth NAND gate is connected to the output end of the fifth NAND gate; The output end of the fourth NAND gate is used to output the low-side power tube control signal; the output end of the fifth NAND gate is used to output the high-side power tube control signal.

[0013] In an optional solution, the high-side power tube shutdown module includes: a third inverter, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a first high-voltage tube and a second high-voltage tube; The input end of the third inverter is connected to the gate of the first high-voltage tube, and is used to input the high-side power tube control signal. The output end of the third inverter is connected to the gate of the second high-voltage tube. The source of the second high-voltage tube is connected to the drain of the thirteenth NMOS tube. The gate of the thirteenth NMOS tube is connected to the gate of the twelfth NMOS tube and the gate and drain of the eleventh NMOS tube and connected to the power supply voltage. The drain of the twelfth NMOS tube is connected to the source of the first high-voltage tube. The sources of the eleventh NMOS tube, the twelfth NMOS tube, and the thirteenth NMOS tube are all grounded. The drain of the first high-voltage tube is connected to the gate and drain of the fifth PMOS tube, the gate of the sixth PMOS tube, the drain of the seventh PMOS tube and the gate of the ninth PMOS tube; the drain of the sixth PMOS tube is connected to the drain and gate of the eighth PMOS tube, the gate of the seventh PMOS tube, the drain of the ninth PMOS tube, the gate of the tenth PMOS tube and the drain of the second high-voltage tube; The drain of the tenth PMOS tube is connected to the high-side power tube driving module and serves as the output end of the half-bridge driving control circuit; The sources of the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube are connected to the gate of the high-side power tube and output the driving signal of the high-side power tube.

[0014] In an optional solution, the high-side power tube shutdown module includes a third buffer and a fourth buffer; the high-side power tube control signal is input to the gate of the first high-voltage tube through the third buffer; and the fourth buffer is connected between the third inverter and the second high-voltage tube.

[0015] In an optional solution, the low-side power tube driving module is a buffer or a combination of buffers connected in series; the input end of the buffer is connected to the output end of the fourth NAND gate, and the output end of the buffer is connected to the gate of the low-side power tube.

[0016] In an optional solution, the drain of the high-side power tube is connected to the input voltage, the source is connected to the drain of the low-side power tube and the output of the half-bridge drive control circuit, and the source of the low-side power tube is grounded.

[0017] The beneficial effects of the present invention are: The present invention can improve the electromagnetic radiation performance of half-bridge and full-bridge driver chips, and at the same time, the driver chip can save the bootstrap capacitor outside the chip, thereby reducing the system cost. Specifically, by integrating the high-side power tube driver module in the chip as the driving circuit of the high-side power tube, the bootstrap capacitor outside the chip is saved, and at the same time, by adjusting the opening speed of the high-side power tube driver module, the conduction slope of the high-side power tube can be controlled, thereby facilitating the optimization of electromagnetic radiation characteristics from the system level. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which like reference numerals generally represent like components.

[0019] Figure 1 Schematic diagram of full-bridge motor power stage drive.

[0020] Figure 2 It is an existing automotive-grade half-bridge drive circuit.

[0021] Figure 3 This is a schematic diagram of a half-bridge drive control circuit architecture according to an embodiment of the present invention.

[0022] Figure 4 This is a schematic diagram of a half-bridge drive control circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and drawings, the advantages and features of the present invention will become clearer. However, it should be noted that the concept of the technical solution of the present invention can be implemented in a variety of different forms and is not limited to the specific embodiments described herein. The drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0024] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0025] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0026] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0027] Example 1 Reference Figure 3 and Figure 4 , this embodiment provides a half-bridge drive control circuit, including: High-side power tube HSMN, low-side power tube LSMN, logic module LOGIC_CTR, high-side power tube driver module CHARGE_PUMP, high-side power tube shutdown module HS_OFF_CTR and low-side power tube driver module LS_DRV; The logic module LOGIC_CTR is used to convert the PWM input signal PWM_IN into a high-side power tube control signal EN_HS_ON and a low-side power tube control signal EN_LS_ON; The high-side power tube driving module CHARGE_PUMP controls the high-side power tube to be turned on according to the input high-side power tube control signal EN_HS_ON; The high-side power tube shutdown module HS_OFF_CTR controls the high-side power tube to be shut down according to the input high-side power tube control signal EN_HS_ON; The low-side power tube driving module LS_DRV controls the low-side power tube to be turned on and off according to the input low-side power tube control signal EN_LS_ON; The high-side power tube control signal EN_HS_ON and the low-side power tube control signal EN_LS_ON have opposite levels at the same time; when the high-side power tube is turned on, the low-side power tube is turned off, and when the high-side power tube is turned off, the low-side power tube is turned on.

[0028] That is, the high-side power tube control signal EN_HS_ON controls the high-side power tube to be turned on through the high-side power tube driver module CHARGE_PUMP, and controls the high-side power tube to be turned off through the high-side power tube shutdown module HS_OFF_CTR. The low-side power tube control signal EN_LS_ON controls the low-side power tube to be turned on and off through the low-side power tube driver module LS_DRV. When the high-side power tube is turned off, the low-side power tube is turned on, and when the low-side power tube is turned off, the high-side power tube is turned on. Specifically, in this embodiment, the input signal of the high-side power tube driving module CHARGE_PUMP also includes: a slope adjustment signal TRIM_HS_SR<2:0>, a clock signal CLK_IN and an output signal OUT of the half-bridge drive control circuit, and the high-side power tube driving module CHARGE_PUMP outputs a high-side power tube voltage driving signal HS_GATE_DRV; when the high-side power tube control signal EN_HS_ON changes from a low level to a high level, the high-side power tube driving module CHARGE_PUMP starts working, and under the control of the clock signal CLK_IN, the output high-side power tube voltage driving signal HS_GATE_DRV is gradually increased, thereby controlling the high-side power tube to be turned on, and at the same time the low-side power tube is turned off; when the high-side power tube control signal EN_HS_ON changes from a high level to a low level, the high-side power tube shutdown module HS_OFF_CTR pulls down the high-side power tube voltage driving signal to turn off the high-side power tube, and at the same time the low-side power tube is turned on. The slope adjustment signal is used to adjust the voltage increase speed of the driving signal HS_GATE_DRV. The drain of the high-side power tube HSMN is connected to the input voltage VIN, the source is connected to the drain of the low-side power tube LSMN and the output OUT of the half-bridge drive control circuit, and the source of the low-side power tube LSMN is grounded. In this embodiment, the high-side power tube driving module CHARGE_PUMP includes: a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a first inverter INV1, a second inverter INV2, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth NMOS tube MN8, a ninth NMOS tube MN9, a tenth NMOS tube MN10, a first resistor R1, a second resistor R2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth NMOS tube MN8, a ninth NMOS tube MN9, a tenth NMOS tube MN10, a first resistor R1, a second resistor R2 a first resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first capacitor C1 and a second capacitor C2; one input end of the first NAND gate NAND1 is used to input the high-side power tube control signal EN_HS_ON, the other input end is used to input the clock signal CLK_IN, and the output end is connected to the input end of the first inverter INV1; the output end of the first inverter INV1 is connected to the input end of the second inverter INV2 and an input end of the second NAND gate NAND2; the other input end of the second NAND gate NAND2 is connected to the output end of the third NAND gate NAND3; the second inverter IN The output end of V2 is connected to an input end of the third NAND gate NAND3, and the other input end of the third NAND gate NAND3 is connected to the output end of the second NAND gate NAND2; the output end of the second NAND gate NAND2 is connected to the gate of the first NMOS transistor MN1 and the gate of the first PMOS transistor MP1; the source of the first PMOS transistor MP1 is connected to the power supply voltage VDD, and the drain is connected to the drain of the first NMOS transistor MN1 and one end of the first capacitor C1; the source of the first NMOS transistor MN1 is grounded through the first resistor R1, connected to the drain of the fourth NMOS transistor MN4 through the second resistor R2, and connected to the third The drain of the NMOS tube MN3 is connected to the drain of the second NMOS tube MN2 through the fourth resistor R4; the sources of the second NMOS tube MN2, the third NMOS tube MN3 and the fourth NMOS tube MN4 are all grounded; the gates of the second NMOS tube MN2, the third NMOS tube MN3 and the fourth NMOS tube MN4 are used to input the slope adjustment signal; the output end of the third NAND gate NAND3 is connected to the gate of the fifth NMOS tube MN5 and the gate of the second PMOS tube MP2; the source of the second PMOS tube MP2 is connected to the power supply voltage VDD, and the drain is connected to the drain of the fifth NMOS tube MN5 and one end of the second capacitor C2;The source of the fifth NMOS tube MN5 is grounded through the fifth resistor R5, connected to the drain of the sixth NMOS tube MN6 through the sixth resistor R6, connected to the drain of the seventh NMOS tube MN7 through the seventh resistor R7, and connected to the drain of the eighth NMOS tube MN8 through the eighth resistor R8; the sources of the sixth NMOS tube MN6, the seventh NMOS tube MN7, and the eighth NMOS tube MN8 are all grounded; the gate of the sixth NMOS tube MN6 is connected to the gate of the fourth NMOS tube MN4; the gate of the seventh NMOS tube MN7 is connected to the gate of the third NMOS tube MN3; the gate of the eighth NMOS tube MN8 is connected to the gate of the second NMOS tube MN2; the other end of the first capacitor C1 ... The gate of the third PMOS tube MP3, the gate of the ninth NMOS tube MN9, the drain of the fourth PMOS tube MP4 and the drain of the tenth NMOS tube MN10; the source of the ninth NMOS tube MN9 and the source of the tenth NMOS tube MN10 are connected to the high-side power tube shutdown module and serve as the output end of the half-bridge drive control circuit; the drain of the ninth NMOS tube MN9 is connected to the gate of the third PMOS tube MP3, the gate of the fourth PMOS tube MP4, the gate of the tenth NMOS tube MN10 and the other end of the second capacitor C2; the source of the third PMOS tube MP3 and the source of the fourth PMOS tube MP4 are connected to the gate of the high-side power tube and output the driving signal HS_GATE_DRV of the high-side power tube. ;

[0029] In this embodiment, the high-side power tube driver module CHARGE_PUMP also includes a first buffer BUF1 and a second buffer BUF2; the first buffer BUF1 is connected between the output end of the second NAND gate NAND2 and the gate of the first PMOS tube MP1; the second buffer BUF2 is connected between the output end of the third NAND gate NAND3 and the gate of the second PMOS tube MP2.

[0030] In this embodiment, the logic module LOGIC_CTR includes: a fourth inverter INV4, a fifth inverter INV5, a fourth NAND gate NAND4 and a fifth NAND gate NAND5; the input end of the fourth inverter INV4 is used to input the PWM input signal, and the output end is connected to the input end of the fifth inverter INV5 and an input end of the fifth NAND gate NAND5; the other input end of the fifth NAND gate NAND5 is connected to the output end of the fourth NAND gate NAND4; the output end of the fifth inverter INV5 is connected to an input end of the fourth NAND gate NAND4; the other input end of the fourth NAND gate NAND4 is connected to the output end of the fifth NAND gate NAND5; the output end of the fourth NAND gate NAND4 is used to output the low-side power tube control signal EN_LS_ON; the output end of the fifth NAND gate NAND5 is used to output the high-side power tube control signal EN_HS_ON. It should be noted that the function of the logic module LOGIC_CTR is to generate the low-side power tube control signal EN_LS_ON and the high-side power tube control signal EN_HS_ON. However, the generation method of the low-side power tube control signal EN_LS_ON and the high-side power tube control signal EN_HS_ON is not limited to this. In other embodiments, they can also be independently controlled by the host.

[0031] The high-side power tube shutdown module HS_OFF_CTR includes: a third inverter INV3, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9, a tenth PMOS tube MP10, an eleventh NMOS tube MN11, a twelfth NMOS tube MN12, a thirteenth NMOS tube MN13, a first high-voltage tube HVMN1 and a second high-voltage tube HVMN2; the input end of the third inverter INV3 is connected to the gate of the first high-voltage tube HVMN1, and is used to input the high-side The power tube control signal EN_HS_ON is generated, the output end of the third inverter INV3 is connected to the gate of the second high-voltage tube HVMN2, the source of the second high-voltage tube HVMN2 is connected to the drain of the thirteenth NMOS tube MN13, the gate of the thirteenth NMOS tube MN13 is connected to the gate of the twelfth NMOS tube MN12 and the gate and drain of the eleventh NMOS tube MN11 and connected to the power supply voltage VDD; the drain of the twelfth NMOS tube MN12 is connected to the source of the first high-voltage tube HVMN1; the eleventh NMOS tube MN11 is connected to the gate of the twelfth NMOS tube MN12 and the gate and drain of the eleventh NMOS tube MN11. The sources of the twelfth NMOS tube MN12 and the thirteenth NMOS tube MN13 are all grounded; the drain of the first high-voltage tube HVMN1 is connected to the gate and drain of the fifth PMOS tube MP5, the gate of the sixth PMOS tube MP6, the drain of the seventh PMOS tube MP7 and the gate of the ninth PMOS tube MP9; the drain of the sixth PMOS tube MP6 is connected to the drain and gate of the eighth PMOS tube MP8 and the gate of the seventh PMOS tube MP7, the drain of the ninth PMOS tube MP9, the drain of the tenth PMOS tube MP10 the gate of the high-side power tube HSMN and the drain of the second high-voltage tube HVMN2; the drain of the tenth PMOS tube MP10 is connected to the high-side power tube driving module CHARGE_PUMP and serves as the output end of the half-bridge driving control circuit; the source of the fifth PMOS tube MP5, the sixth PMOS tube MP6, the seventh PMOS tube MP7, the eighth PMOS tube MP8, the ninth PMOS tube MP9 and the tenth PMOS tube MP10 is connected to the gate of the high-side power tube HSMN and outputs the driving signal HS_GATE_DRV of the high-side power tube.

[0032] In this embodiment, the high-side power tube shutdown module HS_OFF_CTR includes a third buffer BUF3 and a fourth buffer BUF4; the high-side power tube control signal EN_HS_ON is input to the gate of the first high-voltage tube HVMN1 through the third buffer BUF3; and the fourth buffer BUF4 is connected between the third inverter INV3 and the second high-voltage tube HVMN2.

[0033] The low-side power transistor driving module LS_DRV is a buffer or a combination of buffers connected in series; the input end of the buffer is connected to the output end of the fourth NAND gate NAND4, and the output end of the buffer is connected to the gate of the low-side power transistor LSMN. Figure 4 In this embodiment, the low-side power tube driving module LS_DRV includes a fifth buffer BUF5 and a sixth buffer BUF6; the input end of the fifth buffer BUF5 is connected to the output end of the fourth NAND gate NAND4, the output end of the fifth buffer BUF5 is connected to the input end of the sixth buffer BUF6 and the output end of the fifth buffer BUF5, and the output end of the sixth buffer BUF6 is connected to the gate of the low-side power tube LSMN.

[0034] The working principle of the half-bridge drive control circuit is described below: The function of the logic module LOGIC_CTR is to convert the PWM input signal PWM_IN into the enable signal of the high-side power tube HSMN and the low-side power tube LSMN. When PWM_IN=H, EN_HS_ON=H, EN_LS_ON=L. At this time, the high-side power tube driver module CHARGE_PUMP is enabled to turn on the high-side power tube HSMN and turn off the low-side power tube LSMN. When PWM_IN=L, EN_HS_ON=L, EN_LS_ON=H. At this time, the high-side power tube driver module CHARGE_PUMP is turned off, the high-side power tube HSMN is turned off, and the low-side power tube LSMN is turned on.

[0035] The function of the high-side power tube driver module CHARGE_PUMP is to control the conduction of the high-side power tube HSMN. Its input signals are the high-side power tube control signal EN_HS_ON, the slope adjustment signal TRIM_HS_SR<2:0>, the high-frequency clock signal CLK_IN and the output signal OUT of the control circuit. Its output signal is the high-side power tube drive signal HS_GATE_DRV. When EN_HS_ON changes from a low level to a high level, the high-side power tube driver module CHARGE_PUMP starts to work. Under the control of the high-frequency clock signal CLK_IN, the third PMOS tube MP3, the ninth NMOS tube MN9, the first PMOS tube MP1, the first NMOS tube MN1, the fourth PMOS tube MP4, the tenth NMOS tube MN10, the second PMOS tube MP2, and the fifth NMOS tube MN5 charge and discharge the first capacitor C1 and the second capacitor C2 in turn, and the voltage of the high-side power tube drive signal HS_GATE_DRV increases from V OUT Gradually increase and finally reach V HS_GATE_DRV =V OUT +VDD . The first capacitor C1 and the second capacitor C2 are integrated capacitors inside the chip. In this module, the function of the slope adjustment signal TRIM_HS_SR<2:0> is to adjust the equivalent impedance of nodes S1 and S2 to the ground by controlling the conduction and shutdown of the second NMOS tube MN2, the third NMOS tube MN3, the fourth NMOS tube MN4, the sixth NMOS tube MN6, the seventh NMOS tube MN7, and the eighth NMOS tube MN8, thereby adjusting the rising speed of the driving signal HS_GATE_DRV of the high-side power tube. The slope adjustment signal TRIM_HS_SR<2:0> is generated by a digital control register, a host interface, etc., which is a conventional technology in this field. Based on symmetry considerations, the width-to-length ratio of the second NMOS tube MN2, the third NMOS tube MN3, the fourth NMOS tube MN4, the sixth NMOS tube MN6, the seventh NMOS tube MN7, and the eighth NMOS tube MN8 is consistent, and at the same time, the resistance values ​​R1=R5, R2=R6, R3=R7, and R4=R8. For example, when the driving signal TRIM_HS_SR<2:0> of the high-side power tube is 111, the equivalent impedance R to ground of the S1 node (the intersection of the source of the first NMOS tube and the fourth resistor) is S1 =R1 / / R2 / / R3 / / R4 (in parallel), the equivalent impedance to ground of node S2 (the intersection of the source of the fifth NMOS tube and the eighth resistor) R S2 =R5 / / R6 / / R7 / / R8, at this time, the equivalent resistance is the smallest, and the high-side power tube HSMN is turned on with the fastest slope; when TRIM_HS_SR<2:0>=000, the equivalent impedance of the S1 node to ground R S1 = R1, S2 node equivalent impedance to ground R S2 =R5, at this time the equivalent resistance is the largest and the high-side power tube HSMN has the slowest turn-on slope.

[0036] The function of the high-side power tube shutdown module HS_OFF_CTR is that when PWM_IN=L, EN_HS_ON=L, and EN_LS_ON=H, when the low-side power tube LSMN starts to conduct, the high-side power tube drive signal HS_GATE_DRV is pulled to the same potential as the OUT terminal, so that V GS_HSMN =0 (high-side power tube gate-source voltage), the high-side power tube HSMN is completely turned off. The first high-voltage tube HVMN1 and the second high-voltage tube HVMN2 are high-voltage tubes. The high-voltage tubes in this embodiment refer to MOS tubes whose input drain-source voltage is allowed to be above 5V. When EN_HS_ON=L, the first high-voltage tube HVMN1 is turned off, the G9 node is at a high level, the first high-voltage tube HVMN2 is turned on, and the G10 node (the intersection of the drain of the eighth PMOS tube and the gate of the tenth PMOS tube) is pulled down to turn on the tenth MOS tube MP10, thereby making V HS_GATE_DRV =VOUT When PWM_IN=H, EN_HS_ON=H, EN_LS_ON=L, when the low-side power tube LSMN is turned off, at this time, the first high-voltage tube HVMN1 is turned on, and the G9 node (the intersection of the drain of the fifth PMOS tube and the gate of the ninth PMOS tube) is pulled down to turn on the ninth PMOS tube MP9 and turn off the tenth PMOS tube MP10, so that the high-side power tube HSMN is gradually controlled to be turned on by the high-side power tube driving module CHARGE_PUMP module.

[0037] This implementation uses the high-side power tube driver module CHARGE_PUMP in the chip as the driving circuit of the high-side power tube, eliminating the bootstrap capacitor outside the chip and saving the overall system cost. At the same time, the chip has no external bootstrap capacitor, which helps to improve its electromagnetic radiation characteristics. This embodiment can flexibly control the conduction slope of the high-side power tube by adjusting the charging and discharging speed of the high-side power tube driver module CHARGE_PUMP, thereby facilitating further optimization of the electromagnetic radiation characteristics from the system level. The half-bridge drive control circuit proposed in this embodiment has the characteristics of low system cost and good electromagnetic interference characteristics. The half-bridge drive control circuit can be widely used in vehicle-mounted motor drive chips and various full-bridge drive chips.

[0038] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A half-bridge drive control circuit, characterized in that: include: High-side power tube, low-side power tube, logic module, high-side power tube driver module, high-side power tube shutdown module and low-side power tube driver module; The logic module is used to convert the PWM input signal into a high-side power tube control signal and a low-side power tube control signal; The high-side power tube driving module controls the high-side power tube to be turned on according to the input high-side power tube control signal; The high-side power tube shutdown module controls the high-side power tube to shut down according to the input high-side power tube control signal; The low-side power tube driving module controls the low-side power tube to be turned on and off according to the input low-side power tube control signal; The high-side power tube control signal and the low-side power tube control signal are at opposite levels at the same time; when the high-side power tube is turned on, the low-side power tube is turned off, and when the high-side power tube is turned off, the low-side power tube is turned on; The input signal of the high-side power tube driving module also includes: a clock signal and an output signal of the half-bridge driving control circuit, and the high-side power tube driving module outputs a high-side power tube voltage driving signal; When the high-side power tube control signal changes from a low level to a high level, the high-side power tube driving module starts to work, and under the control of the clock signal, the output high-side power tube voltage driving signal is gradually increased, thereby controlling the high-side power tube to be turned on, and the low-side power tube to be turned off; When the high-side power tube control signal changes from a high level to a low level, the high-side power tube shutdown module pulls down the high-side power tube voltage drive signal to shut down the high-side power tube, while turning on the low-side power tube.

2. The half-bridge drive control circuit according to claim 1, characterized in that: The input signal of the high-side power tube driving module includes a slope adjustment signal, and the slope adjustment signal is used to adjust the voltage increase speed of the driving signal.

3. The half-bridge drive control circuit according to claim 2, characterized in that: The high-side power tube driving module includes: A first NAND gate, a second NAND gate, a third NAND gate, a first inverter, a second inverter, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first capacitor, and a second capacitor; One input end of the first NAND gate is used to input the high-side power tube control signal, the other input end is used to input the clock signal, and the output end is connected to the input end of the first inverter; the output end of the first inverter is connected to the input end of the second inverter and one input end of the second NAND gate; the other input end of the second NAND gate is connected to the output end of the third NAND gate; the output end of the second inverter is connected to one input end of the third NAND gate, and the other input end of the third NAND gate is connected to the output end of the second NAND gate; The output end of the second NAND gate is connected to the gate of the first NMOS tube and the gate of the first PMOS tube; the source of the first PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the first NMOS tube and one end of the first capacitor; the source of the first NMOS tube is grounded through the first resistor, connected to the drain of the fourth NMOS tube through the second resistor, connected to the drain of the third NMOS tube through the third resistor, and connected to the drain of the second NMOS tube through the fourth resistor; the sources of the second NMOS tube, the third NMOS tube, and the fourth NMOS tube are all grounded; the gates of the second NMOS tube, the third NMOS tube, and the fourth NMOS tube are used to input the slope adjustment signal; The output end of the third NAND gate is connected to the gate of the fifth NMOS tube and the gate of the second PMOS tube; the source of the second PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the fifth NMOS tube and one end of the second capacitor; the source of the fifth NMOS tube is grounded through the fifth resistor, connected to the drain of the sixth NMOS tube through the sixth resistor, connected to the drain of the seventh NMOS tube through the seventh resistor, and connected to the drain of the eighth NMOS tube through the eighth resistor; the sources of the sixth NMOS tube, the seventh NMOS tube, and the eighth NMOS tube are all grounded; the gate of the sixth NMOS tube is connected to the gate of the fourth NMOS tube; the gate of the seventh NMOS tube is connected to the gate of the third NMOS tube; the gate of the eighth NMOS tube is connected to the gate of the second NMOS tube; The other end of the first capacitor is connected to the gate of the third PMOS tube, the gate of the ninth NMOS tube, the drain of the fourth PMOS tube and the drain of the tenth NMOS tube; the source of the ninth NMOS tube and the source of the tenth NMOS tube are connected to the high-side power tube shutdown module and serve as the output end of the half-bridge drive control circuit; the drain of the ninth NMOS tube is connected to the gate of the third PMOS tube, the gate of the fourth PMOS tube, the gate of the tenth NMOS tube and the other end of the second capacitor; the source of the third PMOS tube and the source of the fourth PMOS tube are connected to the gate of the high-side power tube and output the drive signal of the high-side power tube.

4. The half-bridge drive control circuit according to claim 3, characterized in that: The high-side power tube driving module also includes a first buffer and a second buffer; The first buffer is connected between the output end of the second NAND gate and the gate of the first PMOS tube; The second buffer is connected between the output end of the third NAND gate and the gate of the second PMOS tube.

5. The half-bridge drive control circuit according to claim 1, characterized in that: The logic module includes: a fourth inverter, a fifth inverter, a fourth NAND gate and a fifth NAND gate; The input end of the fourth inverter is used to input the PWM input signal, and the output end is connected to the input end of the fifth inverter and one input end of the fifth NAND gate; the other input end of the fifth NAND gate is connected to the output end of the fourth NAND gate; the output end of the fifth inverter is connected to one input end of the fourth NAND gate; the other input end of the fourth NAND gate is connected to the output end of the fifth NAND gate; The output end of the fourth NAND gate is used to output the low-side power tube control signal; the output end of the fifth NAND gate is used to output the high-side power tube control signal.

6. The half-bridge drive control circuit according to claim 1, characterized in that: The high-side power tube shutdown module includes: a third inverter, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a first high-voltage tube, and a second high-voltage tube; The input end of the third inverter is connected to the gate of the first high-voltage tube, and is used to input the high-side power tube control signal. The output end of the third inverter is connected to the gate of the second high-voltage tube. The source of the second high-voltage tube is connected to the drain of the thirteenth NMOS tube. The gate of the thirteenth NMOS tube is connected to the gate of the twelfth NMOS tube and the gate and drain of the eleventh NMOS tube and connected to the power supply voltage. The drain of the twelfth NMOS tube is connected to the source of the first high-voltage tube. The sources of the eleventh NMOS tube, the twelfth NMOS tube, and the thirteenth NMOS tube are all grounded. The drain of the first high-voltage tube is connected to the gate and drain of the fifth PMOS tube, the gate of the sixth PMOS tube, the drain of the seventh PMOS tube and the gate of the ninth PMOS tube; the drain of the sixth PMOS tube is connected to the drain and gate of the eighth PMOS tube, the gate of the seventh PMOS tube, the drain of the ninth PMOS tube, the gate of the tenth PMOS tube and the drain of the second high-voltage tube; The drain of the tenth PMOS tube is connected to the high-side power tube driving module and serves as the output end of the half-bridge driving control circuit; The sources of the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube are connected to the gate of the high-side power tube and output the driving signal of the high-side power tube.

7. The half-bridge drive control circuit according to claim 6, characterized in that: The high-side power tube shutdown module includes a third buffer and a fourth buffer; the high-side power tube control signal is input to the gate of the first high-voltage tube through the third buffer; and the fourth buffer is connected between the third inverter and the second high-voltage tube.

8. The half-bridge drive control circuit according to claim 1, characterized in that: The low-side power tube driving module is a buffer or a combination of buffers connected in series; the input end of the buffer is connected to the output end of the fourth NAND gate, and the output end of the buffer is connected to the gate of the low-side power tube.

9. The half-bridge drive control circuit according to claim 1, characterized in that: The drain of the high-side power tube is connected to the input voltage, the source is connected to the drain of the low-side power tube and the output of the half-bridge drive control circuit, and the source of the low-side power tube is grounded.

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