Bidirectional normally-closed switch

Abstract

The invention provides a bidirectional normally-closed switch, and belongs to the technical field of semiconductors. Comprising a bidirectional III-V depletion mode high electron mobility transistor, a first enhancement mode transistor and a second enhancement mode transistor, the bidirectional III-V depletion mode high electron mobility transistor comprises a first source electrode / drain electrode node, a second source electrode / drain electrode node, a first grid electrode, a second grid electrode and a first substrate, and the first substrate is an insulating substrate. A third drain electrode of the first enhancement mode transistor is connected with the first source electrode / drain electrode node, and a third source electrode of the first enhancement mode transistor is connected with the first grid electrode; a fourth drain electrode of the second enhancement mode transistor is connected with the second source electrode / drain electrode node, and a fourth source electrode of the second enhancement mode transistor is connected with the second grid electrode; the control source regulates and controls the gate-source voltage of the first enhancement mode transistor and the second enhancement mode transistor so as to control the bidirectional normally-closed switch. According to the invention, the control circuit of the bidirectional normally-closed switch can be simplified, and the back gate effect can be avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a bidirectional normally closed switch. Background Art

[0002] Based on whether the field effect transistor is in the on state or the off state under zero gate-source voltage, the field effect transistor is broadly divided into a depletion transistor or an enhancement transistor, among which the enhancement transistor is widely used in most circuits. When the gate-source voltage is zero, the field effect transistor is converted to the off state, that is, the enhancement transistor is a normally closed device; when the gate-source voltage is zero, the field effect transistor is converted to the on state, that is, the depletion transistor is a normally open device. Semiconductor bidirectional switches are widely used in potential conversion of modern power supplies, such as matrix converters. Semiconductor bidirectional switches can block voltages in two directions and conduct current in either direction. In modern power applications, in order to ensure its safety and reliability, the bidirectional switch must be a normally closed switch.

[0003] In the related art, the normally-off behavior of a general bidirectional normally-closed switch is implemented by a bidirectional depletion-mode transistor and two enhancement-mode transistors, wherein the bidirectional depletion-mode transistor includes: a first source / drain node, a second source / drain node, a first gate, and a second gate, the drain nodes of the two enhancement-mode transistors are respectively connected to the first source / drain node and the second source / drain node of the bidirectional depletion-mode transistor, and the gates of the two enhancement-mode transistors are coupled to the controller with the first gate and the second gate.

[0004] However, when driving a bidirectional normally closed switch based on the related technology, a control signal needs to be sent to the gates of the two enhancement transistors and the gate of the bidirectional depletion transistor via a controller to control the on and off of the bidirectional normally closed switch. This solution has the problem of complex circuit design and signal response delay. In addition, the substrate of the bidirectional depletion transistor is a non-insulating substrate, which makes it impossible for the bidirectional normally closed switch to avoid the back gate effect. Summary of the invention

[0005] The purpose of the present application is to provide a bidirectional normally closed switch, which can simplify the control circuit of the bidirectional normally closed switch and avoid the back gate effect.

[0006] The embodiment of the present application is implemented as follows:

[0007] According to a first aspect of an embodiment of the present application, a bidirectional normally closed switch is provided, the bidirectional normally closed switch comprising: a bidirectional III-V depletion-mode high electron mobility transistor, a first enhancement-mode transistor and a second enhancement-mode transistor, the bidirectional III-V depletion-mode high electron mobility transistor comprising: a first source / drain node, a second source / drain node, a first gate and a second gate, the first enhancement-mode transistor comprising: a third source, a third drain and a third gate, the second enhancement-mode transistor comprising: a fourth source, a fourth drain and a fourth gate;

[0008] The third drain of the first enhancement mode transistor is connected to the first source / drain node of the bidirectional III-V depletion mode high electron mobility transistor, and the third source of the first enhancement mode transistor is connected to the first gate of the bidirectional III-V depletion mode high electron mobility transistor;

[0009] The fourth drain of the second enhancement mode transistor is connected to the second source / drain node of the bidirectional III-V depletion mode high electron mobility transistor, and the fourth source of the second enhancement mode transistor is connected to the second gate of the bidirectional III-V depletion mode high electron mobility transistor;

[0010] The third gate of the first enhancement mode transistor is connected to an external first control source, and the gate-source voltage of the first enhancement mode transistor is controlled by the first control source. The fourth gate of the second enhancement mode transistor is connected to an external second control source, and the gate-source voltage of the second enhancement mode transistor is controlled by the second control source.

[0011] As a possible implementation, a bidirectional III-V depletion-mode high electron mobility transistor includes: a first substrate, the first substrate is an insulating substrate, a first enhancement-mode transistor includes: a second substrate, and a second enhancement-mode transistor includes: a third substrate;

[0012] The second substrate and the third substrate are the same substrate.

[0013] As a possible implementation manner, the second substrate and the third substrate are both insulating substrates;

[0014] Alternatively, the second substrate and the third substrate are both non-insulating substrates.

[0015] As a possible implementation, the third gate of the first enhancement mode transistor is connected to the first control node of the first control source, and the first gate of the bidirectional III-V depletion mode high electron mobility transistor is connected to the second control node of the first control source;

[0016] The fourth gate of the second enhancement mode transistor is connected to the third control node of the second control source, and the second gate of the bidirectional III-V depletion mode high electron mobility transistor is connected to the fourth control node of the second control source;

[0017] The first control source controls the voltage of the first gate, the second control source controls the voltage of the second gate, and when the negative voltage of the first gate and / or the second gate is abnormal and the bidirectional normally closed transistor cannot be turned off, the first control source controls the first enhancement transistor to be disconnected, and the second control source controls the second enhancement transistor to be disconnected, so that the bidirectional normally closed switch enters a safe mode.

[0018] As a possible implementation, the third gate of the first enhancement mode transistor is connected to the first control source, and the first gate of the bidirectional III-V depletion mode high electron mobility transistor is connected to an external third control source;

[0019] The fourth gate of the second enhancement mode transistor is connected to the second control source, and the second gate of the bidirectional III-V depletion mode high electron mobility transistor is connected to an external fourth control source;

[0020] The third control source and the fourth control source directly control the on-off of the bidirectional III-V depletion-mode high electron mobility transistor, the first control source controls the on-off of the first enhancement-mode transistor, and the second control source controls the on-off of the second enhancement-mode transistor.

[0021] As a possible implementation, the bidirectional normally closed switch further includes: a voltage dividing circuit, the voltage dividing circuit includes: a first voltage dividing circuit and a second voltage dividing circuit;

[0022] One end of the first voltage divider circuit is respectively connected to the third drain of the first enhancement mode transistor and the first source / drain node of the bidirectional III-V depletion mode high electron mobility transistor, and the other end of the first voltage divider circuit is respectively connected to the third source of the first enhancement mode transistor and the first gate of the bidirectional III-V depletion mode high electron mobility transistor;

[0023] One end of the second voltage divider circuit is respectively connected to the fourth drain of the second enhancement mode transistor and the second source / drain node of the bidirectional III-V depletion mode high electron mobility transistor, and the other end of the second voltage divider circuit is respectively connected to the fourth source of the second enhancement mode transistor and the second gate of the bidirectional III-V depletion mode high electron mobility transistor.

[0024] As a possible implementation, the first voltage divider circuit includes: a first resistor, and the second voltage divider circuit includes: a second resistor;

[0025] One end of the first resistor is respectively connected to the third drain of the first enhancement mode transistor and the first source / drain node of the bidirectional III-V depletion mode high electron mobility transistor, and the other end of the first resistor is respectively connected to the third source of the first enhancement mode transistor and the first gate of the bidirectional III-V depletion mode high electron mobility transistor;

[0026] One end of the second resistor is respectively connected to the fourth drain of the second enhancement mode transistor and the second source / drain node of the bidirectional III-V depletion mode high electron mobility transistor, and the other end of the second resistor is respectively connected to the fourth source of the second enhancement mode transistor and the second gate of the bidirectional III-V depletion mode high electron mobility transistor.

[0027] As a possible implementation, the first voltage divider circuit includes: a first resistor and a first capacitor, and the second voltage divider circuit includes: a second resistor and a second capacitor;

[0028] One end of the first resistor and one end of the first capacitor are both connected to the third drain of the first enhancement mode transistor and the first source / drain node of the bidirectional III-V depletion mode high electron mobility transistor, and the other end of the first resistor and the other end of the first capacitor are both connected to the third source of the first enhancement mode transistor and the first gate of the bidirectional III-V depletion mode high electron mobility transistor;

[0029] One end of the second resistor and one end of the second capacitor are connected to the fourth drain of the second enhancement transistor and the second source / drain node of the bidirectional III-V depletion-type high electron mobility transistor, and the other end of the second resistor and the other end of the second capacitor are connected to the fourth source of the second enhancement transistor and the second gate of the bidirectional III-V depletion-type high electron mobility transistor.

[0030] The beneficial effects of the embodiments of the present application include:

[0031] A bidirectional normally closed switch provided in an embodiment of the present application is a bidirectional normally closed transistor composed of a bidirectional III-V depletion-type high electron mobility transistor, a first enhancement-type transistor and a second enhancement-type transistor, wherein the third drain of the first enhancement-type transistor is connected to the first source / drain node of the bidirectional III-V depletion-type high electron mobility transistor, the third source of the first enhancement-type transistor is connected to the first gate of the bidirectional III-V depletion-type high electron mobility transistor, and the third gate of the first enhancement-type transistor is connected to an external first control source; the fourth drain of the second enhancement-type transistor is connected to the second source / drain node of the bidirectional III-V depletion-type high electron mobility transistor, and the fourth drain of the second enhancement-type transistor is connected to the second source / drain node of the bidirectional III-V depletion-type high electron mobility transistor. The fourth source of the second enhancement transistor is connected to the second gate of the bidirectional III-V depletion high electron mobility transistor, the fourth gate of the second enhancement transistor is connected to the external second control source, the first enhancement transistor and the second enhancement transistor are cascaded with the bidirectional III-V depletion high electron mobility transistor, the first control source controls the gate-source voltage between the third gate and the third source of the first enhancement transistor, the second control source controls the gate-source voltage between the fourth gate and the fourth source of the second enhancement transistor, and the bidirectional III-V depletion high electron mobility transistor enters the on or off state under the gate-source voltage of the first enhancement transistor and the gate-source voltage of the second enhancement transistor. In addition, the substrate of the bidirectional III-V depletion high electron mobility transistor is an insulating substrate, which can effectively avoid the back gate effect. In this way, the control circuit of the bidirectional normally closed switch can be simplified and the back gate effect can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 A schematic diagram of the structure of a monolithic dual-gate bidirectional III-V depletion-mode high electron mobility transistor provided in an embodiment of the present application;

[0034] Figure 2 A schematic diagram of the structure of a monolithic dual-gate common-drain bidirectional III-V depletion-mode high electron mobility transistor provided in an embodiment of the present application;

[0035] Figure 3 A schematic diagram of the structure of an integrated common-drain bidirectional III-V depletion-mode high electron mobility transistor provided in an embodiment of the present application;

[0036] Figure 4A connection diagram of a first bidirectional normally closed switch provided in an embodiment of the present application;

[0037] Figure 5 A connection diagram of a second bidirectional normally closed switch provided in an embodiment of the present application;

[0038] Figure 6 A connection diagram of a third bidirectional normally closed switch provided in an embodiment of the present application;

[0039] Figure 7 A schematic diagram of the structure of a voltage divider circuit in a bidirectional normally closed switch provided in an embodiment of the present application;

[0040] Figure 8 A schematic diagram of the structure of another voltage divider circuit in a bidirectional normally closed switch provided in an embodiment of the present application;

[0041] Fig. 9 A schematic diagram of the structure of a monolithic bidirectional normally closed switch provided in an embodiment of the present application;

[0042] Fig.10 A schematic diagram of the structure of a discrete bidirectional normally closed switch provided in an embodiment of the present application;

[0043] Fig.11 A connection diagram of a first monolithic bidirectional normally closed switch provided in an embodiment of the present application;

[0044] Fig.12 A connection diagram of a second monolithic bidirectional normally closed switch provided in an embodiment of the present application;

[0045] Fig.13 A connection diagram of a third monolithic bidirectional normally closed switch provided in an embodiment of the present application.

[0046] Description of the drawings: 10: bidirectional normally closed switch; 101: bidirectional III-V depletion-mode high electron mobility transistor; 1011: first substrate; 102: first enhancement-mode transistor; 1021: second substrate; 103: second enhancement-mode transistor; 1031: third substrate; 104: voltage divider circuit; 1041: first voltage divider circuit; 10411: first resistor; 10412: first capacitor; 1042: second voltage divider circuit; 10421: second resistor; 10422: second capacitor; 20: first control source; 21: second control source; 22: third control source; 23: fourth control source. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0048] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0049] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0050] In the description of the present application, it should be noted that the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0051] At present, the function of a bidirectional normally closed switch is often realized by a bidirectional III-V depletion high electron mobility transistor and two enhancement transistors, wherein the drain nodes of the two enhancement transistors are respectively connected to the first source / drain node and the second source / drain node of the bidirectional III-V depletion high electron mobility transistor, and the gates of the two enhancement transistors are coupled to the controller with the first gate and the second gate of the bidirectional III-V depletion high electron mobility transistor. When the negative gate voltage of the bidirectional normally closed switch is not available, the bidirectional normally closed switch can be put into a safe mode by disconnecting the two enhancement transistors. However, this solution requires sending a control signal to the gates of the two enhancement transistors and the gates of the bidirectional III-V depletion high electron mobility transistor via the controller to control the on and off of the bidirectional normally closed switch. This solution has the problem of complex circuit design and signal response delay. In addition, the substrate of the bidirectional III-V depletion high electron mobility transistor is a non-insulating substrate, which makes it impossible for the bidirectional normally closed switch to avoid the back gate effect.

[0052] To this end, the embodiment of the present application provides a bidirectional normally closed switch, which is composed of a bidirectional III-V depletion high electron mobility transistor, a first enhancement transistor and a second enhancement transistor, wherein the third drain of the first enhancement transistor is connected to the first source / drain node of the bidirectional III-V depletion high electron mobility transistor, and the third source of the first enhancement transistor is connected to the first gate of the bidirectional III-V depletion high electron mobility transistor; the fourth drain of the second enhancement transistor is connected to the second source / drain node of the bidirectional III-V depletion high electron mobility transistor, and the fourth source of the second enhancement transistor is connected to the second gate of the bidirectional III-V depletion high electron mobility transistor; the third gate of the first enhancement transistor is connected to an external first control source, and the gate-source voltage of the first enhancement transistor is controlled by the first control source, and the fourth gate of the second enhancement transistor is connected to an external second control source, and the gate-source voltage of the second enhancement transistor is controlled by the second control source. In this way, the effect of simplifying the control circuit of the bidirectional normally closed switch can be achieved.

[0053] The bidirectional normally closed switch provided in the embodiment of the present application is explained in detail below with reference to the accompanying drawings.

[0054] As an optional implementation, the bidirectional normally closed switch 10 is widely used in power conversion, such as a matrix converter, wherein the bidirectional normally closed switch 10 can block voltages in two directions and conduct current in either direction, and the bidirectional normally closed switch 10 can convert the potential of a modern power supply.

[0055] In addition, it should be noted that in the following figures, M1 is used to represent the first enhancement mode transistor 102, G3 is used to represent the third gate of the first enhancement mode transistor 102, S3 is used to represent the third source of the first enhancement mode transistor 102, and D3 is used to represent the third drain of the first enhancement mode transistor 102; M2 is used to represent the second enhancement mode transistor 103, G4 is used to represent the fourth gate of the second enhancement mode transistor 103, S4 is used to represent the fourth source of the second enhancement mode transistor 103, and D4 is used to represent the fourth drain of the second enhancement mode transistor 103; D-BI is used to represent the bidirectional III-V depletion type high electron mobility transistor 101, G1 is used to represent the first gate of the bidirectional III-V depletion type high electron mobility transistor 101, G2 is used to represent the second gate of the bidirectional III-V depletion type high electron mobility transistor 101, and N1 is used to represent the first source / drain junction of the bidirectional III-V depletion type high electron mobility transistor 101. point, N2 is used to represent the second source / drain node of the bidirectional III-V depletion type high electron mobility transistor 101, N1 (N5) is used to represent the connection between the first source / drain node of the bidirectional III-V depletion type high electron mobility transistor 101 and the third drain of the first enhancement mode transistor 102, N2 (N5) is used to represent the connection between the second source / drain node of the bidirectional III-V depletion type high electron mobility transistor 101 and the fourth drain of the second enhancement mode transistor 103, N3 (N6) is used to represent the connection between the first gate of the bidirectional III-V depletion type high electron mobility transistor 101 and the third source of the first enhancement mode transistor 102, N4 (N6) is used to represent the connection between the second gate of the bidirectional III-V depletion type high electron mobility transistor 101 and the fourth drain of the second enhancement mode transistor 103, and N1 (N2) is used to represent the common drain of the bidirectional III-V depletion type high electron mobility transistor 101.

[0056] Figure 1 A schematic diagram of the structure of a monolithic dual-gate bidirectional III-V depletion-mode high electron mobility transistor provided in this application, see Figure 1 The bidirectional III-V depletion-mode high electron mobility transistor 101 provided in the embodiment of the present application includes two gates, and the first substrate 1011 of the bidirectional III-V depletion-mode high electron mobility transistor 101 is an insulating substrate, wherein both depletion-mode transistors adopt field plate FP technology, and the field plates of the two depletion-mode transistors are arranged relatively to each other. The two depletion-mode transistors can be connected by cascading the drain of one depletion-mode transistor and the drain of another depletion-mode transistor, or by cascading the source of one depletion-mode transistor and the source of another depletion-mode transistor. The present application does not make any specific limitation on this.

[0057] As an optional implementation, the bidirectional III-V depletion-type high electron mobility transistor 101 can be formed using GaN technology. The bidirectional III-V depletion-type high electron mobility transistor 101 is a symmetrical structure. The bidirectional III-V depletion-type high electron mobility transistor 101 mainly includes an insulating substrate, a core layer / transition layer buffer layer, a channel layer, and a barrier layer. Among them, the material of the insulating substrate of the bidirectional III-V depletion-type high electron mobility transistor 101 can be Sapphire, Dimond, etc., the channel layer of the bidirectional III-V depletion-type high electron mobility transistor 101 can be unintentionally doped (UID) GaN, and the barrier layer of the bidirectional III-V depletion-type high electron mobility transistor 101 can be Al X GaN 1-X The first gate and the second gate of the bidirectional III-V depletion-mode high electron mobility transistor 101 may adopt field plate (FP) technology.

[0058] Figure 2 A schematic diagram of the structure of a monolithic dual-gate common-drain bidirectional III-V depletion-mode high electron mobility transistor provided in this application, see Figure 2 The bidirectional III-V depletion-mode high electron mobility transistor 101 provided in the embodiment of the present application is a monolithic common-drain transistor, that is, the bidirectional III-V depletion-mode high electron mobility transistor 101 is composed of two depletion-mode transistors with a common drain, and the first substrates 1011 of the two depletion-mode transistors are both insulating substrates.

[0059] Figure 3 A schematic diagram of the structure of an integrated common drain bidirectional III-V depletion-mode high electron mobility transistor provided in this application, see Figure 3 The bidirectional III-V depletion-mode high electron mobility transistor 101 provided in the present application is integrated by two depletion-mode transistors, and the first substrates 1011 of the two depletion-mode transistors are both insulating substrates, which can effectively avoid the back-gate effect of the bidirectional III-V depletion-mode high electron mobility transistor 101.

[0060] Figure 4 The schematic diagram of the structure of the first bidirectional normally closed switch provided in this application is shown in FIG. Figure 4 The bidirectional normally closed switch 10 provided in the embodiment of the present application includes: a bidirectional III-V depletion-mode high electron mobility transistor 101, a first enhancement-mode transistor 102 and a second enhancement-mode transistor 103, the bidirectional III-V depletion-mode high electron mobility transistor 101 includes: a first source / drain node, a second source / drain node, a first gate and a second gate, the first enhancement-mode transistor 102 includes: a third source, a third drain and a third gate, and the second enhancement-mode transistor 103 includes: a fourth source, a fourth drain and a fourth gate.

[0061] Optionally, the bidirectional III-V depletion-mode high electron mobility transistor 101 is integrated by two depletion-mode transistors. The two depletion-mode transistors constituting the bidirectional III-V depletion-mode high electron mobility transistor 101 can be either N-channel depletion-mode transistors, or P-type depletion-mode transistors, or normally-off III-V transistors; the first enhancement-mode transistor 102 and the second enhancement-mode transistor 103 can be either N-channel enhancement-mode transistors, or P-type enhancement-mode transistors, or normally-off III-V transistors, and the present application does not make any specific limitation on this.

[0062] Optionally, the first source / drain node and the second source / drain node of the bidirectional III-V depletion-type high electron mobility transistor 101 can serve as both the source and the drain of the bidirectional III-V depletion-type high electron mobility transistor 101. When the first source / drain node and the second source / drain node both serve as the source of the bidirectional III-V depletion-type high electron mobility transistor 101, the bidirectional III-V depletion-type high electron mobility transistor 101 shares a drain; when the first source / drain node and the second source / drain node both serve as the drain of the bidirectional III-V depletion-type high electron mobility transistor 101, the bidirectional III-V depletion-type high electron mobility transistor 101 shares a source, and the source and drain of the bidirectional III-V depletion-type high electron mobility transistor 101 are determined by the connection relationship between the two depletion-type transistors, which is not specifically limited in the present application.

[0063] Optionally, the first gate and the second gate of the bidirectional III-V depletion-mode high electron mobility transistor 101 are gates of two depletion-mode transistors.

[0064] The third drain of the first enhancement mode transistor 102 is connected to the first source / drain node of the bidirectional III-V depletion mode high electron mobility transistor 101 , and the third source of the first enhancement mode transistor 102 is connected to the first gate of the bidirectional III-V depletion mode high electron mobility transistor 101 .

[0065] Optionally, the first enhancement mode transistor 102 is cascaded with the bidirectional III-V depletion mode high electron mobility transistor 101, and the gate-source voltage between the third gate and the third source of the first enhancement mode transistor 102 is controlled to regulate the on and off of the first gate of the bidirectional III-V depletion mode high electron mobility transistor 101.

[0066] The fourth drain of the second enhancement mode transistor 103 is connected to the second source / drain node of the bidirectional III-V depletion mode high electron mobility transistor 101 , and the fourth source of the second enhancement mode transistor 103 is connected to the second gate of the bidirectional III-V depletion mode high electron mobility transistor 101 .

[0067] Optionally, the second enhancement mode transistor 103 is cascaded with the bidirectional III-V depletion mode high electron mobility transistor 101, and the gate-source voltage between the fourth gate and the fourth source of the second enhancement mode transistor 103 is controlled to regulate the conduction and cutoff of the second gate of the bidirectional III-V depletion mode high electron mobility transistor 101.

[0068] The third gate of the first enhancement mode transistor 102 is connected to the external first control source 20, and the gate-source voltage of the first enhancement mode transistor 102 is controlled by the first control source 20. The fourth gate of the second enhancement mode transistor 103 is connected to the external second control source 21, and the gate-source voltage of the second enhancement mode transistor 103 is controlled by the second control source 21.

[0069] Optionally, an externally connected first control source 20 controls the gate-source voltage between the third gate and the third source of the first enhancement-mode transistor 102, and an externally connected second control source 21 controls the gate-source voltage between the fourth gate and the fourth source of the second enhancement-mode transistor 103, and the on and off of the bidirectional III-V depletion-mode high electron mobility transistor 101 are controlled based on the control signals of the first control source 20 and the second control source 21.

[0070] Optionally, if the first enhancement-mode transistor 102 is turned on and the second enhancement-mode transistor 103 is turned on, the bidirectional III-V depletion-mode high electron mobility transistor 101 can conduct current bidirectionally; if the first enhancement-mode transistor 102 is turned off and the second enhancement-mode transistor 103 is turned off, the bidirectional III-V depletion-mode high electron mobility transistor 101 can block current bidirectionally.

[0071] Optionally, when the first enhancement mode transistor 102 is turned on and the second enhancement mode transistor 103 is turned off, if the voltage difference between the fourth source of the second enhancement mode transistor 103 and the third source of the first enhancement mode transistor 102 is greater than zero, the current in the bidirectional normally closed switch 10 flows from the fourth source of the second enhancement mode transistor 103 to the third source of the first enhancement mode transistor 102, and the bidirectional III-V depletion-mode high electron mobility transistor 101 is turned on. Due to the presence of a body diode in the turned-off second enhancement mode transistor 103, the turn-on voltage of the bidirectional normally closed switch 10 is offset, and the operating characteristics of the bidirectional normally closed switch 10 are similar to those of a diode; if the voltage difference between the fourth source of the second enhancement mode transistor 103 and the third source of the first enhancement mode transistor 102 is less than zero, the bidirectional normally closed switch 10 blocks the current.

[0072] Optionally, when the first enhancement mode transistor 102 is turned off and the second enhancement mode transistor 103 is turned on, if the voltage difference between the fourth source of the second enhancement mode transistor 103 and the third source of the first enhancement mode transistor 102 is greater than zero, the bidirectional normally closed switch 10 blocks the current; if the voltage difference between the fourth source of the second enhancement mode transistor 103 and the third source of the first enhancement mode transistor 102 is less than zero, the current in the bidirectional normally closed switch 10 flows from the third source of the first enhancement mode transistor 102 to the fourth source of the second enhancement mode transistor 103, and the bidirectional III-V depletion-mode high electron mobility transistor 101, due to the presence of a body diode in the turned-off first enhancement mode transistor 102, the turn-on voltage of the bidirectional normally closed switch 10 is offset, and the working characteristics of the bidirectional normally closed switch 10 are similar to those of a diode.

[0073] In an embodiment of the present application, a bidirectional normally closed transistor is formed by a bidirectional III-V depletion-type high electron mobility transistor, a first enhancement-type transistor, and a second enhancement-type transistor, wherein the third drain of the first enhancement-type transistor is connected to the first source / drain node of the bidirectional III-V depletion-type high electron mobility transistor, the third source of the first enhancement-type transistor is connected to the first gate of the bidirectional III-V depletion-type high electron mobility transistor, and the third gate of the first enhancement-type transistor is connected to an external first control source; the fourth drain of the second enhancement-type transistor is connected to the second source / drain node of the bidirectional III-V depletion-type high electron mobility transistor, and the fourth drain of the second enhancement-type transistor is connected to the second source / drain node of the bidirectional III-V depletion-type high electron mobility transistor. The fourth source of the body tube is connected to the second gate of the bidirectional III-V depletion-type high electron mobility transistor, the fourth gate of the second enhancement-type transistor is connected to the external second control source, the first enhancement-type transistor and the second enhancement-type transistor are cascaded with the bidirectional III-V depletion-type high electron mobility transistor, the first control source controls the gate-source voltage between the third gate and the third source of the first enhancement-type transistor, the second control source controls the gate-source voltage between the fourth gate and the fourth source of the second enhancement-type transistor, and the bidirectional III-V depletion-type high electron mobility transistor enters the on or off state under the gate-source voltage of the first enhancement-type transistor and the gate-source voltage of the second enhancement-type transistor. In addition, the substrate of the bidirectional III-V depletion-type high electron mobility transistor is an insulating substrate, which can effectively avoid the back-gate effect. In this way, the control circuit of the bidirectional normally closed switch can be simplified and the back-gate effect can be avoided.

[0074] As an optional implementation, the bidirectional III-V depletion-mode high electron mobility transistor 101 includes: a first substrate 1011 , which is an insulating substrate; the first enhancement-mode transistor 102 includes: a second substrate 1021 ; and the second enhancement-mode transistor 103 includes: a third substrate 1031 .

[0075] Optionally, the bidirectional III-V depletion-type high electron mobility transistor 101 includes: a channel layer, a buffer layer and a first substrate 1011. The first substrate 1011 of the bidirectional III-V depletion-type high electron mobility transistor 101 is an insulating substrate. The first substrate 1011 is an insulating substrate, which can effectively avoid the back gate effect caused by the floating of the non-insulating substrate. Among them, the gate of the bidirectional III-V depletion-type high electron mobility transistor 101 adopts a field plate design, and the field plate design of the gate can effectively reduce the current collapse problem of the bidirectional normally closed switch 10.

[0076] The second substrate 1021 and the third substrate 1031 are the same substrate.

[0077] Optionally, the first enhancement-mode transistor 102 and the second enhancement-mode transistor 103 both have a channel layer and a buffer layer, wherein the substrate materials of the first enhancement-mode transistor 102 and the second enhancement-mode transistor 103 are the same, the second substrate 1021 of the first enhancement-mode transistor 102 and the third substrate 1031 of the second enhancement-mode transistor 103 are both insulating materials, or the second substrate 1021 of the first enhancement-mode transistor 102 and the third substrate 1031 of the second enhancement-mode transistor 103 are both non-insulating materials.

[0078] As an optional implementation, the second substrate 1021 and the third substrate 1031 are both insulating substrates.

[0079] Optionally, when the first substrate 1011, the second substrate 1021 and the third substrate 1031 are all insulating substrates, the first enhancement mode transistor 102, the second enhancement mode transistor 103 and the bidirectional III-V depletion mode high electron mobility transistor 101 can be integrated into a monolithic bidirectional normally closed switch 10, and the monolithic bidirectional normally closed switch 10 can share a channel layer, a buffer layer and an insulating substrate. It is worth noting that the insulating substrate refers to a transistor substrate filled with an insulating material.

[0080] Alternatively, the second substrate 1021 and the third substrate 1031 are both non-insulating substrates.

[0081] Optionally, the second substrate 1021 of the first enhancement-mode transistor 102 and the third substrate 1031 of the second enhancement-mode transistor 103 can be non-insulating substrates. If the second substrate 1021 of the first enhancement-mode transistor 102 and the third substrate 1031 of the second enhancement-mode transistor 103 are both non-insulating substrates, the first enhancement-mode transistor 102, the second enhancement-mode transistor 103 and the bidirectional III-V depletion-mode high electron mobility transistor 101 can be integrated into a discrete bidirectional normally closed switch 10.

[0082] As an optional implementation, Figure 5For the connection diagram of the second bidirectional normally closed switch provided in this application, see Figure 5 In the bidirectional normally closed switch 10 provided in the embodiment of the present application, the third gate of the first enhancement mode transistor 102 and the first gate of the bidirectional III-V depletion mode high electron mobility transistor 101 share the first control source 20, and the fourth gate of the second enhancement mode transistor 103 and the second gate of the bidirectional III-V depletion mode high electron mobility transistor 101 share the second control source 21. Among them, the third gate of the first enhancement mode transistor 102 is connected to the first control node of the first control source 20, and the first gate of the bidirectional III-V depletion type high electron mobility transistor 101 is connected to the second control node of the first control source 20, that is, the third gate of the first enhancement mode transistor 102 and the first gate of the bidirectional III-V depletion type high electron mobility transistor 101 are connected to different control nodes of the first control source 20; the fourth gate of the second enhancement mode transistor 103 is connected to the third control node of the second control source 21, and the second gate of the bidirectional III-V depletion type high electron mobility transistor 101 is connected to the fourth control node of the second control source 21, that is, the fourth gate of the second enhancement mode transistor 103 and the second gate of the bidirectional III-V depletion type high electron mobility transistor 101 are connected to different control nodes of the second control source 21.

[0083] Optionally, the first control source 20 controls the voltage of the first gate of the bidirectional III-V depletion-type high electron mobility transistor 101, and the second control source 21 controls the voltage of the second gate of the bidirectional III-V depletion-type high electron mobility transistor 101, so as to control the on and off of the bidirectional normally closed switch 10. If the negative voltage of the first gate and / or the negative voltage of the second gate of the bidirectional III-V depletion-type high electron mobility transistor 101 is abnormal, and the bidirectional normally closed transistor cannot be turned off, the first control source 20 controls the first enhancement transistor 102 to be turned off, and the second control source 21 controls the second enhancement transistor 103 to be turned off, so that the bidirectional normally closed switch enters the safe mode. It is worth noting that the bidirectional normally closed switch 10 can only be turned off normally when the negative voltage of the gate of the bidirectional III-V depletion-type high electron mobility transistor 101 is normal.

[0084] As an optional implementation, Figure 6 For the connection diagram of the third bidirectional normally closed switch provided in this application, see Figure 6 The bidirectional normally closed switch 10 provided in the embodiment of the present application further includes a voltage divider circuit 104 , and the voltage divider circuit 104 includes: a first voltage divider circuit 1041 and a second voltage divider circuit 1042 .

[0085] Optionally, the voltage divider circuit 104 is used to stabilize the gate-source voltage of the bidirectional III-V depletion-type high electron mobility transistor 101, the first voltage divider circuit 1041 is used to stabilize the voltage between the first source / drain node and the first gate of the bidirectional III-V depletion-type high electron mobility transistor 101, and the second voltage divider circuit 1042 is used to stabilize the voltage between the second source / drain node and the second gate of the bidirectional III-V depletion-type high electron mobility transistor 101.

[0086] Optionally, when the first gate or the second gate of the bidirectional III-V depletion-type high electron mobility transistor 101 is turned off, the drain voltage of the first source / drain node or the second source / drain node of the bidirectional III-V depletion-type high electron mobility transistor 101 rises, and the voltage divider circuit 104 clamps the gate-source voltage of the bidirectional III-V depletion-type high electron mobility transistor 101 so that the terminal voltage at both ends of the first voltage divider circuit 1041 remains constant or the terminal voltage at both ends of the second voltage divider circuit 1042 remains constant, thereby ensuring that the gate-source voltage of the bidirectional III-V depletion-type high electron mobility transistor 101 remains unchanged.

[0087] One end of the first voltage divider circuit 1041 is respectively connected to the third drain of the first enhancement mode transistor 102 and the first source / drain node of the bidirectional III-V depletion mode high electron mobility transistor 101, and the other end of the first voltage divider circuit 1041 is respectively connected to the third source of the first enhancement mode transistor 102 and the first gate of the bidirectional III-V depletion mode high electron mobility transistor 101.

[0088] Optionally, the first voltage divider circuit 1041 can be regarded as being connected in parallel between the third source and the third drain of the first enhancement mode transistor 102, and can also be regarded as being connected in parallel between the first source / drain node and the first gate of the bidirectional III-V depletion type high electron mobility transistor 101. The first voltage divider circuit 1041 can clamp the gate-source voltage of the bidirectional III-V depletion type high electron mobility transistor 101 when the first gate of the bidirectional III-V depletion type high electron mobility transistor 101 is turned off and the voltage of the first source / drain node of the bidirectional III-V depletion type high electron mobility transistor 101 rises to the leakage limit.

[0089] Optionally, the first voltage divider circuit 1041 can not only clamp the gate-source voltage of the bidirectional III-V depletion-type high electron mobility transistor 101, but also compensate for the charge of the first enhancement transistor 102 when the charge stored in the first enhancement transistor 102 is lower than the charge stored in the first source / drain node of the bidirectional III-V depletion-type high electron mobility transistor 101, so as to suppress the capacitance mismatch problem between the bidirectional III-V depletion-type high electron mobility transistor 101 and the first enhancement transistor 102.

[0090] One end of the second voltage divider circuit 1042 is respectively connected to the fourth drain of the second enhancement mode transistor 103 and the second source / drain node of the bidirectional III-V depletion mode high electron mobility transistor 101, and the other end of the second voltage divider circuit 1042 is respectively connected to the fourth source of the second enhancement mode transistor 103 and the second gate of the bidirectional III-V depletion mode high electron mobility transistor 101.

[0091] Optionally, the second voltage divider circuit 1042 can be regarded as being connected in parallel between the fourth source and the fourth drain of the second enhancement mode transistor 103, and can also be regarded as being connected in parallel between the second source / drain node and the second gate of the bidirectional III-V depletion type high electron mobility transistor 101. The second voltage divider circuit 1042 can clamp the gate-source voltage of the bidirectional III-V depletion type high electron mobility transistor 101 when the second gate of the bidirectional III-V depletion type high electron mobility transistor 101 is turned off and the voltage of the second source / drain node of the bidirectional III-V depletion type high electron mobility transistor 101 rises to the leakage limit.

[0092] Optionally, the second voltage divider circuit 1042 can not only clamp the bidirectional III-V depletion-type high electron mobility transistor 101, but also compensate for the charge of the second enhancement transistor 103 when the charge stored in the second enhancement transistor 103 is lower than the charge stored in the second source / drain node of the bidirectional III-V depletion-type high electron mobility transistor 101, so as to suppress the capacitance mismatch problem between the bidirectional III-V depletion-type high electron mobility transistor 101 and the second enhancement transistor 103.

[0093] As an optional implementation, Figure 7 This is a schematic diagram of a voltage divider circuit in a bidirectional normally closed switch provided in the present application, see Figure 7 In the bidirectional normally closed switch 10 provided in the embodiment of the present application, the first voltage divider circuit 1041 includes: a first resistor 10411 , and the second voltage divider circuit 1042 includes: a second resistor 10421 .

[0094] Optionally, the voltage divider circuit 104 is implemented by non-polar electronic device resistors, wherein the first resistor 10411 is used to stabilize the voltage between the first source / drain node and the first gate of the bidirectional III-V depletion-type high electron mobility transistor 101, so that the terminal voltage at both ends of the first voltage divider circuit 1041 remains constant; the second resistor 10421 is used to stabilize the voltage between the second source / drain node and the second gate of the bidirectional III-V depletion-type high electron mobility transistor 101, so that the terminal voltage at both ends of the second voltage divider circuit 1042 remains constant.

[0095] One end of the first resistor 10411 is respectively connected to the third drain of the first enhancement mode transistor 102 and the first source / drain node of the bidirectional III-V depletion mode high electron mobility transistor 101, and the other end of the first resistor 10411 is respectively connected to the third source of the first enhancement mode transistor 102 and the first gate of the bidirectional III-V depletion mode high electron mobility transistor 101.

[0096] One end of the second resistor 10421 is respectively connected to the fourth drain of the second enhancement mode transistor 103 and the second source / drain node of the bidirectional III-V depletion mode high electron mobility transistor 101, and the other end of the second resistor 10421 is respectively connected to the fourth source of the second enhancement mode transistor 103 and the second gate of the bidirectional III-V depletion mode high electron mobility transistor 101.

[0097] As an optional implementation, Figure 8 This is a structural schematic diagram of another voltage divider circuit in a bidirectional normally closed switch provided in the present application, see Figure 8 In the bidirectional normally closed switch 10 provided in the embodiment of the present application, the first voltage divider circuit 1041 includes: a first resistor 10411 and a first capacitor 10412 , and the second voltage divider circuit 1042 includes: a second resistor 10421 and a second capacitor 10422 .

[0098] Optionally, the voltage divider circuit 104 is realized by a non-polar electronic device resistor and a capacitor in parallel, wherein the first voltage divider circuit 1041 is realized by a first resistor 10411 and a first capacitor 10412, and the first resistor 10411 and the first capacitor 10412 are connected in parallel to form the first voltage divider circuit 1041; the second voltage divider circuit 1042 is realized by a second resistor 10421 and a second capacitor 10422, and the second resistor 10421 and the second capacitor 10422 are connected in parallel to form the second voltage divider circuit 1042.

[0099] Optionally, the first resistor 10411 is used to stabilize the voltage between the first source / drain node and the first gate of the bidirectional III-V depletion-type high electron mobility transistor 101 so that the terminal voltage at both ends of the first voltage divider circuit 1041 remains constant, and the first capacitor 10412 is used to cache the redundant charge between the bidirectional III-V depletion-type high electron mobility transistor 101 and the first enhancement-type transistor 102 to solve the capacitance mismatch problem between the bidirectional III-V depletion-type high electron mobility transistor 101 and the first enhancement-type transistor 102.

[0100] Optionally, the second resistor 10421 is used to stabilize the voltage between the second source / drain node and the second gate of the bidirectional III-V depletion-type high electron mobility transistor 101 so that the terminal voltage at both ends of the second voltage divider circuit 1042 remains constant, and the second capacitor 10422 is used to cache the redundant charge between the bidirectional III-V depletion-type high electron mobility transistor 101 and the second enhancement-type transistor 103 to solve the capacitance mismatch problem between the bidirectional III-V depletion-type high electron mobility transistor 101 and the second enhancement-type transistor 103.

[0101] One end of the first resistor 10411 and one end of the first capacitor 10412 are connected to the third drain of the first enhancement mode transistor 102 and the first source / drain node of the bidirectional III-V depletion mode high electron mobility transistor 101, and the other end of the first resistor 10411 and the other end of the first capacitor 10412 are connected to the third source of the first enhancement mode transistor 102 and the first gate of the bidirectional III-V depletion mode high electron mobility transistor 101.

[0102] Optionally, the first capacitor 10412 can be regarded as a compensation capacitor between the first enhancement-mode transistor 102 and the bidirectional III-V depletion-mode high electron mobility transistor 101. When the amount of charge stored in the first enhancement-mode transistor 102 is lower than the amount of charge stored in the first source / drain node of the bidirectional III-V depletion-mode high electron mobility transistor 101, the charge of the first enhancement-mode transistor 102 is compensated via the first capacitor 10412.

[0103] Optionally, the capacitance of the first capacitor 10412 can be set according to the difference between the amount of charge stored at the first source / drain node of the bidirectional III-V depletion-mode high electron mobility transistor 101 and the amount of charge stored in the first enhancement-mode transistor 102. The first capacitor 10412 is connected in parallel with the third source and the third drain of the first enhancement-mode transistor 102 to compensate for the charge of the first enhancement-mode transistor 102.

[0104] One end of the second resistor 10421 and one end of the second capacitor 10422 are connected to the fourth drain of the second enhancement mode transistor 103 and the second source / drain node of the bidirectional III-V depletion mode high electron mobility transistor 101, and the other end of the second resistor 10421 and the other end of the second capacitor 10422 are connected to the fourth source of the second enhancement mode transistor 103 and the second gate of the bidirectional III-V depletion mode high electron mobility transistor 101.

[0105] Optionally, the second capacitor 10422 can be regarded as a compensation capacitor between the second enhancement-mode transistor 103 and the bidirectional III-V depletion-mode high electron mobility transistor 101. When the amount of charge stored in the second enhancement-mode transistor 103 is lower than the amount of charge stored in the second source / drain node of the second enhancement-mode transistor 103, the charge of the second enhancement-mode transistor 103 is compensated via the second capacitor 10422.

[0106] Optionally, the capacitance of the second capacitor 10422 can be set according to the difference between the amount of charge stored at the second source / drain node of the bidirectional III-V depletion-mode high electron mobility transistor 101 and the amount of charge stored in the second enhancement-mode transistor 103, and the second capacitor 10422 is connected in parallel with the fourth source and the fourth drain of the second enhancement-mode transistor 103 to compensate for the charge of the second enhancement-mode transistor 103.

[0107] As an optional implementation, Fig. 9 A schematic diagram of the structure of a monolithic bidirectional normally closed switch provided in this application, see Fig. 9 In the bidirectional normally closed switch 10 provided in the embodiment of the present application, the first enhancement mode transistor 102, the second enhancement mode transistor 103 and the bidirectional III-V depletion mode high electron mobility transistor 101 share a channel layer, a buffer layer and an insulating substrate.

[0108] As an optional implementation, Fig.10 A schematic diagram of a discrete bidirectional normally closed switch provided in this application, see Fig.10 In a discrete bidirectional normally closed switch 10 provided in an embodiment of the present application, the second substrate 1021 of the first enhancement mode transistor 102 and the third substrate 1031 of the second enhancement mode transistor 103 may be an insulating substrate or a non-insulating substrate.

[0109] As an optional implementation, Fig.11 This is a connection diagram of the first monolithic bidirectional normally closed switch provided in this application, see Fig.11 The bidirectional normally closed switch 10 provided in the embodiment of the present application includes a first control source 20 and a second control source 21, wherein the third gate of the first enhancement mode transistor 102 is connected to the first control node of the first control source 20, and the first gate of the bidirectional III-V depletion mode high electron mobility transistor 101 is connected to the second control node of the first control source 20.

[0110] Optionally, the first enhancement-mode transistor 102 shares a first control source 20 with the bidirectional III-V depletion-mode high electron mobility transistor 101, the third gate of the first enhancement-mode transistor 102 is coupled to the first control node of the first control source 20, the first gate of the bidirectional III-V depletion-mode high electron mobility transistor 101 is coupled to the second control node of the first control source 20, and the first control source 20 can control both the gate-source voltage of the first enhancement-mode transistor 102 and the gate-source voltage between the first source / drain node and the first gate of the bidirectional III-V depletion-mode high electron mobility transistor 101.

[0111] The fourth gate of the second enhancement mode transistor 103 is connected to the third control node of the second control source 21 , and the second gate of the bidirectional III-V depletion mode high electron mobility transistor 101 is connected to the fourth control node of the second control source 21 .

[0112] Optionally, the second enhancement mode transistor 103 shares the second control source 21 with the bidirectional III-V depletion mode high electron mobility transistor 101, the fourth gate of the second enhancement mode transistor 103 is coupled to the third control node of the second control source 21, the second gate of the bidirectional III-V depletion mode high electron mobility transistor 101 is coupled to the fourth control node of the second control source 21, and the second control source 21 can control both the gate-source voltage of the second enhancement mode transistor 103 and the gate-source voltage between the second source / drain node and the second gate of the bidirectional III-V depletion mode high electron mobility transistor 101.

[0113] The first control source 20 controls the gate-source voltage of the first enhancement mode transistor 102 , and the second control source 21 controls the gate-source voltage of the second enhancement mode transistor 103 , so as to control the on-off of the bidirectional III-V depletion mode high electron mobility transistor 101 .

[0114] Optionally, the gate-source voltage of the first enhancement mode transistor 102 is used to indicate the voltage value between the third gate and the third source of the first enhancement mode transistor 102 , and the gate-source voltage of the second enhancement mode transistor 103 is used to indicate the voltage value between the fourth gate and the fourth source of the second enhancement mode transistor 103 .

[0115] As an optional implementation, Fig.12 The connection diagram of the second monolithic bidirectional normally closed switch provided in this application is shown in FIG. Fig.12 The bidirectional normally closed switch 10 provided in the embodiment of the present application includes a first control source 20, a second control source 21, a third control source 22 and a fourth control source 23, wherein the third gate of the first enhancement mode transistor 102 is connected to the first control source 20, and the first gate of the bidirectional III-V depletion mode high electron mobility transistor 101 is connected to the external third control source 22.

[0116] Optionally, the first control source 20 is used to control the gate-source voltage of the first enhancement mode transistor 102 to control the on-off of the first enhancement mode transistor 102; the third control source 22 is used to control the gate-source voltage between the first gate and the first source / drain node of the bidirectional III-V depletion mode high electron mobility transistor 101, thereby controlling the on-off of the first gate of the bidirectional III-V depletion mode high electron mobility transistor 101.

[0117] The fourth gate of the second enhancement mode transistor 103 is connected to the second control source 21 , and the second gate of the bidirectional III-V depletion mode high electron mobility transistor 101 is connected to the external fourth control source 23 .

[0118] Optionally, the second control source 21 is used to control the gate-source voltage of the second enhancement mode transistor 103 to control the on and off of the second enhancement mode transistor 103; the fourth control source 23 is used to control the gate-source voltage between the second gate and the second source / drain node of the bidirectional III-V depletion mode high electron mobility transistor 101, thereby controlling the on and off of the second gate of the bidirectional III-V depletion mode high electron mobility transistor 101.

[0119] The third control source 22 and the fourth control source 23 directly control the on-off of the bidirectional III-V depletion-mode high electron mobility transistor 101 , the first control source 20 controls the on-off of the first enhancement-mode transistor 102 , and the second control source 21 controls the on-off of the second enhancement-mode transistor 103 .

[0120] Optionally, the first control source 20 , the second control source 21 , the third control source 22 and the fourth control source 23 are four independent control sources, and the controls among the first control source 20 , the second control source 21 , the third control source 22 and the fourth control source 23 do not interfere with each other.

[0121] As an optional implementation, Fig.13 The connection diagram of the third monolithic bidirectional normally closed switch provided in this application is shown in FIG. Fig.13 In the bidirectional normally closed switch 10 provided in the embodiment of the present application, the third source of the first enhancement mode transistor 102 is connected to the first gate of the bidirectional III-V depletion type high electron mobility transistor 101, and the first source / drain node of the bidirectional III-V depletion type high electron mobility transistor 101 and the third drain of the first enhancement mode transistor 102 are connected to the first gate of the bidirectional III-V depletion type high electron mobility transistor 101 via the first voltage divider circuit 1041.

[0122] In addition, the fourth source of the second enhancement mode transistor 103 is connected to the second gate of the bidirectional III-V depletion type high electron mobility transistor 101, and the second source / drain node of the bidirectional III-V depletion type high electron mobility transistor 101 and the fourth drain of the second enhancement mode transistor 103 are connected to the second gate of the bidirectional III-V depletion type high electron mobility transistor 101 via the second voltage divider circuit 1042.

[0123] Optionally, the bidirectional III-V depletion mode high electron mobility transistor 101 controls the on / off of the first gate and the second gate of the bidirectional III-V depletion mode high electron mobility transistor 101 based on the on / off of the first enhancement mode transistor 102 and the on / off of the second enhancement mode transistor 103 .

[0124] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0125] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A bidirectional normally closed switch, characterized in that: The bidirectional normally closed switch comprises: a bidirectional III-V depletion-mode high electron mobility transistor, a first enhancement-mode transistor and a second enhancement-mode transistor, the bidirectional III-V depletion-mode high electron mobility transistor comprises: a first source / drain node, a second source / drain node, a first gate and a second gate, the first enhancement-mode transistor comprises: a third source, a third drain and a third gate, the second enhancement-mode transistor comprises: a fourth source, a fourth drain and a fourth gate; The third drain of the first enhancement mode transistor is connected to the first source / drain node of the bidirectional III-V depletion mode high electron mobility transistor, and the third source of the first enhancement mode transistor is connected to the first gate of the bidirectional III-V depletion mode high electron mobility transistor; The fourth drain of the second enhancement mode transistor is connected to the second source / drain node of the bidirectional III-V depletion mode high electron mobility transistor, and the fourth source of the second enhancement mode transistor is connected to the second gate of the bidirectional III-V depletion mode high electron mobility transistor; The third gate of the first enhancement mode transistor is connected to an external first control source, and the gate-source voltage of the first enhancement mode transistor is controlled by the first control source. The fourth gate of the second enhancement mode transistor is connected to an external second control source, and the gate-source voltage of the second enhancement mode transistor is controlled by the second control source.

2. The bidirectional normally closed switch according to claim 1, characterized in that: The bidirectional III-V depletion-mode high electron mobility transistor comprises: a first substrate, the first substrate is an insulating substrate, the first enhancement-mode transistor comprises: a second substrate, and the second enhancement-mode transistor comprises: a third substrate; The second substrate and the third substrate are the same substrate.

3. The bidirectional normally closed switch according to claim 2, characterized in that: The second substrate and the third substrate are both insulating substrates; Alternatively, both the second substrate and the third substrate are non-insulating substrates.

4. The bidirectional normally closed switch according to claim 2, characterized in that: The third gate of the first enhancement mode transistor is connected to the first control node of the first control source, and the first gate of the bidirectional III-V depletion mode high electron mobility transistor is connected to the second control node of the first control source; The fourth gate of the second enhancement mode transistor is connected to the third control node of the second control source, and the second gate of the bidirectional III-V depletion mode high electron mobility transistor is connected to the fourth control node of the second control source; The first control source controls the voltage of the first gate, the second control source controls the voltage of the second gate, and when the negative voltage of the first gate and / or the second gate is abnormal and the bidirectional normally closed transistor cannot be turned off, the first control source controls the first enhancement transistor to be turned off, and the second control source controls the second enhancement transistor to be turned off, so that the bidirectional normally closed switch enters a safe mode.

5. The bidirectional normally closed switch according to claim 2, characterized in that: The third gate of the first enhancement mode transistor is connected to the first control source, and the first gate of the bidirectional III-V depletion mode high electron mobility transistor is connected to an external third control source; The fourth gate of the second enhancement mode transistor is connected to the second control source, and the second gate of the bidirectional III-V depletion mode high electron mobility transistor is connected to an external fourth control source; The third control source and the fourth control source directly control the on-off of the bidirectional III-V depletion-mode high electron mobility transistor, the first control source controls the on-off of the first enhancement-mode transistor, and the second control source controls the on-off of the second enhancement-mode transistor.

6. The bidirectional normally closed switch according to claim 1, characterized in that: The bidirectional normally closed switch further comprises: a voltage dividing circuit, the voltage dividing circuit comprising: a first voltage dividing circuit and a second voltage dividing circuit; One end of the first voltage divider circuit is respectively connected to the third drain of the first enhancement mode transistor and the first source / drain node of the bidirectional III-V depletion mode high electron mobility transistor, and the other end of the first voltage divider circuit is respectively connected to the third source of the first enhancement mode transistor and the first gate of the bidirectional III-V depletion mode high electron mobility transistor; One end of the second voltage divider circuit is respectively connected to the fourth drain of the second enhancement mode transistor and the second source / drain node of the bidirectional III-V depletion mode high electron mobility transistor, and the other end of the second voltage divider circuit is respectively connected to the fourth source of the second enhancement mode transistor and the second gate of the bidirectional III-V depletion mode high electron mobility transistor.

7. The bidirectional normally closed switch according to claim 6, characterized in that: The first voltage divider circuit includes: a first resistor, and the second voltage divider circuit includes: a second resistor; One end of the first resistor is respectively connected to the third drain of the first enhancement mode transistor and the first source / drain node of the bidirectional III-V depletion mode high electron mobility transistor, and the other end of the first resistor is respectively connected to the third source of the first enhancement mode transistor and the first gate of the bidirectional III-V depletion mode high electron mobility transistor; One end of the second resistor is respectively connected to the fourth drain of the second enhancement transistor and the second source / drain node of the bidirectional III-V depletion-mode high electron mobility transistor, and the other end of the second resistor is respectively connected to the fourth source of the second enhancement transistor and the second gate of the bidirectional III-V depletion-mode high electron mobility transistor.

8. The bidirectional normally closed switch according to claim 6, characterized in that: The first voltage divider circuit includes: a first resistor and a first capacitor, and the second voltage divider circuit includes: a second resistor and a second capacitor; One end of the first resistor and one end of the first capacitor are both connected to the third drain of the first enhancement mode transistor and the first source / drain node of the bidirectional III-V depletion mode high electron mobility transistor, and the other end of the first resistor and the other end of the first capacitor are both connected to the third source of the first enhancement mode transistor and the first gate of the bidirectional III-V depletion mode high electron mobility transistor; One end of the second resistor and one end of the second capacitor are connected to the fourth drain of the second enhancement transistor and the second source / drain node of the bidirectional III-V depletion-mode high electron mobility transistor, and the other end of the second resistor and the other end of the second capacitor are connected to the fourth source of the second enhancement transistor and the second gate of the bidirectional III-V depletion-mode high electron mobility transistor.

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