Level shifter for eliminating static power consumption

Abstract

The invention discloses a level shifter for eliminating static power consumption. In order to eliminate static power consumption in the level converter, the level conversion circuit comprises a first phase inverter, an input end of the first phase inverter is connected with a level converter input signal, and the first phase inverter is connected with a first power supply voltage and a first ground voltage; the output end of the first phase inverter serves as the input end of the second phase inverter, and the first power supply voltage and the second ground voltage are connected to the second phase inverter; the output end of the second phase inverter serves as the input end of the first module, the output end of the second phase inverter is connected to the grid electrode of the third NMOS tube, and the output end of the first module is connected to the grid electrode of the third PMOS tube; the drain electrode of the third PMOS tube leads out an output signal of the level converter, and the output signal of the level converter is used as an input signal of the first module; the source electrode of the third PMOS tube is connected to a second power supply voltage, and the source electrode of the third NMOS tube is connected to a second ground voltage. The invention also has a wide conversion range and no overpressure risk.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to a level shifter for eliminating static power consumption. Background Art

[0002] In chip applications, there are various different power supply voltages and ground voltages. A level shifter is a circuit used to convert the level of a signal from one logic or voltage level to another logic or voltage level. It realizes signal compatibility and interconnection between different circuits, enabling devices with different levels to communicate and interact with each other.

[0003] The working principle of a level shifter is based on technologies such as voltage comparison, driving, and logic conversion. It changes the conduction state through an internal circuit structure (such as transistors, MOSFETs, etc.) to control the current flow and voltage level at the output end, ensuring that the output signal meets the logic high and logic low level requirements of the target system.

[0004] Level shifters are widely used in fields such as digital circuits, communication interfaces, and sensor interfaces. For example, in digital circuits, different chips or systems may operate with different power supply voltages, and a level shifter can adjust the signal level so that the output end can match the logic threshold of the target system.

[0005] Figure 1 It is the circuit diagram of the first level shifter in the prior art. Through the first inverter composed of a P-channel Metal Oxide Semiconductor (PMOS) transistor P1 and an N-channel Metal Oxide Semiconductor (NMOS) transistor N1, and the second inverter composed of a PMOS transistor P2 and an NMOS transistor N2, the level shifter receives an input signal IN and generates a converted output signal OUT. The first inverter is connected to a first power supply voltage with a voltage value of VDDL and a first ground voltage with a voltage value of VSSL, and the second inverter is connected to a second power supply voltage with a voltage value of VDDH and a second ground voltage with a voltage value of VSSH, where VDDL < VDDH and VSSL < VSSH, and there is a connection node A between the first inverter and the second inverter. The defect of this solution is that when the voltage value of node A is VDDL, there is a risk that the PMOS transistor P2 cannot be completely turned off, resulting in static power consumption. When the deviation between VDDH and VDDL is relatively large, the overall power consumption is relatively large.

[0006] Figure 2This is the second level converter circuit diagram in the prior art. The main difference from the first level converter is that a capacitor is used as a connecting device between the first inverter and the second inverter, and a resistor is connected between the common gate and the common drain of the PMOS tube P2 and the NMOS tube N1. From node B0 to node B1, the AC signal is coupled to the high voltage domain through the capacitor. When the frequency of the input signal IN is low, the coupling process has signal amplitude attenuation, resulting in signal distortion, so the signal applicable to this solution has a frequency lower limit. Summary of the invention

[0007] In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows: A level converter for eliminating static power consumption comprises: a first inverter, wherein the input end of the first inverter is connected to a level converter input signal, and the first inverter is connected to a first power supply voltage and a first ground voltage; a second inverter, wherein the output end of the first inverter is used as the input end of the second inverter, and the second inverter is connected to the first power supply voltage and the second ground voltage; and the output end of the second inverter is used as the input end of the first module, the output end of the second inverter is connected to the gate of a third NMOS tube, and the output end of the first module is connected to the gate of a third PMOS tube; the drain of the third PMOS tube leads to the output signal of the level converter, and the output signal of the level converter is used as the input signal of the first module; the source of the third PMOS tube is connected to the second power supply voltage, and the source of the third NMOS tube is connected to the second ground voltage; in addition, the first module comprises a third inverter, a fourth NMOS tube, a fifth NMOS tube and an XNO R circuit; and, the level converter output signal is used as the input signal of the third inverter; the level converter output signal is used as the first input signal of the XNOR circuit; the level converter output signal is used as the gate control signal of the fifth NMOS tube; the output signal of the output end of the second inverter is used as the second input signal of the XNOR circuit; the output signal of the output end of the second inverter is used as the source input signal of the fifth NMOS tube; the drain of the fifth NMOS tube is led out to the output end of the first module; the output end of the third inverter is connected to the drain of the fourth NMOS tube and the drain of the fifth NMOS tube, the gate of the fourth NMOS tube is connected to the output end of the XNOR circuit, and the source of the fourth NMOS tube is connected to the second ground voltage; wherein the voltage value of the second ground voltage is greater than the voltage value of the first ground voltage, and the voltage value of the second power supply voltage is greater than the voltage value of the first power supply voltage.

[0008] Furthermore, the first inverter includes a first PMOS tube and a first NMOS tube, wherein a source of the first PMOS tube is connected to a first power supply voltage, and a source of the first NMOS tube is connected to a first ground voltage.

[0009] Furthermore, the second inverter includes a second PMOS tube and a second NMOS tube, wherein the source of the second PMOS tube is connected to the first power supply voltage, and the source of the second NMOS tube is connected to the second ground voltage.

[0010] Further, the voltage variation range of the output terminal of the XNOR circuit is from the voltage value of the second ground voltage to the voltage value of the first power supply voltage.

[0011] Further, the voltage variation range of the output end of the first module is from the voltage value of the second ground voltage to the voltage value of the second power supply voltage.

[0012] Furthermore, the gate of the first PMOS tube and the gate of the first NMOS tube are connected to the input signal of the level converter.

[0013] Furthermore, the gate of the second PMOS tube and the gate of the second NMOS tube are connected to the output end of the first inverter.

[0014] The technical solution of the present invention has one or more of the following beneficial technical effects: (1) Adapt to a wide power supply voltage conversion range; (2) No overpressure risk; (3) No static power consumption loss; (4) Supports a wide operating frequency range and has no lower operating frequency limit.

[0015] In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is the first level converter circuit diagram in the prior art; Figure 2 It is the second level converter circuit diagram in the prior art; Figure 3 is a circuit diagram of a level converter of the present invention; Figure 4 It is a circuit diagram of the first module of the present invention. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

[0019] Figure 3 The level converter circuit diagram of the present invention is shown in FIG. The level converter can be divided into three levels of circuits: a first level circuit, a second level circuit and a third level circuit.

[0020] The first stage circuit is a first inverter composed of a PMOS tube P1 and an NMOS tube N1. The first inverter is connected to a first power supply voltage with a voltage value of VDDL and a first ground voltage with a voltage value of VSSL. The first inverter has an output terminal C0. The input terminal of the first inverter is connected to a level converter input signal IN. The first inverter includes a first PMOS tube and a first NMOS tube, wherein the source of the first PMOS tube is connected to the first power supply voltage, and the source of the first NMOS tube is connected to the first ground voltage. The gate of the first PMOS tube and the gate of the first NMOS tube are connected to the level converter input signal.

[0021] The second stage circuit is a second inverter, including a PMOS tube P2 and an NMOS tube N2. The output terminal C0 of the first inverter serves as the input terminal of the second inverter, that is, the gate of the second PMOS tube and the gate of the second NMOS tube. The second inverter is connected to a first power supply voltage with a voltage value of VDDL and a second ground voltage with a voltage value of VSSH, and the second inverter has an output terminal C1. The second inverter includes a second PMOS tube and a second NMOS tube, wherein the source of the second PMOS tube is connected to the first power supply voltage, and the source of the second NMOS tube is connected to the second ground voltage.

[0022] The third stage circuit includes a first module, a PMOS transistor P3 and an NMOS transistor N3. The output terminal C1 of the second inverter serves as the input terminal of the first module, and the output terminal C1 of the second inverter is connected to the gate of the NMOS transistor N3.

[0023] The source of the PMOS transistor P3 is connected to the second power supply voltage with a voltage value of VDDH, the gate of the PMOS transistor P3 is connected to the output terminal C2 of the first module, and the drain of the PMOS transistor P3 leads to the output signal OUT of the level converter.

[0024] The drain of the PMOS tube P3 is connected to the drain of the NMOS tube N3 , and the source of the NMOS tube N3 is connected to the second ground voltage whose voltage value is VSSH.

[0025] In addition, the first module also receives the level converter output signal OUT as an input signal.

[0026] In the present invention, VSSH>VSSL, and VDDH>VDDL.

[0027] Figure 4 The circuit diagram of the first module of the present invention is shown in FIG. The level converter output signal OUT is used as the input signal of the third inverter, and also as the first input signal of the XNOR circuit, and also as the gate control signal of the NMOS tube N5.

[0028] The output signal of the output terminal C1 of the second inverter is used as the second input signal of the XNOR circuit and as the source input signal of the NMOS transistor N5. The drain of the NMOS transistor N5 leads to the output terminal C2 of the first module.

[0029] The output end of the third inverter is connected to the drain of the NMOS tube N4 and the drain of the NMOS tube N5, the gate of the NMOS tube N4 is connected to the output end of the XNOR circuit, and the source of the NMOS tube N4 is connected to the second ground voltage with a voltage value of VSSH.

[0030] In the present invention, the voltage variation range of the output terminal C1 of the second inverter is VSSH to VDDL, the voltage variation range of the output terminal C2 of the first module is VSSH to VDDH, and the voltage variation range of the output terminal of the XNOR circuit is VSSH to VDDL.

[0031] In the present invention, the flipping of the signal in the PMOS tube P3 and the NMOS tube N3 depends on the feedback control of the level converter output signal OUT, and does not depend on the driving capability of the PMOS tube P2 and the NMOS tube N2, and can adapt to the scene with a large voltage difference between VDDL and VDDH.

[0032] In the present invention, the output terminal C2 of the first module controls the gate of the PMOS tube P3 to complete the normal signal level conversion process without generating static power consumption.

[0033] When the level converter input signal IN is a high level with a voltage value of VDDL, the voltage value output by the output terminal C0 of the first inverter is VSSL, the voltage value output by the output terminal C1 of the second inverter is VDDL, the PMOS tube N3 is turned on, and the voltage value of the level converter output signal OUT is VSSH. Further, the NMOS tube N5 is turned off, and the third inverter makes the voltage value output by the output terminal C2 of the first module be VDDH, and the PMOS tube P3 is turned off. Thus, the level conversion function is realized without static power consumption.

[0034] When the voltage value of the level converter input signal IN is a low level of VSSL, the voltage value output by the output terminal C0 of the first inverter is VDDL, the voltage value output by the output terminal C1 of the second inverter is VSSH, and the PMOS tube N3 is turned off. If the voltage value of the level converter output signal OUT is VSSH, the XNOR circuit turns on the NMOS tube N4, the third inverter turns on the voltage value output by the output terminal C2 of the first module, and the PMOS tube P3 is turned on. If the voltage value of the level converter output signal OUT is VDDH, the third inverter turns on the voltage value output by the output terminal C2 of the first module, and the PMOS tube P3 is also turned on. In this way, the level conversion function is realized without static power consumption.

[0035] Furthermore, during the above working process, all PMOS tubes and all NMOS tubes operate within a safe voltage range without the risk of overvoltage.

[0036] In order to better illustrate the present invention, numerous specific details are provided in the above specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

[0037] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A level converter for eliminating static power consumption, characterized in that: include: A first inverter, wherein an input terminal of the first inverter is connected to an input signal of the level converter, and the first inverter is connected to a first power supply voltage and a first ground voltage; A second inverter, wherein the output terminal of the first inverter serves as the input terminal of the second inverter, and the second inverter is connected to a first power supply voltage and a second ground voltage; and The output end of the second inverter is used as the input end of the first module, the output end of the second inverter is connected to the gate of the third NMOS tube, and the output end of the first module is connected to the gate of the third PMOS tube; The drain of the third PMOS tube leads to an output signal of the level converter, and the output signal of the level converter is used as an input signal of the first module; The source of the third PMOS tube is connected to the second power supply voltage, and the source of the third NMOS tube is connected to the second ground voltage; in addition, The first module includes a third inverter, a fourth NMOS transistor, a fifth NMOS transistor and an XNOR circuit; and, The level converter output signal is used as an input signal of the third inverter; The level converter output signal is used as a first input signal of the XNOR circuit; The level converter outputs a signal as a gate control signal of the fifth NMOS tube; An output signal of the output terminal of the second inverter is used as a second input signal of the XNOR circuit; The output signal of the output terminal of the second inverter is used as the source input signal of the fifth NMOS tube; The drain of the fifth NMOS tube leads to the output end of the first module; The output end of the third inverter is connected to the drain of the fourth NMOS tube and the drain of the fifth NMOS tube, the gate of the fourth NMOS tube is connected to the output end of the XNOR circuit, and the source of the fourth NMOS tube is connected to the second ground voltage; The voltage value of the second ground voltage is greater than the voltage value of the first ground voltage, and the voltage value of the second power supply voltage is greater than the voltage value of the first power supply voltage.

2. The level converter for eliminating static power consumption according to claim 1, characterized in that: The first inverter includes a first PMOS tube and a first NMOS tube, wherein the source of the first PMOS tube is connected to a first power supply voltage, and the source of the first NMOS tube is connected to a first ground voltage.

3. The level converter for eliminating static power consumption according to claim 2, characterized in that: The second inverter includes a second PMOS tube and a second NMOS tube, wherein the source of the second PMOS tube is connected to the first power supply voltage, and the source of the second NMOS tube is connected to the second ground voltage.

4. The level converter for eliminating static power consumption according to claim 3, characterized in that: The voltage variation range of the output terminal of the XNOR circuit is from the voltage value of the second ground voltage to the voltage value of the first power supply voltage.

5. The level converter for eliminating static power consumption according to claim 4, characterized in that: The voltage variation range of the output terminal of the first module is from the voltage value of the second ground voltage to the voltage value of the second power supply voltage.

6. The level converter for eliminating static power consumption according to claim 5, characterized in that: The gate of the first PMOS tube and the gate of the first NMOS tube are connected to the input signal of the level converter.

7. The level converter for eliminating static power consumption according to claim 6, characterized in that: The gate of the second PMOS tube and the gate of the second NMOS tube are connected to the output end of the first inverter.

Images