Novel ferroelectric memory and preparation method thereof

Abstract

The invention provides a novel ferroelectric memory, and belongs to the technical field of semiconductors. The buffer layer is introduced between the source electrode and the channel layer to realize ohmic contact, and the tunneling layer is introduced between the drain electrode and the channel layer to realize tunneling contact. A buffer layer and a tunneling layer are respectively introduced between a source electrode and a channel layer and between a drain electrode and the channel layer of the ferroelectric memory, the novel ferroelectric memory is prepared, and a two-dimensional semiconductor / tunneling layer / metal tunnel junction is adopted as a channel. In the novel ferroelectric memory, the Fermi level of the two-dimensional semiconductor can be subjected to bipolar regulation and control through ferroelectric polarization, and regulation and control of the Fermi level can be sensitively detected through direct quantum tunneling current of a tunnel junction. A new hope is brought to logical devices, and a new solution is provided for high-density integration of the devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a novel ferroelectric memory and a preparation method thereof, and specifically to a novel ferroelectric memory using a "two-dimensional semiconductor / tunneling layer / metal" tunnel junction as a channel and a preparation method thereof. Background Art

[0002] With the popularization of data-intensive computing, the market demand for high-performance non-volatile storage solutions is growing. Although traditional silicon-based complementary metal oxide semiconductor (CMOS) technology has been successfully advanced to the sub-10nm process node, the further miniaturization of transistors is facing severe challenges. In response to this trend, new materials and technologies are emerging. Van der Waals layered two-dimensional semiconductors have attracted much attention due to their properties such as no dangling bonds and flexible stacking, and are expected to be a strong candidate for the next generation of transistor channel materials. At the same time, compared with traditional dielectric materials, ferroelectric materials can provide high-intensity localized electric fields at the interface, which can accurately and non-volatilely regulate the carrier concentration and band structure of the channel. Ferroelectric field-effect transistors based on ferroelectrics and two-dimensional materials open up new possibilities for the research and development of non-volatile memory devices.

[0003] The metal-semiconductor contact interface is a key factor affecting charge injection and transport and determining the performance of two-dimensional semiconductor devices. The contact interface between two-dimensional semiconductors and metals is usually not ideal, and often has defects such as atomic vacancies, molecular clusters and dislocations. These defects may capture carriers in the band gap to form defect levels, thereby leading to Fermi level pinning. How to further solve the contact problem between metal and semiconductor interfaces on the basis of meeting high-density integration is an important challenge to improve the performance of ferroelectric field-effect transistors.

[0004] So far, although a variety of technologies (electrode transfer, buffer layer, interface doping, edge contact, etc.) have been developed to solve the contact problem between metal and semiconductor, there are still huge challenges in obtaining high-performance complementary logic elements. Summary of the invention

[0005] In view of this, in order to solve the technical problem of the unsatisfactory contact interface between the two-dimensional semiconductor and the metal in the existing ferroelectric memory, on the one hand, the present invention provides a new ferroelectric memory, which is prepared by introducing a buffer layer and a tunneling layer between the source electrode, the drain electrode and the channel layer of the ferroelectric memory, and adopts a "two-dimensional semiconductor / tunneling layer / metal" tunnel junction as a channel. In the new ferroelectric memory, the Fermi level of the two-dimensional semiconductor can be bipolarly regulated by ferroelectric polarization, and the regulation of the Fermi level can be sensitively detected by the direct quantum tunneling current of the tunnel junction. It not only brings new hope for logic devices, but also provides a new solution for high-density integration of devices.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A novel ferroelectric memory introduces a buffer layer between a source electrode and a channel layer to realize ohmic contact, and introduces a tunneling layer between a drain electrode and a channel layer to realize tunneling contact.

[0008] Preferably, the buffer layer is a single layer or a multilayer of graphene.

[0009] Preferably, the tunneling layer is an insulating material.

[0010] Preferably, the insulating material is one of aluminum oxide, hafnium oxide and h-BN.

[0011] Preferably, the insulating material has a thickness of about 1 nanometer to 5 nanometers.

[0012] Preferably, the source electrode is a metal electrode, a nitride electrode or an oxide conductor electrode.

[0013] Preferably, the drain electrode is a metal electrode, a nitride electrode or an oxide conductor electrode.

[0014] Preferably, the ferroelectric functional layer on the ferroelectric memory is a ferroelectric thin film.

[0015] Preferably, the gate electrode on the ferroelectric memory is a metal electrode, a nitride electrode or an oxide conductor electrode.

[0016] On the other hand, the present invention also provides a method for preparing the novel ferroelectric memory, comprising the following steps:

[0017] Step (1): cleaning the surface of the selected substrate;

[0018] Step (2): preparing source electrode and drain electrode: preparing patterned source electrode and drain electrode on the surface of substrate;

[0019] Step (3): Preparation of a drain tunneling layer: preparing a tunneling layer on the drain electrode to achieve tunneling contact;

[0020] Step (4): Realization of ohmic contact at the source end: preparing a buffer layer on the source electrode to realize ohmic contact between the electrode and the semiconductor;

[0021] Step (5): Preparation of channel: preparing a channel layer of a two-dimensional semiconductor;

[0022] Step (6): Preparation of ferroelectric gate dielectric: preparing a ferroelectric functional layer on the channel layer of the two-dimensional semiconductor;

[0023] Step (7): Preparation of gate electrode: Prepare a patterned gate electrode on the ferroelectric functional layer.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The above-mentioned new ferroelectric memory provided by the present invention is prepared by introducing a buffer layer and a tunneling layer between the source electrode, the drain electrode and the channel layer of the ferroelectric memory respectively to realize tunneling contact and ohmic contact, and adopts a "two-dimensional semiconductor / tunneling layer / metal" tunnel junction as a channel.

[0026] The device achieved 10 9 Ultra-high on / off ratio and stable bipolar operation of MoS2.

[0027] In this new type of ferroelectric memory, the Fermi level of the two-dimensional semiconductor can be bipolarly regulated by ferroelectric polarization, and the regulation of the Fermi level can be sensitively detected by the direct quantum tunneling current of the tunnel junction. This not only brings new hope for logic devices, but also provides a new solution for high-density integration of devices.

[0028] The preparation method of the invention has simple operation steps and is easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a structural schematic diagram of the present invention;

[0030] Figure 2 The electrical performance of the novel ferroelectric memory prepared in Example 1 of the present invention, the device realizes stable bipolar operation of MoS2;

[0031] Figure 3 The electrical performance of the novel ferroelectric memory prepared in Example 1 of the present invention under different gate voltage test conditions, wherein (a) is a source-drain voltage of 0.3V, and (b) is a source-drain voltage of -0.3V. It can be seen that the output curve of the device exhibits bipolar characteristics, wherein the source-drain voltage is 0.3V and the device is biased to the p-type, and the source-drain voltage is -0.3V and the device is biased to the n-type;

[0032] Figure 4 Output curve of a ferroelectric field effect transistor using Cr / Au as source and drain electrodes and MoS2 semiconductor as the channel;

[0033] In the figure, 1, substrate layer; 2, drain electrode; 3, tunneling layer; 4, buffer layer; 5, channel layer; 6, ferroelectric functional layer; 7, gate electrode; 8, source electrode. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention; it is obvious that the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments, and all other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making creative work are within the scope of protection of the present invention.

[0035] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", "top / bottom" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0036] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "provided with", "mounted / connected", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0037] Glossary

[0038] h-BN-----hexagonal boron nitride;

[0039] P(VDF-TrFE)----Poly(vinylidene fluoride-trifluoroethylene);

[0040] MoS2----Molybdenum disulfide.

[0041] like Figure 1 As shown, the present invention provides a novel ferroelectric memory, in which a buffer layer is introduced between the source electrode and the channel layer to realize ohmic contact, and a tunneling layer is introduced between the drain electrode and the channel layer to realize tunneling contact.

[0042] like Figure 1 As shown, the present invention is an improvement based on the existing ferroelectric field effect transistor, which is a ferroelectric memory. The existing ferroelectric field effect transistor usually uses a semiconductor material as a channel, and its structure is as follows Figure 1 As shown, it has a substrate layer, a drain electrode, a source electrode, a channel layer, a ferroelectric functional layer and a gate electrode.

[0043] The present invention is based on the above-mentioned existing ferroelectric field effect transistor. By introducing a buffer layer between the source electrode and the channel layer to achieve ohmic contact, and introducing a tunneling layer between the drain electrode and the channel layer to achieve tunneling contact, the "two-dimensional semiconductor / tunneling layer / metal" tunnel junction is used as the channel. The Fermi level of the two-dimensional semiconductor of the novel ferroelectric memory can be bipolarly regulated by ferroelectric polarization, and the regulation of the Fermi level can be sensitively detected by the direct quantum tunneling current of the tunnel junction.

[0044] In the present invention, the buffer layer is a single layer or multiple layers of graphene.

[0045] In the present invention, the tunneling layer is an insulating material.

[0046] In the present invention, the insulating material is one of aluminum oxide, hafnium oxide and h-BN.

[0047] In the present invention, the thickness of the insulating material is about 1 nanometer to 5 nanometers.

[0048] In the present invention, the source electrode, drain electrode or gate electrode can all be metal electrodes, nitride electrodes or oxide conductor electrodes. The electrodes are preferably prepared by magnetron sputtering, thermal evaporation, electron beam evaporation and other preparation methods, and the electrodes are patterned by electron beam exposure, laser direct writing, ultraviolet lithography, mask and other processes. It belongs to the existing technology well known to those skilled in the art and will not be described in detail here.

[0049] In the present invention, the ferroelectric functional layer on the ferroelectric memory is a ferroelectric film, wherein the ferroelectric film can be preferably made of P(VDF-TrFE), Pb(Zr,Ti)O3, BiFeO3, BaTiO3 or Hf 0.5 Zr 0.5 Prepared from O2.

[0050] The channel involved in the present invention is a "two-dimensional semiconductor / tunneling layer / metal" tunnel junction, in which the two-dimensional material serves as an electrode of the tunnel junction and can be selected from N-type, P-type or bipolar semiconductors such as transition metal sulfides and black phosphorus.

[0051] On the other hand, the present invention also provides a method for preparing the novel ferroelectric memory, comprising the following steps:

[0052] Step (1): cleaning the surface of the selected substrate;

[0053] Step (2): preparing source electrode and drain electrode: preparing patterned source electrode and drain electrode on the surface of substrate;

[0054] Step (3): Preparation of a drain tunneling layer: preparing a tunneling layer on the drain electrode by mechanical stripping or physical vapor deposition to achieve tunneling contact;

[0055] Step (4): Realization of ohmic contact at the source end: preparing a buffer layer on the source electrode to realize ohmic contact between the electrode and the semiconductor;

[0056] Step (5): Preparation of channel: preparing a channel layer of a two-dimensional semiconductor;

[0057] Step (6): Preparation of ferroelectric gate dielectric: preparing a ferroelectric functional layer on the channel layer of the two-dimensional semiconductor;

[0058] Step (7): Preparation of gate electrode: Prepare a patterned gate electrode on the ferroelectric functional layer.

[0059] The technical solution of the present invention is clearly described in detail below in conjunction with specific embodiments.

[0060] Example 1

[0061] The method for manufacturing a novel ferroelectric memory structure using a "two-dimensional semiconductor / tunneling layer / metal" tunnel junction as a channel is as follows, and the specific steps are as follows:

[0062] (1) The substrate layer (SiO2 / Si) was placed in acetone for 5 minutes for ultrasonic treatment, then placed in an alcohol solution for 5 minutes for ultrasonic treatment, and then placed in deionized water for 5 minutes for ultrasonic treatment. Finally, the substrate was blown dry with a nitrogen gun.

[0063] (2) Electron beam exposure technology is used to pattern the shape of the source electrode and drain electrode on the cleaned SiO2 / Si surface, and then thermal evaporation technology is used to evaporate 10 / 50nm thick Cr / Au as the source electrode and drain electrode. The Cr deposition rate is The Au deposition rate is

[0064] (3) On the prepared drain electrode, the tunneling layer (thin layer h-BN) is transferred based on the PVA / PDMS point transfer technology.

[0065] (4) On the prepared source electrode, a buffer layer (single-layer or multi-layer graphene) is prepared based on the PDMS point transfer technology.

[0066] (5) Then, the channel layer (thin layer of MoS2) was prepared based on the PDMS point-to-point transfer technology.

[0067] (6) Spin coating the P(VDF-TrFE) gate dielectric layer with a thickness of 280 nm.

[0068] (7) Finally, a patterned Al gate electrode with a thickness of 50 nm and a deposition rate of 100 nm was prepared on the P(VDF-TrFE) gate dielectric layer using a mask process and thermal evaporation equipment.

[0069] The electrical properties of the device prepared in Example 1 were tested. Figure 2 As shown in the figure, it is found that the switching ratio of the device is as high as 9 orders of magnitude, and the ferroelectric field effect transistor exhibits bipolar characteristics, with an n-type characteristic when the source-drain voltage is negative and a p-type characteristic when the source-drain voltage is positive. Figure 3 The output curve of the ferroelectric field effect transistor using Cr / Au as source and drain electrodes and MoS2 semiconductor as the channel is shown in the attached figure. Figure 4 As shown, the nanostructured carbon nanotubes exhibit n-type characteristics, which is in sharp contrast to Example 1.

[0070] The above are only preferred specific implementations of the present invention; however, the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical solutions and improved concepts of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A novel ferroelectric memory, characterized in that: A buffer layer is introduced between the source electrode and the channel layer to realize ohmic contact, and a tunneling layer is introduced between the drain electrode and the channel layer to realize tunneling contact.

2. A novel ferroelectric memory according to claim 1, characterized in that: The buffer layer is a single layer or multiple layers of graphene.

3. A novel ferroelectric memory according to claim 1, characterized in that: The tunneling layer is made of insulating material.

4. A novel ferroelectric memory according to claim 3, characterized in that: The insulating material is one of aluminum oxide, hafnium oxide and h-BN.

5. A novel ferroelectric memory according to claim 3, characterized in that: The thickness of the insulating material is about 1 nanometer to 5 nanometers.

6. A novel ferroelectric memory according to claim 1, characterized in that: The source electrode is a metal electrode, a nitride electrode or an oxide conductor electrode.

7. A novel ferroelectric memory according to claim 1, characterized in that: The drain electrode is a metal electrode, a nitride electrode or an oxide conductor electrode.

8. The novel ferroelectric memory according to claim 1, characterized in that: The ferroelectric functional layer on the ferroelectric memory is a ferroelectric film.

9. A novel ferroelectric memory according to any one of claims 1 to 8, characterized in that: The gate electrode on the ferroelectric memory is a metal electrode, a nitride electrode or an oxide conductor electrode.

10. A method for preparing a novel ferroelectric memory according to any one of claims 1 to 9, characterized in that: The steps include: Step (1): cleaning the surface of the selected substrate; Step (2): preparing source electrode and drain electrode: preparing patterned source electrode and drain electrode on the surface of substrate; Step (3): Preparation of a drain tunneling layer: preparing a tunneling layer on the drain electrode to achieve tunneling contact; Step (4): Realization of ohmic contact at the source end: preparing a buffer layer on the source electrode to realize ohmic contact between the electrode and the semiconductor; Step (5): Preparation of channel: preparing a channel layer of a two-dimensional semiconductor; Step (6): Preparation of ferroelectric gate dielectric: preparing a ferroelectric functional layer on the channel layer of the two-dimensional semiconductor; Step (7): Preparation of gate electrode: Prepare a patterned gate electrode on the ferroelectric functional layer.

Images