Ferroelectric tunnel junction memory device

Abstract

The invention discloses a ferroelectric tunnel junction memory device, which comprises a first dielectric layer (100) and an array of field effect transistor monomers (1) arranged on the first dielectric layer in an array, the first dielectric layer (100) is sequentially provided with a drain electrode strip electrode (5), a second dielectric layer (200), a third dielectric layer (300), a ferroelectric tunnel junction first electrode (8), a ferroelectric dielectric tunneling layer (9), a ferroelectric tunnel junction second electrode (10) and a fourth dielectric layer (400). And then the fourth dielectric layer (400) is used as the first dielectric layer (100) of the next device, and the operation is repeated, so that multi-layer stacking of the three-dimensional structure ferroelectric tunnel junction can be realized, and the device has the advantages of low power consumption, easiness in reading and high-density integration, and has good practicability.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic technology, specifically to the field of information storage technology, and in particular to a ferroelectric tunnel junction memory device. Background Art

[0002] At present, the field of information technology has entered the era of big data, and the rapid development of technology has put forward higher and higher requirements for information storage and processing systems. The huge amount of data requires faster information processing speed, larger storage space and lower unit energy consumption, and there is an urgent need for a non-volatile, ultra-fast, low-energy and high-density storage device. Among them, as one of the principles of emerging storage devices, ferroelectric tunnel junction memory has great advantages in non-volatility, fast speed and low power consumption due to its ferroelectric storage principle.

[0003] With the existing information storage technology, the integration density and unit size of two-dimensional planar memory in a single layer are gradually approaching their limits through structural design and unit size miniaturization. And with the miniaturization of size, higher requirements are put forward for related micro-nano processing technologies, and the manufacturing cost of devices is becoming more and more expensive. At the same time, under the miniaturization of size, the ferroelectric tunnel junction cannot be well used in single-layer planar structure high-density storage due to its low read current density. Therefore, there is an urgent need for a ferroelectric tunnel junction memory device with low power consumption, easy reading, and further high-density integration.

[0004] In view of this, the present invention is proposed. Summary of the invention

[0005] The purpose of the present invention is to provide a ferroelectric tunnel junction memory device, which can realize multi-layer stacking, has the advantages of low power consumption, easy reading and high-density integration, and has good practicality.

[0006] The objective of the present invention is achieved through the following technical solutions:

[0007] A ferroelectric tunnel junction memory device comprises a first dielectric layer 100 and an array of field effect transistor monomers 1 arranged in an array thereon;

[0008] The field effect transistor monomer 1 includes a field effect transistor source 2, a field effect transistor gate 3 and a field effect transistor drain 4; the field effect transistor source 2 is arranged in a hexagonal close-packed array on the first dielectric layer 100;

[0009] The first dielectric layer 100 is provided with a drain strip electrode 5 or a gate strip electrode 6; the drain strip electrode 5 is connected to the field effect transistor drain 4 of the field effect transistor monomer 1 in the same row or column; the gate strip electrode 6 is connected to the field effect transistor gate 3 of the field effect transistor monomer 1 in the same row or column;

[0010] A second dielectric layer 200 is disposed on the first dielectric layer 100 to cover the drain electrode 4 of the field effect transistor and the drain strip electrode 5 or the gate strip electrode 6;

[0011] The second dielectric layer 200 is further provided with a gate strip electrode 6 or a drain strip electrode 5; the gate strip electrode 6 is connected to the field effect transistor gate 3 of the field effect transistor monomer 1 in the same column or row; the drain strip electrode 5 is connected to the field effect transistor drain 4 of the field effect transistor monomer 1 in the same column or row;

[0012] The second dielectric layer 200 is further provided with a third dielectric layer 300, covering the field effect transistor gate 3 and the gate strip electrode 6 or the drain strip electrode 5;

[0013] An array of ferroelectric tunnel junction first electrodes 8 connected to the source electrodes 2 of the field effect transistors is arranged upward on the third dielectric layer 300 corresponding to the source electrodes 2 of the field effect transistors below; a ferroelectric dielectric tunnel layer 9 is arranged on the surface of the ferroelectric tunnel junction first electrodes 8;

[0014] A ferroelectric tunnel junction second electrode 10 is disposed on the entire upper surface of the current device; and a fourth dielectric layer 400 is then entirely covered on the upper surface.

[0015] Preferably, the ferroelectric tunnel junction memory device is stacked in multiple layers; the fourth dielectric layer 400 of the ferroelectric tunnel junction memory device in the lower layer serves as the first dielectric layer 100 of the upper layer; a field effect transistor monomer 1, a drain strip electrode 5 or a gate strip electrode 6, a second dielectric layer 200 of the upper layer, a gate strip electrode 6 or a drain strip electrode 5, a third dielectric layer 300 of the upper layer, a ferroelectric tunnel junction first electrode 8, a ferroelectric dielectric tunneling layer 9, a ferroelectric tunnel junction second electrode 10 and a fourth dielectric layer 400 of the upper layer are sequentially arranged thereon; a multilayer stacked structure of a ferroelectric tunnel junction memory device of at least two layers is formed.

[0016] Preferably, one or all of the length or width dimensions of the upper dielectric layer in the first dielectric layer 100, the second dielectric layer 200, the third dielectric layer 300 and the fourth dielectric layer 400 are smaller than those of the lower dielectric layer; a multi-layer stacked structure of a ferroelectric tunnel junction memory device with a terrace structure is formed; electrodes of each layer are leaked out at the staggered layer edges for electrode leads.

[0017] Preferably, the ferroelectric tunnel junction first electrode 8 is a columnar electrode; comprising:

[0018] A single electrode, including a columnar electrode formed solely from a ferroelectric tunnel junction electrode material 801, or;

[0019] A double-layer electrode, comprising a columnar electrode core 802 and an electrode layer of a ferroelectric tunnel junction electrode material 801 coated outside the electrode core 802, forming a double-layer columnar electrode, or;

[0020] The three-layer electrode includes a columnar electrode core 802 , the columnar electrode core 802 is coated with a buffer electrode material layer 803 , and the electrode material layer 803 is coated with an electrode layer of a ferroelectric tunnel junction electrode material 801 , forming a three-layer columnar electrode.

[0021] Preferably, the ferroelectric dielectric tunneling layer 9 comprises:

[0022] A single ferroelectric layer 901, or;

[0023] A stacked structure of two or more layers consisting of at least one ferroelectric layer 901 and at least one dielectric layer 902.

[0024] Preferably, the field effect transistor monomer 1 comprises two field effect transistor sources 2, two field effect transistor gates 3 and a field effect transistor drain 4; the two field effect transistors constituting the common drain constitute the strip-shaped field effect transistor monomer 1.

[0025] Preferably, the strip-shaped field effect transistor monomer 1 is tilted to form an angle of 30 to 75 degrees with the drain strip electrode 5 .

[0026] Preferably, the second dielectric layer 200 and the third dielectric layer 300 are etched away above the field effect transistor source 2 to form a through hole, and a conductor 7 made of a conductive material is arranged in the through hole to connect the field effect transistor source 2 and the first electrode 8 of the ferroelectric tunnel junction.

[0027] A ferroelectric tunnel junction memory device comprises a first dielectric layer 100 and a blind hole groove arranged in a hexagonal close-packed array is etched on the upper surface; and a ferroelectric tunnel junction second electrode 10 is integrally arranged on the upper surface and the inner surface of the blind hole groove;

[0028] A ferroelectric dielectric tunneling layer 9 is disposed on the inner surface of the blind hole in the ferroelectric tunnel junction second electrode 10 in the blind hole groove; the upper surface is flush with the ferroelectric tunnel junction second electrode 10;

[0029] A ferroelectric tunnel junction first electrode 8 is filled in the blind hole in the ferroelectric dielectric tunnel layer 9; the upper surface is flush with the ferroelectric tunnel junction second electrode 10;

[0030] A second dielectric layer 200 is disposed on the entire upper surface of the current device;

[0031] An array of field effect transistor monomers 1 is arranged upwardly at the second dielectric layer 200 corresponding to the first electrode 8 of the ferroelectric tunnel junction below;

[0032] The field effect transistor monomer 1 includes a field effect transistor source 2, a field effect transistor gate 3 and a field effect transistor drain 4; the ferroelectric tunnel junction first electrode 8 is respectively connected to the field effect transistor source 2; the field effect transistor source 2 is arranged in a hexagonal close-packed array on the second dielectric layer 200;

[0033] The second dielectric layer 200 is provided with a drain strip electrode 5 or a gate strip electrode 6; the drain strip electrode 5 is connected to the field effect transistor drain 4 of the field effect transistor monomer 1 in the same row or column; the gate strip electrode 6 is connected to the field effect transistor gate 3 of the field effect transistor monomer 1 in the same row or column;

[0034] A third dielectric layer 300 is disposed on the second dielectric layer 200 to cover the field effect transistor drain 4 and the drain strip electrode 5 or the gate strip electrode 6;

[0035] The third dielectric layer 300 is further provided with a gate strip electrode 6 or a drain strip electrode 5; the gate strip electrode 6 is connected to the field effect transistor gate 3 of the field effect transistor monomer 1 in the same column or row; the drain strip electrode 5 is connected to the field effect transistor drain 4 of the field effect transistor monomer 1 in the same column or row;

[0036] The third dielectric layer 300 is further provided with a fourth dielectric layer 400 to cover the field effect transistor gate 3 and the gate strip electrode 6 or the drain strip electrode 5 .

[0037] Preferably, the ferroelectric tunnel junction memory device is stacked in multiple layers; the fourth dielectric layer 400 of the ferroelectric tunnel junction memory device in the lower layer serves as the first dielectric layer 100 of the upper layer; the ferroelectric tunnel junction second electrode 10, the ferroelectric dielectric tunneling layer 9, the ferroelectric tunnel junction first electrode 8, the second dielectric layer 200 of the upper layer, the field effect transistor monomer 1, the drain strip electrode 5 or the gate strip electrode 6, the third dielectric layer 300 of the upper layer, the gate strip electrode 6 or the drain strip electrode 5 and the fourth dielectric layer 400 of the upper layer are sequentially arranged thereon; forming a multi-layer stacked structure of at least two layers of ferroelectric tunnel junction memory devices.

[0038] Preferably, one or all of the length or width dimensions of the upper dielectric layer in the first dielectric layer 100, the second dielectric layer 200, the third dielectric layer 300 and the fourth dielectric layer 400 are smaller than those of the lower dielectric layer; a multi-layer stacked structure of a ferroelectric tunnel junction memory device with a terrace structure is formed; electrodes of each layer are leaked out at the staggered layer edges for electrode leads.

[0039] Preferably, the ferroelectric tunnel junction first electrode 8 is a columnar electrode; comprising:

[0040] A single electrode, including a columnar electrode formed solely from a ferroelectric tunnel junction electrode material 801, or;

[0041] A double-layer electrode, comprising a columnar electrode core 802 and an electrode layer of a ferroelectric tunnel junction electrode material 801 coated outside the electrode core 802, forming a columnar electrode, or;

[0042] The three-layer electrode includes a columnar electrode core 802, the columnar electrode core 802 is coated with a buffer electrode material layer 803, and the electrode material layer 803 is coated with an electrode layer of a ferroelectric tunnel junction electrode material 801 to form a columnar electrode.

[0043] Preferably, the ferroelectric dielectric tunneling layer 9 comprises:

[0044] A single ferroelectric layer 901, or;

[0045] A stacked structure of two or more layers consisting of at least one ferroelectric layer 901 and at least one dielectric layer 902.

[0046] Preferably, the field effect transistor monomer 1 comprises two field effect transistor sources 2, two field effect transistor gates 3 and a field effect transistor drain 4; the two field effect transistors constituting the common drain constitute the strip-shaped field effect transistor monomer 1.

[0047] Preferably, the strip-shaped field effect transistor monomer 1 is tilted to form an angle of 10 to 75 degrees with the drain strip electrode 5 .

[0048] Preferably, the strip-shaped field effect transistor monomer 1 is tilted to form an angle of 60 degrees with the drain strip electrode 5 .

[0049] Preferably, the second dielectric layer 200 is removed by etching above the field effect transistor source 2 to form a through hole, and a conductor 7 made of a conductive material is arranged in the through hole to connect the field effect transistor source 2 and the first electrode 8 of the ferroelectric tunnel junction.

[0050] Based on the above scheme, the ferroelectric tunnel junction memory device provided by the present invention can realize a ferroelectric tunnel junction memory device structure with two or more layers of high density stacking, and its beneficial effects include: the size of the three-dimensional columnar ferroelectric tunnel junction in a limited surface increases the unit area and improves the read current, thereby realizing the miniaturization of the size of the ferroelectric tunnel junction surface and improving the storage density; utilizing the insulating barrier dielectric layer filled to isolate each information storage array layer and avoid device failure caused by device series connection to realize stacking integration and improve storage density; the ferroelectric tunnel junctions in the same layer can be arranged in a hexagonal close-packed manner to improve storage density; the unit ferroelectric tunnel junction is an electrode / ferroelectric dielectric tunneling layer / electrode structure, the ferroelectric dielectric tunneling layer at least includes a ferroelectric layer and an optional dielectric layer, and the optional one or more dielectric layers can bring greater asymmetry to the entire ferroelectric tunnel junction device, which is conducive to achieving a high switching ratio and is beneficial to reducing the ferroelectric coercive field and operating voltage.

[0051] Compared with the prior art, the ferroelectric tunnel junction memory device provided by the present invention can realize multi-layer stacking, has the advantages of low power consumption, easy reading and high-density integration, and has good practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0053] Figure 1 A schematic diagram of a vertical cross-sectional structure of a ferroelectric tunnel junction memory device provided in Embodiment 1 of the present invention;

[0054] Figure 2 A schematic plan view of the layout of multiple field effect transistor monomers of a ferroelectric tunnel junction memory device is provided for the first embodiment of the present invention;

[0055] Figure 3 A schematic plan view of the external circuits of each electrode of a single-layer field effect transistor monomer array of a ferroelectric tunnel junction memory device is provided for the first embodiment of the present invention;

[0056] Figure 4 A schematic diagram of a rectangular array of field effect transistor monomers of a single-layer field effect transistor monomer array of a ferroelectric tunnel junction memory device is provided for the first embodiment of the present invention;

[0057] Figure 5 A schematic diagram of a staggered rectangular array of field effect transistor monomers of a single-layer field effect transistor monomer array of a ferroelectric tunnel junction memory device is provided for the first embodiment of the present invention;

[0058] Figure 6 A schematic diagram of a planar top view structure of a ferroelectric tunnel junction memory device is provided for the first embodiment of the present invention;

[0059] Figure 7 A schematic structural diagram of a first electrode of a ferroelectric tunnel junction of a ferroelectric tunnel junction memory device is provided for the first and second embodiments of the present invention;

[0060] Figure 8 A schematic structural diagram of a ferroelectric dielectric tunneling layer of a ferroelectric tunnel junction memory device is provided for an embodiment of the present invention;

[0061] Fig. 9 A schematic diagram of a multi-layer stacked structure of a ferroelectric tunnel junction memory device provided in the second embodiment of the present invention;

[0062] Fig.10 A schematic diagram of a vertical cross-sectional structure of a ferroelectric tunnel junction memory device provided in Embodiment 3 of the present invention;

[0063] Fig.11 A schematic diagram of a multi-layer stacked structure of a ferroelectric tunnel junction memory device provided in Embodiment 4 of the present invention;

[0064] Fig.12 A schematic diagram of the structural principle of a ferroelectric tunnel junction memory device is provided for an embodiment of the present invention. DETAILED DESCRIPTION

[0065] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in combination with the specific content of the present invention; it is obvious that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments, which does not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the present invention.

[0066] First, the terms that may be used in this article are explained as follows:

[0067] The term “and / or” means that either or both of them can be realized at the same time. For example, X and / or Y means both “X” or “Y” and “X and Y”.

[0068] The terms "include", "comprises", "contains", "has" or other descriptions with similar semantics should be interpreted as non-exclusive inclusion. For example, including certain technical feature elements (such as raw materials, components, ingredients, carriers, dosage forms, materials, dimensions, parts, components, mechanisms, devices, steps, procedures, methods, reaction conditions, processing conditions, parameters, algorithms, signals, data, products or products, etc.) should be interpreted as including not only certain technical feature elements explicitly listed, but also other technical feature elements known in the art that are not explicitly listed.

[0069] The term "consisting of..." means excluding any technical feature elements not explicitly listed. If this term is used in a claim, it will make the claim closed, so that it does not contain technical feature elements other than the technical feature elements explicitly listed, except for the conventional impurities related to them. If this term only appears in a clause of a claim, it only limits the elements explicitly listed in the clause, and the elements recorded in other clauses are not excluded from the overall claim.

[0070] Unless otherwise specified or limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example: it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this article can be understood according to specific circumstances.

[0071] The orientation or position relationship indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. are based on the orientation or position relationship shown in the drawings and are only for the convenience and simplification of description, and do not explicitly or implicitly indicate that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation of this document.

[0072] The technical solution provided by the present invention is described in detail below. The contents not described in detail in the embodiments of the present invention belong to the prior art known to professionals in the field. If the specific conditions are not specified in the embodiments of the present invention, the conditions are carried out according to the conventional conditions in the field or the conditions recommended by the manufacturer. If the manufacturer is not specified in the reagents or instruments used in the embodiments of the present invention, they are all conventional products that can be purchased commercially.

[0073] Embodiment 1

[0074] like Figure 1 As shown, an embodiment of the present invention provides a ferroelectric tunnel junction memory device, which structurally includes a first dielectric layer 100; multiple field effect transistor monomers 1, a drain strip electrode 5, a second dielectric layer 200, a gate strip electrode 6, a third dielectric layer 300, a ferroelectric tunnel junction first electrode 8, a ferroelectric dielectric tunneling layer 9, a ferroelectric tunnel junction second electrode 10 and a fourth dielectric layer 400.

[0075] The material of the dielectric layer mainly plays an insulating role and can be a dielectric material with good insulating properties such as silicon oxide and aluminum oxide.

[0076] Specific as Figure 2 and 3As shown, the first dielectric layer 100 is used as a substrate, and a plurality of field effect transistor monomers 1 are arranged in an array on the substrate. Here, a plurality of field effect transistor monomers 1 are grown in a rectangular array on the substrate by a growth method. The "growth" in this article can refer to the material growth and processing technology in the manufacture of integrated circuits. Here, the method of making field effect transistors in integrated circuits is referred to, and its principle is not repeated. A plurality of field effect transistor monomers 1 constitute a field effect transistor monomer 1 array; the field effect transistor monomer 1 comprises a field effect transistor source 2, a field effect transistor gate 3 and a field effect transistor drain 4. In this example, the field effect transistor monomer 1 comprises two field effect transistor sources 2, two field effect transistor gates 3 and a field effect transistor drain 4; the two field effect transistors constituting a common drain constitute a strip field effect transistor monomer 1. The drain is shared, which can reduce the overall size.

[0077] The array of field effect transistor monomers 1 here may include a "rectangular array" or a staggered "rectangular array", and it is necessary to ensure that the field effect transistor source 2 is arranged in a "hexagonal close-packed" array on the first dielectric layer 100. Hexagonal close-packing refers to constructing an array in a hexagonal close-packed manner, which can make full use of the single-layer plane area to further increase the integration density. This "hexagonal close-packed" arrangement has the same hexagonal function as a honeycomb, which can make full use of the single-layer plane area.

[0078] like Figure 4 As shown, in this example, the field effect transistor monomers 1 share the drain electrode, and the field effect transistor monomers 1 are arranged as a "rectangular array" as a whole, and the subsequent strip-shaped field effect transistor monomers 1 are tilted at an angle of 60 degrees to ensure that the field effect transistor source 2 is arranged in a hexagonal close-packed array on the first dielectric layer 100. In addition, the multiple ferroelectric tunnel junction first electrodes 8 grown later are arranged in a "hexagonal close-packed" arrangement. Figure 4 The five continuous squares in the middle bar represent the field effect transistor monomers with a common drain, while the solid black blocks are arranged in a "hexagonal close-packed" manner, expressing the "hexagonal close-packed" arrangement of the source 2 of the field effect transistor, and can be extended outward within the range allowed by the structural size.

[0079] like Figure 5 As shown, if the drain is not shared but a separate field effect transistor, a staggered "rectangular array" arrangement is adopted. The field effect transistors in adjacent rows are staggered and the field effect transistors in alternate rows are arranged in a "rectangular array", that is, two "rectangular arrays" are staggered to ensure that the field effect transistor source 2 is arranged in a hexagonal close-packed array on the first dielectric layer 100. Figure 5 The three continuous squares in the middle strip represent field effect transistors that do not share a drain. Adjacent rows are arranged in a staggered "rectangular array" and tilted at an angle of 60 degrees, ensuring that the source electrodes 2 of the field effect transistors are arranged in a hexagonal close-packed array on the first dielectric layer 100 and facilitating the subsequent arrangement of strip electrodes.

[0080] Here, the drain strip electrode 5 and the gate strip electrode 6 are grown on the first dielectric layer 100. The drain strip electrode 5 may be grown first and then the gate strip electrode 6, or the gate strip electrode 6 may be grown first and then the drain strip electrode 5. If the drain strip electrode 5 is arranged on this layer, the gate strip electrode 6 is arranged on the second dielectric layer 200; or vice versa, if the gate strip electrode 6 is arranged on this layer, the drain strip electrode 5 is arranged on the second dielectric layer 200.

[0081] At the same time, reference Figure 3 In order to facilitate the subsequent growth of the drain strip electrode 5 or the gate strip electrode 6, the strip-shaped field effect transistor monomer 1 is tilted to form an angle of 15 to 75 degrees with the drain strip electrode 5. Figure 3 Taking the drain strip electrode 5 grown first as an example, since the drain strip electrode 5 has a certain width, the strip field effect transistor monomer 1 is tilted and arranged at a 60-degree angle with the drain strip electrode 5, and the drain strip electrode 5 is arranged just between the two field effect transistor gates 3. At the same time, the strip field effect transistor monomer 1 is tilted and arranged at a 60-degree angle with the drain strip electrode 5, so that multiple ferroelectric tunnel junction first electrodes 8 can be arranged in an array in a dense arrangement of inner hexagons, which can make full use of the single-layer plane area to further increase the integration density. This "hexagonal dense stacking" arrangement has the same function as the hexagonal shape of the honeycomb, which can make full use of the single-layer plane area. The same is true for growing the gate strip electrode 6 first, except that it is necessary to connect the two field effect transistor gates 3 separately to avoid the field effect transistor drain 4.

[0082] Of course, if the field effect transistor monomer 1 includes only one field effect transistor, there is no need to consider the angle problem, as long as the drain strip electrode 5 and the gate strip electrode 6 are staggered and do not contact each other.

[0083] The height of the field effect transistor gate 3 here should be greater than the sum of the heights of the field effect transistor drain 4 and the drain strip electrode 5, and the size greater than should ensure that no electrical breakdown occurs between the drain strip electrode 5 and the gate strip electrode 6. Normally, the size greater than is more than 10 nm.

[0084] In this example, the drain strip electrode 5 is first grown and then the gate strip electrode 6 is grown. After the strip-shaped field effect transistor monomer 1 is grown, the drain strip electrode 5 is arranged on the first dielectric layer 100. Here, the drain strip electrode 5 is also grown on the first dielectric layer 100 in a growth manner to connect the field effect transistor drain 4 of the field effect transistor monomer 1 in the same row or column.

[0085] The electrode material of the drain strip electrode 5 may be, but is not limited to, heavily doped polysilicon, metal silicide, titanium nitride, tantalum nitride, tungsten, copper, aluminum, or other electrode materials that have good conductivity and can form good contact with adjacent electrode materials.

[0086] refer to Figure 2 and 3 , a second dielectric layer 200 is arranged on the first dielectric layer 100, and the second dielectric layer 200 is grown on the first dielectric layer 100 in a growth manner. The second dielectric layer 200 needs to cover the drain electrode 4 and the drain strip electrode 5 of the field effect transistor; the height of the second dielectric layer 200 should not exceed the height of the gate electrode 3 of the field effect transistor, so as to facilitate the subsequent arrangement of the gate strip electrode 6 and the electrical connection with the gate 3 of the field effect transistor. Of course, if the height of the second dielectric layer 200 exceeds the height of the gate 3 of the field effect transistor, it is necessary to etch the position of the second dielectric layer 200 corresponding to the gate 3 of the field effect transistor before arranging the gate strip electrode 6 to expose the gate 3 of the field effect transistor.

[0087] At the same time, at least one edge of the second dielectric layer 200 needs to leave a strip that does not cover the drain strip electrode 5 on the first dielectric layer 100, that is, one or both of the length and width of the second dielectric layer 200 are smaller than the first dielectric layer 100; it is convenient for the drain strip electrode 5 to connect to the external circuit. If the second dielectric layer 200 is grown on the entire surface of the first dielectric layer 100, the side length parallel to the long side direction of the drain strip electrode 5 can be made shorter than the drain strip electrode 5 by etching.

[0088] After the second dielectric layer 200 is completed, the surface of the second dielectric layer 200 may be subjected to chemical mechanical polishing to form a flat surface, thereby providing a good substrate for subsequent structure growth.

[0089] refer to Figure 2 and 3 , a gate strip electrode 6 is further arranged on the second dielectric layer 200. At this time, a drain strip electrode 5 is already arranged on the corresponding first dielectric layer 100. Here, the gate strip electrode 6 is also grown on the second dielectric layer 200 by a growth method. The gate strip electrode 6 is connected to the field effect transistor gate 3 of the field effect transistor monomer 1 in the same column or row. The gate strip electrode 6 crosses the drain strip electrode 5, generally in an orthogonal manner.

[0090] The material selection requirements for the gate strip electrode 6 are consistent with the material selection requirements for the drain strip electrode 5 .

[0091] refer to Figure 2 and 3 After the gate strip electrode 6 is grown, an insulating dielectric layer, that is, a third dielectric layer 300, needs to be filled for corresponding isolation. Specifically, the third dielectric layer 300 is arranged on the second dielectric layer 200, and the third dielectric layer 300 is grown on the second dielectric layer 200 in a growing manner, and the third dielectric layer 300 covers the field effect transistor gate 3 and the gate strip electrode 6.

[0092] At the same time, at least one edge of the third dielectric layer 300 needs to leave a strip that does not cover the gate strip electrode 6 on the second dielectric layer 200, that is, one or both of the length and width of the third dielectric layer 300 are smaller than the second dielectric layer 200, so as to facilitate the connection of the gate strip electrode 6 to the external circuit. If the third dielectric layer 300 is grown on the entire surface of the second dielectric layer 200, the side length parallel to the long side of the gate strip electrode 6 can be made shorter than the gate strip electrode 6 by etching.

[0093] After the third dielectric layer 300 is completed, the surface of the third dielectric layer 300 may be subjected to chemical mechanical polishing to form a flat surface, thereby providing a good substrate for subsequent structure growth.

[0094] Taking the example of first growing the gate strip electrode 6 and then growing the drain strip electrode 5, after the strip-shaped field effect transistor monomer 1 is grown, the gate strip electrode 6 is set on the first dielectric layer 100; here, the gate strip electrode 6 is also grown on the first dielectric layer 100 in a growth manner to connect the field effect transistor gates 3 of the field effect transistor monomers 1 in the same row or column; the electrode material of the gate strip electrode 6 can be but is not limited to heavily doped polysilicon, metal silicide, titanium nitride, tantalum nitride, tungsten, copper, aluminum and other electrode materials with good conductivity and capable of forming good contact with adjacent electrode materials.

[0095] refer to Figure 2 and 3 , a second dielectric layer 200 is arranged on the first dielectric layer 100, and the second dielectric layer 200 is grown on the first dielectric layer 100 in a growth manner. The second dielectric layer 200 needs to cover the field effect transistor gate 3 and the gate strip electrode 6; the height of the second dielectric layer 200 should not exceed the height of the field effect transistor drain 4, so as to facilitate the subsequent arrangement of the drain strip electrode 5 and the field effect transistor drain 4 to be electrically connected. Of course, if the height of the second dielectric layer 200 exceeds the height of the field effect transistor drain 4, it is necessary to etch the position of the second dielectric layer 200 corresponding to the field effect transistor drain 4 before arranging the gate strip electrode 6 to expose the field effect transistor drain 4.

[0096] At the same time, at least one edge of the second dielectric layer 200 needs to leave a strip that does not cover the gate strip electrode 6 on the first dielectric layer 100, that is, one or both of the length and width of the second dielectric layer 200 are smaller than the first dielectric layer 100, so as to facilitate the connection of the gate strip electrode 6 to the external circuit. If the second dielectric layer 200 is grown on the entire surface of the first dielectric layer 100, the side length parallel to the long side of the gate strip electrode 6 can be made shorter than the gate strip electrode 6 by etching.

[0097] After the second dielectric layer 200 is completed, the surface of the second dielectric layer 200 may be subjected to chemical mechanical polishing to form a flat surface, thereby providing a good substrate for subsequent structure growth.

[0098] refer to Figure 2 and 3 , a drain strip electrode 5 is arranged on the second dielectric layer 200, and a gate strip electrode 6 is arranged on the corresponding first dielectric layer 100; here, the drain strip electrode 5 is grown on the second dielectric layer 200 in a growing manner, and the drain strip electrode 5 is connected to the field effect transistor drain 4 of the field effect transistor monomer 1 in the same column or row; the drain strip electrode 5 crosses the gate strip electrode 6, generally in an orthogonal manner.

[0099] The material selection requirements for the drain strip electrode 5 are consistent with the material selection requirements for the gate strip electrode 6 .

[0100] refer to Figure 2 and 3 After growing the drain strip electrode 5, an insulating dielectric layer, that is, a third dielectric layer 300, needs to be filled for corresponding isolation. Specifically, the third dielectric layer 300 is arranged on the second dielectric layer 200, and the third dielectric layer 300 is grown on the second dielectric layer 200 in a growth manner. The third dielectric layer 300 covers the drain 4 and the drain strip electrode 5 of the field effect transistor.

[0101] At the same time, at least one edge of the third dielectric layer 300 needs to leave a strip that does not cover the drain strip electrode 5 on the second dielectric layer 200, that is, one or both of the length and width of the third dielectric layer 300 are smaller than the second dielectric layer 200; it is convenient for the drain strip electrode 5 to connect to the external circuit. If the third dielectric layer 300 is grown on the entire surface of the second dielectric layer 200, the side length parallel to the long side direction of the drain strip electrode 5 can be shorter than the drain strip electrode 5 by etching.

[0102] After the third dielectric layer 300 is completed, the surface of the third dielectric layer 300 may be subjected to chemical mechanical polishing to form a flat surface, thereby providing a good substrate for subsequent structure growth.

[0103] refer to Figure 3 and 4, the third dielectric layer 300 is provided with an array of first ferroelectric tunnel junction electrodes 8 connected to the source electrode 2 of the field effect transistor at the corresponding position of the source electrode 2 of the field effect transistor below; here, the array of first ferroelectric tunnel junction electrodes 8 connected to the source electrode 2 of the field effect transistor is also grown upward on the third dielectric layer 300 corresponding to the source electrode 2 of the field effect transistor below. The thickness of the ferroelectric tunnel junction should be determined according to the current process conditions. When the diameter of a single three-dimensional ferroelectric tunnel junction memory device allowed under the current integration density is 50nm, the thickness (i.e., diameter) of the first ferroelectric tunnel junction electrode 8 should be ensured to be about 20 to 30nm, to ensure its conductivity and mechanical strength, and also to leave enough space for the ferroelectric dielectric tunneling layer 9 (generally <5nm) and the second ferroelectric tunnel junction electrode 10 (thickness is generally 5 to 10nm, to ensure conductivity).

[0104] Here, after forming the third dielectric layer 300, the source electrode 2 of the field effect transistor needs to be exposed. The source electrode 2 of the field effect transistor may be exposed by increasing its height. In this example, the second dielectric layer 200 and the third dielectric layer 300 are etched and removed above the source electrode 2 of the field effect transistor to form a through hole, and a conductor 7 made of a conductive material is grown in the through hole until the upper surface of the third dielectric layer 300 is exposed, and the conductor 7 is used to connect the source electrode 2 of the field effect transistor with the first electrode 8 of the ferroelectric tunnel junction.

[0105] The material of the conductor 7 is selected from but not limited to heavily doped polysilicon, metal silicide, titanium nitride, tantalum nitride, tungsten, copper, aluminum, titanium, cobalt, ruthenium, molybdenum, tantalum, alloys thereof and / or combinations thereof, etc., which are materials capable of forming good contacts.

[0106] refer to Figure 7 Here, the first electrode 8 of the ferroelectric tunnel junction is a columnar electrode; the specific shape of the columnar electrode can be selected as a rectangular parallelepiped, a cylinder, a hexagonal prism, an octagonal prism, etc., as long as it has a large aspect ratio structure. This can ensure that the electrode area of ​​a single ferroelectric tunnel junction device is increased as much as possible while occupying a certain area on the plane to increase the reading current. The material is selected as an electrode material with good conductivity and good mechanical strength, which can ensure that it can support itself when it forms a large aspect ratio material.

[0107] The ferroelectric tunnel junction first electrode 8 has but is not limited to the following three structural forms:

[0108] The first type, single electrode, reference Figure 7 In the two figures on the left, the first ferroelectric tunnel junction electrode 8 is a columnar electrode formed by a ferroelectric tunnel junction electrode material 801 alone; specifically, the ferroelectric tunnel junction electrode material 801 is grown on the entire surface of the third dielectric layer 300 to a required height, and then etched to form the first ferroelectric tunnel junction electrode 8, and finally formed as shown in FIG. Figure 6An array of arranged ferroelectric tunnel junction first electrodes 8 .

[0109] This growth process is relatively simple, but it also places high demands on the material of the ferroelectric tunnel junction electrode material 801. Under this structure, the electrode material needs to have high mechanical strength and good process to be etched to form a flat surface, and the material itself should also be the material required for the ferroelectric tunnel junction, for example, it should meet the requirements of the ferroelectric generation of the ferroelectric layer and the tunneling effect of the tunnel junction itself. If the ferroelectric properties of the ferroelectric layer place certain requirements on the electrode, the electrode material should also meet the requirements. For example, when the ferroelectric layer is selected as a ferroelectric layer doped with hafnium oxide, the preferred electrode should be a material such as titanium nitride that can assist in doping hafnium oxide to produce a ferroelectric phase.

[0110] The second type, double-layer electrode, reference Figure 7 In the two figures listed above, the ferroelectric tunnel junction electrode material 801 includes a columnar electrode core 802 and an electrode layer of the ferroelectric tunnel junction electrode material 801 coated outside the electrode core 802, forming a double-layer columnar electrode.

[0111] Specifically, the electrode inner core material is first grown on the entire surface of the third dielectric layer 300 to a required height, and then etched to form the electrode inner core 802, and finally formed as shown in FIG. Figure 5 An array of arranged electrode cores 802. The electrode cores 802 are used as internal supports and are required to have sufficient mechanical strength and be easy to etch and grow, including but not limited to polysilicon materials.

[0112] Then, a ferroelectric tunnel junction electrode material 801 is grown on the electrode inner core 802 to form an array of ferroelectric tunnel junction first electrodes 8. The ferroelectric tunnel junction electrode material 801 here is made of titanium nitride, tungsten, ruthenium and other materials with excellent conductivity and suitable for process integration.

[0113] The third type, three-layer electrode, reference Figure 7 In the two figures on the right column, the ferroelectric tunnel junction electrode material 801 includes a columnar electrode core 802, the columnar electrode core 802 is coated with a buffer electrode material layer 803, and the electrode material layer 803 is coated with an electrode layer of the ferroelectric tunnel junction electrode material 801 to form a three-layer columnar electrode.

[0114] Specifically, the electrode inner core material is first grown on the entire surface of the third dielectric layer 300 to a required height, and then etched to form the electrode inner core 802, and finally formed as shown in FIG. Figure 5 An array of arranged electrode cores 802. The electrode cores 802 are used as internal supports and are required to have sufficient mechanical strength and be easy to etch and grow, including but not limited to polysilicon materials.

[0115] Then, a buffer electrode material layer 803 is grown on the electrode core 802. As a buffer layer, the material of the buffer electrode material layer 803 can be a metal material with good conductivity, or heavily doped polysilicon, etc., to reduce the negative effects caused by the electrode resistance. This buffer layer material is suitable for the case where the resistivity of the ferroelectric tunnel junction electrode material 801 itself is relatively large in the case of high-density integration.

[0116] Finally, a ferroelectric tunnel junction electrode material 801 is grown on the buffer electrode material layer 803 to form an array of ferroelectric tunnel junction first electrodes 8. The ferroelectric tunnel junction electrode material 801 here is made of titanium nitride, tungsten, ruthenium and other materials with excellent conductivity and suitable for process integration.

[0117] It can be seen that the first electrode 8 of the ferroelectric tunnel junction can be a single material or a multi-layer material, such as a titanium nitride / heavily doped polysilicon double-layer material. If a multi-layer material is prepared, it is necessary to conformally grow the second layer of electrode material and etch it after the first layer of columnar electrode is etched.

[0118] refer to Figure 3 and 6 , a ferroelectric dielectric tunneling layer 9 is arranged on the surface of the first ferroelectric tunnel junction electrode 8; here, the ferroelectric dielectric tunneling layer 9 is also grown on the first ferroelectric tunnel junction electrode 8 by a growth method.

[0119] refer to Figure 8 , in the upper left column, the ferroelectric dielectric tunneling layer 9 can be a single ferroelectric layer 901.

[0120] refer to Figure 8 Except for the left figure, the ferroelectric dielectric tunneling layer 9 can be a stacked structure of two or more layers consisting of at least one ferroelectric layer 901 and at least one dielectric layer 902.

[0121] It can be seen that the structure of the ferroelectric dielectric tunneling layer 9 can be composed of a single ferroelectric layer 901 material, and on the other hand, a dielectric layer 902 material with a low dielectric constant and a high bandgap can be introduced to form a ferroelectric tunneling layer together with it. There is no clear upper and lower relationship and layer number relationship between the ferroelectric layer 901 and the dielectric layer 902. On the other hand, the number of layers of the ferroelectric layer 901 and the dielectric layer 902 can also be a structure with more than one layer, which can be in the form of two layers of dielectric layers 902 sandwiching a ferroelectric layer 901, or the number of ferroelectric layers and dielectric layers can be continuously increased to stack upward to form an interlaced structure.

[0122] Among them, the material of the dielectric layer 902 is selected as an insulating dielectric material with a large band gap and a low dielectric constant, such as silicon oxide or aluminum oxide. The larger band gap ensures its good insulation and brings a larger switching ratio to the device, so as to facilitate the realization and reading of different discrete states. The lower dielectric constant is to reduce the delay effect of the capacitor on the entire circuit when the device is operated at high frequency.

[0123] The material of the ferroelectric layer 901 is a ferroelectric material with stable electric polarization and flippable polarization. Based on ferroelectric multi-domain flipping, the ferroelectric layer can be in at least two stable directions to obtain at least two storage states. The ferroelectric material of the ferroelectric layer may include at least one material selected from the following: wurtzite-based ferroelectric nitride material, hafnium oxide, doped hafnium oxide (doped elements may be zirconium, yttrium, aluminum, silicon, gadolinium, strontium, lanthanum, nitrogen, iron, lutetium, praseodymium, germanium, scandium, cerium, neodymium, magnesium, barium, indium, gallium, calcium, carbon, but not limited to the above elements), barium titanate, colemanite, bismuth titanate, barium europium titanate, ferroelectric polymer, germanium telluride, anhydrous potassium magnesium sulfate, scandium lead tantalate, lead titanate, lead zirconate titanate, lithium niobate, polyvinylidene fluoride, potassium niobate, potassium sodium tartrate, potassium titanyl phosphate, sodium bismuth titanate, lithium tantalate, lanthanum lead titanate, lanthanum lead zirconate titanate, ammonium dihydrogen phosphate and potassium dihydrogen phosphate. Other suitable ferroelectric materials are within the expected scope of the present invention. The preferred ferroelectric material can continuously and uniformly form a continuous ferroelectric layer on the surface of the columnar electrode by atomic layer deposition technology.

[0124] In the ferroelectric dielectric tunneling layer 9, the sum of the thicknesses of the ferroelectric layer 901 and the dielectric layer 902 should be less than 5 nanometers to ensure that the main conductive mechanism is tunneling. This ensures that after the ferroelectric storage state of the storage device is changed in a non-volatile, stable, and low-power manner, the ferroelectric storage state can be read directly and non-destructively by reading the tunneling current.

[0125] refer to Figure 3 and 6 , a ferroelectric tunnel junction second electrode 10 is disposed on the upper surface of the current device as a whole; the ferroelectric tunnel junction second electrode 10 is also grown on the upper surface of the current device by a growth method. Considering the influence of the conductivity of the electrode material on the performance, after the ferroelectric tunnel junction second electrode 10 is grown, a conductive layer can be further grown to connect all the individual devices to reduce the energy loss on the line. The material can be copper or other materials with good conductivity.

[0126] Then, the fourth dielectric layer 400 is entirely covered on the upper surface. Here, the fourth dielectric layer 400 is also grown on the upper surface of the current device by a growth method. Considering that the ferroelectric tunnel junction second electrode 10 needs to be fully covered here, so as to be insulated or multi-layered.

[0127] At the same time, at least one edge of the fourth dielectric layer 400 needs to leave a strip that does not cover the ferroelectric tunnel junction second electrode 10 on the third dielectric layer 300, that is, one or both of the length and width dimensions of the fourth dielectric layer 400 are smaller than the third dielectric layer 300; the ferroelectric tunnel junction second electrode 10 is connected to an external circuit. If the fourth dielectric layer 400 is grown on the entire surface of the third dielectric layer 300, the edge of one side of the fourth dielectric layer 400 can be etched smaller than the third dielectric layer 300 by etching.

[0128] In summary, after each covering of the insulating isolation dielectric layer is completed, the material surface may be optionally subjected to chemical mechanical polishing to form a flat surface, thereby providing a good substrate for subsequent structure growth.

[0129] Embodiment 2

[0130] like Fig. 9 As shown, the ferroelectric tunnel junction memory device can be a multi-layer stack of ferroelectric tunnel junction memory devices; the fourth dielectric layer 400 of the ferroelectric tunnel junction memory device of the lower layer is used as the first dielectric layer 100 of the upper layer; the field effect tube monomer 1, the drain strip electrode 5 or the gate strip electrode 6, the second dielectric layer 200 of the upper layer, the gate strip electrode 6 or the drain strip electrode 5, the third dielectric layer 300 of the upper layer, the first electrode 8 of the ferroelectric tunnel junction, the ferroelectric dielectric tunneling layer 9, the second electrode 10 of the ferroelectric tunnel junction and the fourth dielectric layer 400 of the upper layer are sequentially grown thereon; forming a multi-layer stack structure of a ferroelectric tunnel junction memory device of at least two layers. At the same time, one or all of the length or width dimensions of the upper dielectric layer of the first dielectric layer 100, the second dielectric layer 200, the third dielectric layer 300 and the fourth dielectric layer 400 are smaller than the lower dielectric layer; forming a multi-layer stack structure of a ferroelectric tunnel junction memory device with a terrace structure; the electrodes of each layer are leaked out at the staggered layer edges for electrode leads.

[0131] Embodiment 3

[0132] like Fig.10 As shown, a ferroelectric tunnel junction memory device, which structurally includes a first dielectric layer 100; multiple field effect transistor monomers 1, a drain strip electrode 5, a second dielectric layer 200, a gate strip electrode 6, a third dielectric layer 300, a ferroelectric tunnel junction first electrode 8, a ferroelectric dielectric tunneling layer 9, a ferroelectric tunnel junction second electrode 10 and a fourth dielectric layer 400.

[0133] You can refer to Figure 2 and 3 As shown, the first dielectric layer 100 is used as a substrate, and blind holes arranged in a hexagonal close-packed array are etched on the upper surface of the first dielectric layer 100. A ferroelectric tunnel junction second electrode 10 is integrally arranged on the upper surface of the first dielectric layer 100 and the inner surface of the blind hole groove; here, a layer of ferroelectric tunnel junction second electrode 10 is three-dimensionally conformally grown on the upper surface of the first dielectric layer 100 and the inner surface of the blind hole groove in a growth manner. The ferroelectric tunnel junction second electrode 10 in the blind hole groove forms an inner blind hole of the ferroelectric tunnel junction second electrode 10 again. Three-dimensional conformal growth refers to growing the ferroelectric tunnel junction second electrode 10 on the surface of the existing product in a full-coverage manner, and keeping the shape of the product roughly unchanged.

[0134] The material and thickness of the second ferroelectric tunnel junction electrode 10 refer to the corresponding description in the first embodiment.

[0135] A ferroelectric dielectric tunneling layer 9 is arranged on the inner surface of the inner blind hole of the ferroelectric tunnel junction second electrode 10 formed in the ferroelectric tunnel junction second electrode 10 in the blind hole groove; the upper surface is flush with the ferroelectric tunnel junction second electrode 10; a layer of ferroelectric dielectric tunneling layer 9 is grown on the ferroelectric tunnel junction second electrode 10 in a three-dimensional conformal growth manner. An inner blind hole of the ferroelectric dielectric tunneling layer 9 is formed again in the inner blind hole of the ferroelectric tunnel junction second electrode 10.

[0136] The structure and materials of the ferroelectric dielectric tunneling layer 9 refer to the corresponding description in the first reference embodiment.

[0137] The first ferroelectric tunnel junction electrode 8 is filled in the inner blind hole of the ferroelectric dielectric tunneling layer 9; the upper surface is flush with the second ferroelectric tunnel junction electrode 10; here, the first ferroelectric tunnel junction electrode 8 is grown in the inner blind hole of the ferroelectric dielectric tunneling layer 9 and filled.

[0138] refer to Figure 7 Here, the first ferroelectric tunnel junction electrode 8 is a columnar electrode; it can also be considered as a slot electrode. The specific shape of the columnar electrode can be selected as a cuboid, a cylinder, a hexagonal prism, an octagonal prism, etc. It only needs to have a large aspect ratio structure, so that the electrode area of ​​a single ferroelectric tunnel junction device can be increased as much as possible under the condition of a certain occupied area on the plane to increase the reading current. The material is selected as an electrode material with good conductivity and good mechanical strength, which can ensure that it can support itself when it forms a material with a large aspect ratio.

[0139] The ferroelectric tunnel junction first electrode 8 has but is not limited to the following three structural forms:

[0140] The first type, single electrode, reference Figure 7 In the two figures below the left column, the first ferroelectric tunnel junction electrode 8 is a columnar electrode formed by a ferroelectric tunnel junction electrode material 801 alone; specifically, the first ferroelectric tunnel junction electrode 8 is grown in the inner blind hole of the ferroelectric dielectric tunnel layer 9, and finally a reference is formed as shown in FIG. Figure 5 An array of arranged ferroelectric tunnel junction first electrodes 8 .

[0141] This growth process is relatively simple, but it also places high demands on the material of the ferroelectric tunnel junction electrode material 801. Under this structure, the electrode material needs to have high mechanical strength and good process to be etched to form a flat surface, and the material itself should also be the material required for the ferroelectric tunnel junction, for example, it should meet the requirements of the ferroelectric generation of the ferroelectric layer and the tunneling effect of the tunnel junction itself. If the ferroelectric properties of the ferroelectric layer place certain requirements on the electrode, the electrode material should also meet the requirements. For example, when the ferroelectric layer is selected as a ferroelectric layer doped with hafnium oxide, the preferred electrode should be a material such as titanium nitride that can assist in doping hafnium oxide to produce a ferroelectric phase.

[0142] The second type, double-layer electrode, reference Figure 7 In the two figures below, the ferroelectric tunnel junction electrode material 801 includes a columnar electrode core 802 and an electrode layer of the ferroelectric tunnel junction electrode material 801 coated outside the electrode core 802, forming a double-layer columnar electrode.

[0143] Specifically, firstly, a layer of ferroelectric tunnel junction electrode material 801 is grown in the inner blind hole of the ferroelectric dielectric tunneling layer 9 to form an inner blind hole composed of the ferroelectric tunnel junction electrode material 801 .

[0144] Then, the electrode core 802 is grown and filled in the inner blind hole of the ferroelectric tunnel junction electrode material 801. The electrode core 802 serves as an inner support and is required to have sufficient mechanical strength and be easy to etch and grow, including but not limited to polysilicon materials.

[0145] The third type, three-layer electrode, reference Figure 7 In the two figures on the right column, the ferroelectric tunnel junction electrode material 801 includes a columnar electrode core 802, the columnar electrode core 802 is coated with a buffer electrode material layer 803, and the electrode material layer 803 is coated with an electrode layer of the ferroelectric tunnel junction electrode material 801 to form a three-layer columnar electrode.

[0146] Specifically, firstly, a layer of ferroelectric tunnel junction electrode material 801 is grown in the inner blind hole of the ferroelectric dielectric tunneling layer 9 to form an inner blind hole composed of the ferroelectric tunnel junction electrode material 801 .

[0147] Then, a buffer electrode material layer 803 is grown in the inner blind hole of the ferroelectric tunnel junction electrode material 801 to form an inner blind hole composed of the buffer electrode material layer 803. As a buffer layer, the material of the buffer electrode material layer 803 can be a metal material with good conductivity, or heavily doped polysilicon, etc., to reduce the negative effects caused by the electrode resistance. This buffer layer material is suitable for the case where the resistivity of the ferroelectric tunnel junction electrode material 801 itself is relatively large in the case of high-density integration.

[0148] Finally, the electrode core 802 is filled in the inner blind hole of the buffer electrode material layer 803 and is fully filled. The electrode core 802 serves as an inner support and is required to have sufficient mechanical strength and be easy to etch and grow, including but not limited to polysilicon materials.

[0149] It can be seen that the first electrode 8 of the ferroelectric tunnel junction can be a single material or a multi-layer material, such as a titanium nitride / heavily doped polysilicon double-layer material. If a multi-layer material is prepared, it is necessary to conformally grow the second layer of electrode material and etch it after the first layer of columnar electrode is etched.

[0150] A second dielectric layer 200 is disposed on the entire upper surface of the current device; the second dielectric layer 200 is also grown in a growth manner, and the second dielectric layer 200 needs to cover the first ferroelectric tunnel junction electrode 8, the ferroelectric dielectric tunneling layer 9 and the second ferroelectric tunnel junction electrode 10;

[0151] At the same time, at least one edge of the second dielectric layer 200 needs to leave a strip that does not cover the ferroelectric tunnel junction second electrode 10 on the first dielectric layer 100, that is, one or both of the length and width dimensions of the second dielectric layer 200 are smaller than the first dielectric layer 100, so as to facilitate the connection of the ferroelectric tunnel junction second electrode 10 to an external circuit. If the second dielectric layer 200 is grown on the entire surface of the first dielectric layer 100, the ferroelectric tunnel junction second electrode 10 can be exposed on at least one edge by etching.

[0152] After the second dielectric layer 200 is completed, a chemical mechanical polishing process may be performed on the surface of the second dielectric layer 200 to form a flat surface, thereby providing a good substrate for subsequent structure growth.

[0153] Here, after forming the second dielectric layer 200, the ferroelectric tunnel junction first electrode 8 needs to be exposed. The height of the ferroelectric tunnel junction first electrode 8 can be increased to expose it. In this example, the second dielectric layer 200 is etched and removed above the ferroelectric tunnel junction first electrode 8 to form a through hole, and a conductor 7 made of a conductive material is grown in the through hole until the upper surface of the second dielectric layer 200 is exposed, and the conductor 7 is used to connect the source 2 of the field effect transistor with the ferroelectric tunnel junction first electrode 8.

[0154] The material of the conductor 7 is selected from but not limited to heavily doped polysilicon, metal silicide, titanium nitride, tantalum nitride, tungsten, copper, aluminum, titanium, cobalt, ruthenium, molybdenum, tantalum, alloys thereof and / or combinations thereof, etc., which are materials capable of forming good contacts.

[0155] An array of field effect transistor monomers 1 is arranged upward from the second dielectric layer 200 corresponding to the first electrode 8 of the ferroelectric tunnel junction below; here, a plurality of field effect transistor monomers 1 are grown in a rectangular array on the second dielectric layer 200 by a growth method. The "growth" in this article can refer to the electrode growth and processing technology in the manufacture of integrated circuits, and its principle is not repeated here. A plurality of field effect transistor monomers 1 constitute an array of field effect transistor monomers 1; the field effect transistor monomer 1 comprises a field effect transistor source 2, a field effect transistor gate 3 and a field effect transistor drain 4. In this example, the field effect transistor monomer 1 comprises two field effect transistor sources 2, two field effect transistor gates 3 and a field effect transistor drain 4; the two field effect transistors constituting the common drain constitute a strip-shaped field effect transistor monomer 1. The first electrode 8 of the ferroelectric tunnel junction is respectively connected to the field effect transistor source 2.

[0156] The array of field effect transistor monomers 1 generated here may include a "rectangular array" or a staggered "rectangular array", and it is necessary to ensure that the field effect transistor source 2 is arranged in a "hexagonal close-packed" array on the second dielectric layer 200. Hexagonal close-packing refers to constructing an array in a hexagonal close arrangement, which can make full use of the single-layer plane area to further increase the integration density. This "hexagonal close-packed" arrangement has the same hexagonal function as the honeycomb, which can make full use of the single-layer plane area.

[0157] like Figure 4 As shown, in the manner in which the generated field effect transistor monomers 1 share the drain, the field effect transistor monomers 1 are arranged as a "rectangular array" as a whole, and the subsequent strip-shaped field effect transistor monomers 1 are tilted at an angle of 60 degrees to ensure that the field effect transistor source 2 is arranged in a hexagonal close-packed array on the second dielectric layer 200. In addition, the multiple ferroelectric tunnel junction first electrodes 8 grown later are arranged in a "hexagonal close-packed" arrangement. Figure 4 The five continuous squares in the middle bar represent the field effect transistor monomers with a common drain, while the solid black blocks are arranged in a "hexagonal close-packed" manner, expressing the "hexagonal close-packed" arrangement of the source 2 of the field effect transistor, and can be extended outward within the range allowed by the structural size.

[0158] like Figure 5 As shown, if a separate field effect transistor is generated instead of a shared drain, an alternating "rectangular array" arrangement is adopted, the field effect transistors in adjacent rows are staggered and the field effect transistors in alternate rows are arranged in a "rectangular array", that is, two "rectangular arrays" are arranged in an alternating manner to ensure that the source electrodes 2 of the field effect transistors are arranged in a hexagonal close-packed array on the second dielectric layer 200. Figure 5 The three continuous squares in the middle strip represent field effect transistors that do not share a common drain. Adjacent rows are arranged in a staggered "rectangular array" and tilted at an angle of 60 degrees, ensuring that the source electrodes 2 of the field effect transistors are arranged in a hexagonal close-packed array on the second dielectric layer 200 and facilitating the subsequent arrangement of strip electrodes.

[0159] Here, the drain strip electrode 5 and the gate strip electrode 6 are grown on the second dielectric layer 200. The drain strip electrode 5 can be grown first and then the gate strip electrode 6, or the gate strip electrode 6 can be grown first and then the drain strip electrode 5. If the drain strip electrode 5 is set on this layer, the gate strip electrode 6 is set on the third dielectric layer 300; or vice versa, if the gate strip electrode 6 is set on this layer, the drain strip electrode 5 is set on the third dielectric layer 300.

[0160] At the same time, you can refer to Figure 3 In order to facilitate the subsequent growth of the drain strip electrode 5 or the gate strip electrode 6, the strip-shaped field effect transistor monomer 1 is tilted to form an angle of 15 to 75 degrees with the drain strip electrode 5, which needs to be controlled when the blind hole slot array is generated in the early stage. Figure 3 Taking the drain strip electrode 5 grown first as an example, since the drain strip electrode 5 has a certain width, the strip field effect transistor monomer 1 is tilted and arranged at a 60-degree angle with the drain strip electrode 5, and the drain strip electrode 5 is arranged just between the two field effect transistor gates 3. At the same time, the strip field effect transistor monomer 1 is tilted and arranged at a 60-degree angle with the drain strip electrode 5, so that multiple ferroelectric tunnel junction first electrodes 8 can be arranged in an array in a dense arrangement of inner hexagons, which can make full use of the single-layer plane area to further increase the integration density. This "hexagonal dense stacking" arrangement has the same function as the hexagonal shape of the honeycomb, which can make full use of the single-layer plane area. The same is true for growing the gate strip electrode 6 first, except that it is necessary to connect the two field effect transistor gates 3 separately to avoid the field effect transistor drain 4.

[0161] Of course, if the field effect transistor monomer 1 includes only one field effect transistor, there is no need to consider the angle problem, as long as the drain strip electrode 5 and the gate strip electrode 6 are staggered and do not contact each other. Usually, the size greater than is 10 nm.

[0162] The height of the field effect transistor gate 3 here should be greater than the sum of the heights of the field effect transistor drain 4 and the drain strip electrode 5, and the size greater than should ensure that no electrical breakdown occurs between the drain strip electrode 5 and the gate strip electrode 6.

[0163] In this example, the drain strip electrode 5 is first grown and then the gate strip electrode 6 is grown. After the strip-shaped field effect transistor monomer 1 is grown, the drain strip electrode 5 is arranged on the second dielectric layer 200. Here, the drain strip electrode 5 is also grown on the second dielectric layer 200 in a growth manner to connect the field effect transistor drain 4 of the field effect transistor monomer 1 in the same row or column.

[0164] The electrode material of the drain strip electrode 5 may be, but is not limited to, heavily doped polysilicon, metal silicide, titanium nitride, tantalum nitride, tungsten, copper, aluminum, or other electrode materials that have good conductivity and can form good contact with adjacent electrode materials.

[0165] A third dielectric layer 300 is arranged on the second dielectric layer 200. Here, the third dielectric layer 300 is grown on the second dielectric layer 200 in a growing manner. The third dielectric layer 300 needs to cover the drain electrode 4 and the drain strip electrode 5 of the field effect transistor. Here, the height of the third dielectric layer 300 should not exceed the height of the gate electrode 3 of the field effect transistor, so as to facilitate the subsequent arrangement of the gate strip electrode 6 and the electrical connection with the gate electrode 3 of the field effect transistor. Of course, if the height of the third dielectric layer 300 exceeds the height of the gate electrode 3 of the field effect transistor, it is necessary to etch the position of the third dielectric layer 300 corresponding to the gate electrode 3 of the field effect transistor before arranging the gate strip electrode 6 to expose the gate electrode 3 of the field effect transistor.

[0166] At the same time, at least one edge of the third dielectric layer 300 needs to leave a strip that does not cover the drain strip electrode 5 on the second dielectric layer 200, that is, one or both of the length and width of the third dielectric layer 300 are smaller than the second dielectric layer 200; it is convenient for the drain strip electrode 5 to connect to the external circuit. If the third dielectric layer 300 is grown on the entire surface of the second dielectric layer 200, the side length parallel to the long side direction of the drain strip electrode 5 can be shorter than the drain strip electrode 5 by etching.

[0167] After the third dielectric layer 300 is completed, the surface of the third dielectric layer 300 may be subjected to chemical mechanical polishing to form a flat surface, thereby providing a good substrate for subsequent structure growth.

[0168] A gate strip electrode 6 is further arranged on the third dielectric layer 300; at this time, a drain strip electrode 5 has been arranged on the corresponding second dielectric layer 200; here, the gate strip electrode 6 is also grown on the third dielectric layer 300 by a growth method, and the gate strip electrode 6 is connected to the field effect transistor gate 3 of the field effect transistor monomer 1 in the same column or row; the gate strip electrode 6 crosses the drain strip electrode 5, generally in an orthogonal manner.

[0169] The material selection requirements for the gate strip electrode 6 are consistent with the material selection requirements for the drain strip electrode 5 .

[0170] After the gate strip electrode 6 is grown, an insulating dielectric layer, that is, a fourth dielectric layer 400, needs to be filled for corresponding isolation. Specifically, the fourth dielectric layer 400 is arranged on the third dielectric layer 300, and the fourth dielectric layer 400 is grown on the third dielectric layer 300 in a growth manner, and the fourth dielectric layer 400 covers the field effect transistor gate 3 and the gate strip electrode 6.

[0171] At the same time, at least one edge of the fourth dielectric layer 400 needs to leave a strip that does not cover the gate strip electrode 6 on the third dielectric layer 300, that is, one or both of the length and width of the fourth dielectric layer 400 are smaller than the third dielectric layer 300, so as to facilitate the connection of the gate strip electrode 6 to the external circuit. If the fourth dielectric layer 400 is grown on the entire surface of the third dielectric layer 300, the side length parallel to the long side of the gate strip electrode 6 can be made shorter than the gate strip electrode 6 by etching.

[0172] After the fourth dielectric layer 400 is completed, the surface of the fourth dielectric layer 400 may be subjected to chemical mechanical polishing to form a flat surface, thereby providing a good substrate for subsequent structure growth.

[0173] In summary, after each covering of the insulating isolation dielectric layer is completed, the material surface may be optionally subjected to chemical mechanical polishing to form a flat surface, thereby providing a good substrate for subsequent structure growth.

[0174] Taking the example of growing the gate strip electrode 6 first and then growing the drain strip electrode 5, after the strip-shaped field effect transistor monomer 1 is grown, the gate strip electrode 6 is arranged on the second dielectric layer 200; here, the gate strip electrode 6 is also grown on the second dielectric layer 200 in a growth manner to connect the field effect transistor gates 3 of the field effect transistor monomers 1 in the same row or column;

[0175] The electrode material of the gate strip electrode 6 may be, but is not limited to, heavily doped polysilicon, metal silicide, titanium nitride, tantalum nitride, tungsten, copper, aluminum, or other electrode materials that have good conductivity and can form good contact with adjacent electrode materials.

[0176] A third dielectric layer 300 is arranged on the second dielectric layer 200. Here, the third dielectric layer 300 is grown on the second dielectric layer 200 in a growing manner. The third dielectric layer 300 needs to cover the field effect transistor gate 3 and the gate strip electrode 6. Here, the height of the third dielectric layer 300 should not exceed the height of the field effect transistor drain 4, so as to facilitate the subsequent arrangement of the drain strip electrode 5 and the electrical connection with the field effect transistor drain 4. Of course, if the height of the third dielectric layer 300 exceeds the height of the field effect transistor drain 4, it is necessary to etch the position of the third dielectric layer 300 corresponding to the field effect transistor drain 4 before arranging the drain strip electrode 5 to expose the field effect transistor drain 4.

[0177] At the same time, at least one edge of the third dielectric layer 300 needs to leave a strip that does not cover the gate strip electrode 6 on the second dielectric layer 200, that is, one or both of the length and width of the third dielectric layer 300 are smaller than the second dielectric layer 200, so as to facilitate the connection of the gate strip electrode 6 to the external circuit. If the third dielectric layer 300 is grown on the entire surface of the second dielectric layer 200, the side length parallel to the long side of the gate strip electrode 6 can be made shorter than the gate strip electrode 6 by etching.

[0178] After the third dielectric layer 300 is completed, the surface of the third dielectric layer 300 may be subjected to chemical mechanical polishing to form a flat surface, thereby providing a good substrate for subsequent structure growth.

[0179] A drain strip electrode 5 is arranged on the third dielectric layer 300; at this time, a gate strip electrode 6 is arranged on the corresponding second dielectric layer 200; here, the drain strip electrode 5 is grown on the third dielectric layer 300 in a growing manner, and the drain strip electrode 5 is connected to the field effect transistor drain 4 of the field effect transistor monomer 1 in the same column or row; the drain strip electrode 5 crosses the gate strip electrode 6, generally in an orthogonal manner.

[0180] The material selection requirements for the drain strip electrode 5 are consistent with the material selection requirements for the drain strip electrode 5 .

[0181] After growing the drain strip electrode 5, an insulating dielectric layer, that is, a fourth dielectric layer 400, needs to be filled for corresponding isolation. Specifically, the fourth dielectric layer 400 is arranged on the third dielectric layer 300, and the fourth dielectric layer 400 is grown on the third dielectric layer 300 in a growth manner, and the fourth dielectric layer 400 covers the field effect transistor drain 4 and the drain strip electrode 5.

[0182] At the same time, at least one edge of the fourth dielectric layer 400 needs to leave a strip that does not cover the drain strip electrode 5 on the third dielectric layer 300, that is, one or both of the length and width of the fourth dielectric layer 400 are smaller than the third dielectric layer 300; it is convenient for the drain strip electrode 5 to connect to the external circuit. If the fourth dielectric layer 400 is grown on the entire surface of the third dielectric layer 300, the side length parallel to the long side direction of the drain strip electrode 5 can be made shorter than the drain strip electrode 5 by etching.

[0183] After the fourth dielectric layer 400 is completed, the surface of the fourth dielectric layer 400 may be subjected to chemical mechanical polishing to form a flat surface, thereby providing a good substrate for subsequent structure growth.

[0184] In summary, after each covering of the insulating isolation dielectric layer is completed, the material surface may be optionally subjected to chemical mechanical polishing to form a flat surface, thereby providing a good substrate for subsequent structure growth.

[0185] Embodiment 4

[0186] You can refer to Fig. 9 ,like Fig.11 As shown, the ferroelectric tunnel junction memory device can be a multi-layer stack of ferroelectric tunnel junction memory devices; the fourth dielectric layer 400 of the ferroelectric tunnel junction memory device of the lower layer is used as the first dielectric layer 100 of the upper layer; the second ferroelectric tunnel junction electrode 10, the ferroelectric dielectric tunneling layer 9, the first ferroelectric tunnel junction electrode 8, the second dielectric layer 200 of the upper layer, the field effect transistor monomer 1, the drain strip electrode 5, the third dielectric layer 300 of the upper layer, the gate strip electrode 6 and the fourth dielectric layer 400 of the upper layer are sequentially grown thereon; a multi-layer stack structure of a ferroelectric tunnel junction memory device of at least two layers is formed. At the same time, one or all of the length or width dimensions of the upper dielectric layer of the first dielectric layer 100, the second dielectric layer 200, the third dielectric layer 300 and the fourth dielectric layer 400 are smaller than the lower dielectric layer; a multi-layer stack structure of a ferroelectric tunnel junction memory device with a terrace structure is formed; the electrodes of each layer are leaked out at the staggered layer edges for electrode leads.

[0187] Fig.12 The figure shows the equivalent circuit diagram corresponding to the single-layer ferroelectric tunnel junction memory array, in which one end electrode of the ferroelectric tunnel junction memory device in the same layer is connected through the ferroelectric tunnel junction second electrode 10, and the other end electrode forms an open circuit or a path through the switch of the field effect tube to prevent the information of different devices from being written or read incorrectly. The selection of a certain field effect tube and ferroelectric tunnel junction information unit can be uniquely determined by the row electrode-drain strip electrode 5 and the column electrode-gate strip electrode 6, so as to realize the selection of a certain memory device and read and write operations on it.

[0188] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or in any form that the information constitutes prior art known to those skilled in the art.

Claims

1. A ferroelectric tunnel junction memory device, characterized in that: It comprises a first dielectric layer (100) and an array of field effect tube monomers (1) arranged in an array thereon; The field effect transistor monomer (1) comprises a field effect transistor source (2), a field effect transistor gate (3) and a field effect transistor drain (4); the field effect transistor source (2) is arranged in a hexagonal close-packed array on the first dielectric layer (100); A drain strip electrode (5) or a gate strip electrode (6) is arranged on the first dielectric layer (100); the drain strip electrode (5) is connected to the field effect transistor drain (4) of the field effect transistor monomer (1) in the same row or column; the gate strip electrode (6) is connected to the field effect transistor gate (3) of the field effect transistor monomer (1) in the same row or column; A second dielectric layer (200) is disposed on the first dielectric layer (100) to cover the field effect transistor drain (4) and the drain strip electrode (5) or the gate strip electrode (6); A gate strip electrode (6) or a drain strip electrode (5) is further arranged on the second dielectric layer (200); The gate strip electrode (6) is connected to the field effect transistor gates (3) of the field effect transistor monomers (1) in the same column or row; the drain strip electrode (5) is connected to the field effect transistor drains (4) of the field effect transistor monomers (1) in the same column or row; The second dielectric layer (200) is further provided with a third dielectric layer (300) to cover the field effect transistor gate (3) and the gate strip electrode (6) or the drain strip electrode (5); An array of ferroelectric tunnel junction first electrodes (8) connected to the source electrodes (2) of the field effect transistors is arranged upward on the third dielectric layer (300) corresponding to the source electrodes (2) of the field effect transistors below; a ferroelectric dielectric tunnel layer (9) is arranged on the surface of the ferroelectric tunnel junction first electrodes (8); A ferroelectric tunnel junction second electrode (10) is integrally arranged on the upper surface of the current device; and a fourth dielectric layer (400) is integrally covered on the upper surface.

2. The ferroelectric tunnel junction memory device according to claim 1, characterized in that: The ferroelectric tunnel junction memory device is stacked in multiple layers; The fourth dielectric layer (400) of the ferroelectric tunnel junction memory device of the lower layer is used as the first dielectric layer (100) of the upper layer; a field effect tube monomer (1), a drain strip electrode (5) or a gate strip electrode (6), a second dielectric layer (200) of the upper layer, a gate strip electrode (6) or a drain strip electrode (5), a third dielectric layer (300) of the upper layer, a ferroelectric tunnel junction first electrode (8), a ferroelectric dielectric tunneling layer (9), a ferroelectric tunnel junction second electrode (10) and a fourth dielectric layer (400) of the upper layer are sequentially arranged thereon; a multi-layer stacked structure of a ferroelectric tunnel junction memory device of at least two layers is formed.

3. The ferroelectric tunnel junction memory device according to claim 2, characterized in that: One or both of the length or width dimensions of the upper dielectric layer among the first dielectric layer (100), the second dielectric layer (200), the third dielectric layer (300) and the fourth dielectric layer (400) are smaller than the lower dielectric layer; a multi-layer stacked structure of a ferroelectric tunnel junction memory device with a terrace structure is formed; electrodes of each layer are leaked out at the staggered layer edges for electrode leads.

4. The ferroelectric tunnel junction memory device according to claim 1, 2 or 3, characterized in that: The ferroelectric dielectric tunneling layer (9) comprises: a single ferroelectric layer (901), or; A stacked structure of two or more layers consisting of at least one ferroelectric layer (901) and at least one dielectric layer (902).

5. The ferroelectric tunnel junction memory device according to claim 1, 2 or 3, characterized in that: The field effect transistor monomer (1) comprises two field effect transistor sources (2), two field effect transistor gates (3) and a field effect transistor drain (4); A strip-shaped field effect tube monomer (1) is formed by two field effect tubes with a common drain.

6. A ferroelectric tunnel junction memory device, characterized in that: It comprises a first dielectric layer (100) and blind holes arranged in a hexagonal close-packed array are etched on the upper surface; and a ferroelectric tunnel junction second electrode (10) is integrally arranged on the upper surface and the inner surface of the blind hole. A ferroelectric dielectric tunneling layer (9) is arranged on the inner surface of the blind hole of the ferroelectric tunnel junction second electrode (10) in the blind hole groove; the upper surface is flush with the ferroelectric tunnel junction second electrode (10); A ferroelectric tunnel junction first electrode (8) is filled in a blind hole in a ferroelectric dielectric tunnel layer (9); the upper surface is flush with the ferroelectric tunnel junction second electrode (10); A second dielectric layer (200) is disposed on the entire upper surface of the current device; An array of field effect transistor monomers (1) is arranged upwardly at a position corresponding to the first electrode (8) of the ferroelectric tunnel junction below the second dielectric layer (200); The field effect transistor monomer (1) comprises a field effect transistor source (2), a field effect transistor gate (3) and a field effect transistor drain (4); the ferroelectric tunnel junction first electrodes (8) are respectively connected to the field effect transistor source electrodes (2); the field effect transistor source electrodes (2) are arranged in a hexagonal close-packed array on the second dielectric layer (200); A drain strip electrode (5) or a gate strip electrode (6) is arranged on the second dielectric layer (200); the drain strip electrode (5) is connected to the field effect transistor drain (4) of the field effect transistor monomer (1) in the same row or column; the gate strip electrode (6) is connected to the field effect transistor gate (3) of the field effect transistor monomer (1) in the same row or column; A third dielectric layer (300) is disposed on the second dielectric layer (200) to cover the field effect transistor drain (4) and the drain strip electrode (5) or the gate strip electrode (6); A gate strip electrode (6) or a drain strip electrode (5) is further arranged on the third dielectric layer (300); The gate strip electrode (6) is connected to the field effect transistor gates (3) of the field effect transistor monomers (1) in the same column or row; the pole strip electrode (5) is connected to the field effect transistor drains (4) of the field effect transistor monomers (1) in the same column or row; The third dielectric layer (300) is further provided with a fourth dielectric layer (400) to cover the field effect transistor gate (3) and the gate strip electrode (6) or the drain strip electrode (5).

7. The ferroelectric tunnel junction memory device according to claim 6, characterized in that: Multilayer stacking of ferroelectric tunnel junction memory devices; The fourth dielectric layer (400) of the ferroelectric tunnel junction memory device of the lower layer is used as the first dielectric layer (100) of the upper layer; a ferroelectric tunnel junction second electrode (10), a ferroelectric dielectric tunneling layer (9), a ferroelectric tunnel junction first electrode (8), a second dielectric layer (200) of the upper layer, a field effect transistor monomer (1), a drain strip electrode (5) or a gate strip electrode (6), a third dielectric layer (300) of the upper layer, a gate strip electrode (6) or a drain strip electrode (5) and a fourth dielectric layer (400) of the upper layer are sequentially arranged thereon; a multi-layer stacked structure of a ferroelectric tunnel junction memory device of at least two layers is formed.

8. The ferroelectric tunnel junction memory device according to claim 7, characterized in that: One or both of the length or width dimensions of the upper dielectric layer among the first dielectric layer (100), the second dielectric layer (200), the third dielectric layer (300) and the fourth dielectric layer (400) are smaller than the lower dielectric layer; a multi-layer stacked structure of a ferroelectric tunnel junction memory device with a terrace structure is formed; electrodes of each layer are leaked out at the staggered layer edges for electrode leads.

9. The ferroelectric tunnel junction memory device according to claim 6, 7 or 8, characterized in that: The ferroelectric dielectric tunneling layer (9) comprises: a single ferroelectric layer (901), or; A stacked structure of two or more layers consisting of at least one ferroelectric layer (901) and at least one dielectric layer (902).

10. The ferroelectric tunnel junction memory device according to claim 6, 7 or 8, characterized in that: The field effect transistor monomer (1) comprises two field effect transistor sources (2), two field effect transistor gates (3) and a field effect transistor drain (4); A strip-shaped field effect tube monomer (1) is formed by two field effect tubes with a common drain.

Images