Nonvolatile memory device and erasing method thereof

Abstract

The present disclosure relates to a nonvolatile memory device and an erase method thereof, the erase method including: initiating an erase operation of a memory block by applying an erase condition to the memory block; performing a first erase verify program on at least a portion of the memory block compared to the first erase verify voltage; adjusting the first erase verify voltage in response to having passed the first erase verify program; performing a second erase verify program on at least a portion of the memory block compared to the adjusted erase verify voltage; performing a post-program verify program on at least a portion of the memory block compared to the post-program verify voltage; and determining whether the adjusted erase verify voltage reaches a final erase verify voltage and whether the post-program verify voltage reaches a final post-program verify voltage.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory, and more particularly to a non-volatile memory device capable of improving over-erasure and an erasing method thereof. Background Art

[0002] During an erase operation of a flash memory device (e.g., a NOR flash memory device), when erasing is performed on an entire memory block, variations in the threshold voltages of the memory cells therein may cause some memory cells to fail to be properly erased, and some memory cells may have a threshold voltage close to a low voltage, thereby causing leakage current. These memory cells are also referred to as over-erased cells.

[0003] In detail, Figure 1 , the conventional erasing operation includes an erase pulse application procedure S201, an erase verification procedure S202, and a post-programming procedure S203. If the post-programming operation is performed, the threshold voltage of the memory cell with the fastest erase rate rises faster than the threshold voltage of the memory cell with the slowest erase rate. Therefore, the threshold voltage distribution of these memory cells can be narrowed. Although the implementation methods are different, the purpose of the post-programming operation S203 is also well known, which essentially involves recovering over-erased memory cells.

[0004] In addition, memory cells that are over-erased or very close to being over-erased may have bit line leakage currents that are higher than acceptable levels. Since the actual memory cell verification current is equal to the sum of the bit line leakage current and the memory cell current, the presence of leakage currents may cause the memory cell verification current to be abnormally high and thus cause a read failure. Since the bit line is shared between multiple memory cells, high bit line leakage currents may also cause read failures for all memory cells that share the same bit line. Figure 2 An example of the above problem is shown. Figure 2 In the present invention, a flash memory device includes a plurality of sectors or memory blocks, each of which includes a plurality of storage cells. Assuming that a sector or memory block 301 is selected for an erase operation, if a post-programming operation is not completed, there may be a significant leakage current. In addition, if a leakage current exists in the memory block 301 selected for an erase operation, it may cause subsequent read or programming operations on the remaining unselected sectors (or memory blocks 302) sharing the same bit line BL to fail. In addition, there may also be a power drop in the bit line bias voltage during the erase operation, and if the post-programming operation is not completed before the power drop, the power drop may also increase the bit line leakage current. Therefore, in order to solve the above problems, it is necessary to improve the erase operation of the memory device. Summary of the invention

[0005] To solve the problem that memory cells that are over-erased or very close to being over-erased may have a bit line leakage current higher than an acceptable level, the present disclosure relates to a nonvolatile memory device and an erase method thereof.

[0006] The present disclosure relates to an erasing method for a non-volatile memory device, comprising: starting an erasing operation of a memory block by applying an erasing condition to the memory block; performing a first erasing verification procedure on at least a portion of the memory block that is compared with a first erasing verification voltage; adjusting the first erasing verification voltage in response to at least a portion of the memory block having passed the first erasing verification procedure; performing a second erasing verification procedure on at least a portion of the memory block that is compared with the adjusted erasing verification voltage; performing a post-programming verification procedure on the memory block that is compared with a post-programming verification voltage to detect over-erased storage cells or leakage currents of the memory block; determining whether the adjusted erasing verification voltage has reached a final erasing verification voltage, and whether the post-programming verification voltage has reached a final post-programming verification voltage; and completing the erasing operation in response to the adjusted erasing verification voltage having reached the final erasing verification voltage and the post-programming verification voltage having reached the final post-programming verification voltage.

[0007] The present disclosure also relates to a memory device, including a memory block and a controller coupled to the memory block. The controller is configured to: start an erase operation of the memory block by applying an erase condition to the memory block; perform a first erase verification procedure compared with a first verification voltage on at least a portion of the memory block; adjust the first verification voltage in response to at least a portion of the memory block having passed the first erase verification procedure; perform a second erase verification procedure compared with the adjusted erase verification voltage on the memory block; perform a post-programming verification procedure compared with a post-programming verification voltage on the memory block to detect over-erased storage cells or leakage currents of the memory block; determine whether the adjusted erase verification voltage reaches the final erase verification voltage, and whether the post-programming verification voltage reaches the final post-programming verification voltage; and complete the erase operation in response to the adjusted erase verification voltage having reached the final erase verification voltage and the post-programming verification voltage having reached the final post-programming verification voltage.

[0008] The present disclosure enables more efficient erasing of memory blocks by minimizing leakage current while conserving the number of erase pulses without significantly increasing the amount of time required to erase a memory block. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A conventional erasing method of a flash memory device is shown;

[0010] Figure 2The problem that leakage current of a memory block selected for erasure causes read or program failure of an unselected memory block sharing the same bit line is shown;

[0011] Figure 3 and Figure 5 An erasing method according to an embodiment of the present disclosure is shown;

[0012] Figure 4 A memory device implementing an erasing method according to an embodiment of the present disclosure is shown;

[0013] Fig. 6A shows a change in threshold voltage distribution through a third erase verification procedure after applying an erase pulse according to an embodiment of the present disclosure;

[0014] Figure 6B shows a change in the threshold voltage distribution that fails the first erase verification procedure after the erase pulse cycle count has exceeded an expected number according to an embodiment of the present disclosure;

[0015] Figure 7 A schematic diagram showing maintaining the erase speed regardless of the number of erase cycles according to an embodiment of the present disclosure;

[0016] Figure 8 shows the change of threshold voltage distribution in various steps according to an embodiment of the present disclosure;

[0017] Fig.9A shows a shift in the threshold voltage distribution of a portion of faster memory cells compared to the entire memory block after applying an erase condition to the entire memory block according to an embodiment of the present disclosure;

[0018] Fig. 9B shows a shift in the threshold voltage distribution of a portion of slower memory cells compared to the entire memory block after applying an erase condition to the entire memory block according to an embodiment of the present disclosure;

[0019] Fig. 10A and Fig. 10B Schematic diagrams each showing a method of performing a post-program verification procedure on a portion of the memory cells of a block according to some embodiments of the present disclosure;

[0020] Fig.11 The concept of selecting a portion of storage units according to an embodiment of the present disclosure is illustrated;

[0021] Fig.12 and Fig.13 A schematic diagram of a memory device according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0022] Reference will now be made in detail to the present exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0023] The concept of the present disclosure is described as follows. After receiving an erase command, an erase condition is applied to erase all memory cells of a memory block, and then a first erase verification procedure is performed on the memory block, which is compared with a first erase verification voltage. In detail, in the first erase verification procedure, a test voltage or current is applied to determine whether the threshold voltage distribution of the memory block is lower than the first erase verification voltage. If it is determined that the threshold voltage distribution of the memory block is lower than the first erase verification voltage, it means passing the first erase verification procedure, and then performing a second erase verification procedure compared with a second erase verification voltage on the memory block. If it is determined that the threshold voltage distribution of the memory block is lower than the second erase verification voltage, it means passing the second erase verification procedure, and then performing a post-programming verification procedure to detect whether there are any over-erased memory cells in the memory block by applying a post-programming verification voltage to the memory block. If it is determined that the threshold voltage distribution of the memory block is higher than the post-programming verification voltage, it means passing the post-programming verification procedure, and then determining whether the post-programming verification voltage and the second erase verification voltage reach the final post-programming verification voltage and the final erase verification voltage, respectively. The second erase verification voltage is between the final erase verification voltage and the first erase verification voltage. If the post-program verification voltage and the second erase verification voltage reach the final post-program verification voltage and the final erase verification voltage, respectively, it means that the erase operation is completed.

[0024] If the post-program verification voltage and the second erase verification voltage do not reach the final post-program verification voltage and the final erase verification voltage, respectively, a step voltage will be used to adjust the post-program verification voltage and the second erase verification voltage to the final post-program verification voltage and the final erase verification voltage, or close to the final post-program verification voltage and the final erase verification voltage, and the process will return to apply the erase condition again. In other words, the present disclosure can detect memory cells that may be damaged and cannot be erased at an early stage by using the erase verification voltage and the post-program verification voltage that are respectively less than the final erase verification voltage and the final post-program verification voltage as intermediate targets for determining whether the erase operation is on track.

[0025] If the erase verification procedure (e.g., the first erase verification procedure or the second erase verification procedure) is not passed, the erase condition may be changed. For example, the bias voltage of the erase pulse may be made stronger (e.g., a voltage of a more negative value), or more erase pulses may be applied. For example, the erase condition may be a single erase pulse, and if the erase verification procedure (e.g., the first erase verification procedure or the second erase verification procedure) is not passed, the number of erase pulses applied before the erase verification procedure is passed (hereinafter referred to as the erase pulse loop count) is counted and compared with the expected number (e.g., 5). If the erase pulse loop count is not greater than the expected number, the process will return to apply the same erase condition again. On the contrary, if the erase pulse loop count is greater than the expected number, the erase bias voltage of the erase pulse is adjusted to be stronger, and then the process will return to apply the adjusted erase pulse.

[0026] In detail, if it is determined that a portion of the threshold voltage distribution of the memory block is higher than the first erase verification voltage, it means that the first erase verification procedure has not been passed, and if the erase pulse cycle count is greater than the expected number, the erase condition will be adjusted to be stronger and then applied to the memory block until the first erase verification procedure is passed. The erase condition is usually applied to the word line of the memory block.

[0027] Before the final post-programming verification voltage has been reached, one or more slightly higher post-programming verification voltages may be applied to determine whether some erased memory cells near the tail end of the threshold voltage distribution are below the higher post-programming verification voltage. If some erased memory cells near the tail end of the threshold voltage distribution are below the higher post-programming verification voltage, it may indicate that the erased memory cells are close to being over-erased, which may cause leakage current. If some erased memory cells are below the higher post-programming verification voltage, a post-programming procedure is performed to attempt to increase the threshold voltage of the erased memory cells near the tail end of the threshold voltage distribution and reduce leakage current. The purpose of the higher post-programming verification voltage is to act as a buffer before leakage current actually occurs.

[0028] During the erase operation, the erase condition may be adjusted according to a first step level and a second step level that is less than the first step level. The first step level is configured to enable the threshold voltage distribution of the memory block to reach the corresponding erase verification voltage faster, but after the leakage current has been detected by the post-programming verification procedure, the second step level is adopted to avoid over-erasing the memory block. In an alternative embodiment, when some erased memory cells are below a higher post-programming verification voltage, that is, when the post-programming verification procedure is not passed, only a portion of the memory cells in the memory block are erased before the post-programming procedure. The portion of the memory cells may be some memory cells from each partition in the block, or may be a byte in the block. In another alternative embodiment, when the post-programming verification procedure is not passed, the subsequent erase conditions may remain the same or decrease.

[0029] The erase condition (e.g., bias voltage) may be adjusted after each erase verify voltage is reached. However, the erase condition may not be adjusted until the erase condition is greater than the expected number before the erase verify voltage has been reached. Changing the erase bias voltage may reduce the number of erase pulses applied to minimize memory cell degradation. In addition, the proper balance between the number of erase pulses and the adjustment of the erase bias voltage may be optimized to increase the erase speed and avoid over-erasing the memory cells.

[0030] The post-program verification voltage and the final post-program verification voltage can be implemented by bit line (column), so it does not take longer than the conventional technology. The post-program verification voltage and the final post-program verification voltage can have different bit line bias voltages, or can be used in a sense amplifier circuit to detect more than one bit line current or a higher word line voltage level.

[0031] In order to implement the above concept, the present disclosure provides an erasing method of a memory device and a memory device using the erasing method. Figure 34 shows an erasing method of a memory device. Please note that the contents described above can also be applied to this embodiment and will not be described in detail. In step S401, the memory device receives an erase command. In step S402, an erase condition is applied to erase a memory block of the memory device. In step S403, a first erase verification procedure is performed on the memory block to verify whether the threshold voltage distribution of the memory block has reached the first erase verification voltage. In step S404, a second erase verification procedure is performed on the memory block that has reached the first erase verification voltage to verify whether the threshold voltage distribution of the memory block has reached the second erase verification voltage. In step S405, the memory device will perform a post-programming verification procedure to detect whether the memory block that has reached the second erase verification voltage is close to being over-erased according to the post-programming verification voltage. In step S406, if the post-programming verification procedure is passed, the memory device can determine whether the post-programming verification voltage and the second erase verification voltage have reached the final post-programming verification voltage and the final erase verification voltage, respectively. The second erase verification voltage is between the final erase verification voltage and the first erase verification voltage. In step S407, when the post-program verification voltage and the second erase verification voltage reach the final post-program verification voltage and the final erase verification voltage, respectively, the memory device can complete the erase operation. Otherwise, in step S408, the memory device can adjust the post-program verification voltage and the second erase verification voltage, and the process will return to step S402, but the adjusted post-program verification voltage and the adjusted second erase verification voltage are used in the subsequent corresponding steps.

[0032] According to an exemplary embodiment, in response to determining that a memory block has not passed an iteration of an erase verification procedure (e.g., a first erase verification procedure or a second erase verification procedure), the memory device may apply a plurality of erase pulses (which is an example of an erase condition). Similarly, in response to determining that a memory block has not passed an iteration of an erase verification procedure, the memory device may also adjust the erase condition from a first erase bias voltage to a second erase bias voltage. The memory device may also apply the above two measures in response to determining that a memory block has not passed an iteration of an erase verification procedure. In addition, in response to the memory block not passing another iteration of an erase verification procedure, the memory device may apply a third erase bias voltage. The step level between the first erase bias voltage and the second erase bias voltage may be equal to the step level between the second erase bias voltage and the third erase bias voltage, thereby reaching different erase verification voltages in a linear manner.

[0033] Figure 45. The memory device 500 is shown with the hardware blocks most relevant to the present disclosure. The memory device 500 will include, but is not limited to, a memory array 501 for storing digital binary information controlled by a memory controller 503. The memory array 501 may include a plurality of memory banks, and each memory bank may include a memory block 502. The structure of the memory block 502 may be in various ways (e.g., Fig.13 The memory controller 503 is electrically connected to the memory array 501 and is configured to control the memory array 501 to implement the following. Figure 4 And the erasing method described in the subsequent exemplary embodiments.

[0034] To further illustrate the erasing method 400 and the memory device 500, the present disclosure provides the following Figures 5 to 13 The exemplary embodiments of the present invention are described in detail and are set forth in their corresponding written description. Figure 5 Show this disclosure Figure 3 The exemplary embodiment of the erasing method shown in FIG. The previously described contents can also be applied to this embodiment and will not be described in detail. Figure 5 In step S601, after receiving the erase command, the memory device starts an erase operation to erase the memory block, and sets initial conditions including a first erase bias voltage, a first erase verification voltage, and a first post-programming verification voltage. In step S602, the memory device applies a single erase pulse to the memory block as an erase condition. In step S603, the memory device performs a first erase verification procedure by measuring the threshold voltage distribution of the memory block and based on whether the threshold voltage distribution is completely lower than the first erase verification voltage. If the threshold voltage distribution is not completely lower than the first erase verification voltage, it means that the first erase verification procedure has not been passed. If the threshold voltage distribution is completely lower than the first erase verification voltage, it means that the first erase verification procedure has been passed.

[0035] In response to not passing the first erase verification procedure, in step S604, if the erase pulse cycle count has exceeded the expected number N, the memory device may change the erase bias voltage of the erase condition applied to the word line of the memory block to a voltage of a larger negative value. The expected number N is a positive integer and may be, for example, 5, but the present disclosure does not limit the expected number N to any specific number. If the erase bias voltage has been changed, the erase pulse cycle count is reset to 0. In response to having passed the first erase verification procedure, in step S605, the memory device will determine whether the erase pulse cycle count is 1, and if the erase pulse cycle count is 1, the first erase verification voltage is adjusted to a second erase verification voltage that may be the final erase verification voltage or closer to the final erase verification voltage. In this embodiment, the second erase verification voltage may be lower than the first erase verification voltage. It should be noted that in order to complete the erase operation faster, the step level between the first erase verification voltage and the second erase verification voltage may be larger, and the step level between subsequent erase verification voltages may gradually become smaller.

[0036] In step S607, the memory device may perform a post-programming verification procedure to determine whether to perform a post-programming operation. In addition, in step S607, the memory device may clear the erase pulse cycle count. The post-programming verification procedure may involve determining whether the threshold voltage distribution of the memory block is completely greater than the first post-programming verification voltage that is higher than the final post-programming verification voltage. If the threshold voltage distribution of the memory block is not completely greater than the first post-programming verification voltage, it means that the post-programming verification procedure has not been passed. If the threshold voltage distribution of the memory block is completely greater than the first post-programming verification voltage, it means that the post-programming verification procedure has been passed. If the post-programming verification procedure has not been passed, the memory device will perform a post-programming operation in step S608. If the post-programming verification procedure has been passed, the memory device will determine in step S609 whether the current erase verification voltage and the current post-programming verification voltage are the same as the final erase verification voltage and the final post-programming verification voltage, respectively. The final erase verification voltage and the final post-programming verification voltage are each a predetermined target voltage. If the current erase verification voltage and the current post-program verification voltage are the same as the final erase verification voltage and the final post-program verification voltage, respectively, then in step S611, the erase operation is completed. If the current erase verification voltage and the current post-program verification voltage are different from the final erase verification voltage and the final post-program verification voltage, respectively, then in step S610, the memory device will adjust the first post-program verification voltage and the second erase verification voltage to the final post-program verification voltage and the final erase verification voltage, or closer to the final post-program verification voltage and the final erase verification voltage, respectively, and the process will return to step S602, but the adjusted post-program verification voltage and the adjusted erase verification voltage will be used. In addition, in step S610, the memory device may further change the post-program bias voltage and use the changed post-program bias voltage in step S608 of the next iteration. In one embodiment, in step S610, if the erase verification voltage is the final erase verification voltage, the post-program verification voltage is changed, and if the erase verification voltage is not the final erase verification voltage, the erase verification voltage is changed.

[0037] Fig. 6A and Figure 6B For further illustration Figure 5 Steps S601 to S606 are shown. Fig. 6A and Figure 6B In FIG. 7 , the vertical dotted lines are various erase verification voltages 705 (eg, 1st EV, 2nd EV, 3rd EV, 4th EV, etc.) that are not the final erase verification voltage, the X-axis is voltage, and the Y-axis is quantity. Fig. 6AAs can be seen in FIG. 6 , before any erase pulse is applied, the initial threshold voltage distribution 701 of the memory block is not completely below the first erase verification voltage (1st EV). After applying one erase pulse (e.g., S602), the initial threshold voltage distribution 701 moves to a second threshold voltage distribution 702 that will successfully pass the third erase verification procedure (e.g., S603). In other words, in response to only one erase pulse, the threshold voltage distribution has shifted to be below the third erase verification voltage (3rd EV). Therefore, the loop from step S603 to step S606 is performed three times to change the erase verification voltage from the 1st EV to the 4th EV. Subsequently, since the second threshold voltage distribution 702 will not pass the fourth erase verification procedure, the memory device will perform step S602 to apply another single erase pulse and make the erase pulse cycle count equal to 2. Then, assuming that the second threshold voltage distribution 702 shifts below the fourth erase verification voltage (4th EV) in response to another single erase pulse, since the erase pulse cycle count is not 1, the memory will perform step S607.

[0038] exist Figure 6B In the embodiment, before any erase pulse is applied, the initial threshold voltage distribution 703 of the memory block is not completely below the first erase verification voltage (1st EV). In this embodiment, after multiple iterations from step S602 to step S604, the erase pulse cycle count has exceeded the expected number N, but the second threshold voltage distribution 704 still fails the first erase verification procedure. Therefore, in step S604, the memory device can change the erase bias voltage by making the erase bias voltage applied to the word line of the memory block stronger (i.e., a voltage with a more negative value).

[0039] refer to Figure 7 As a result of sequentially performing the first erase verification procedure, the second erase verification procedure, the third erase verification procedure, and the fourth erase verification procedure on the same memory block, four threshold voltage distributions 801, 802, 803, and 804 can be obtained respectively. In order to ensure that each erase verification procedure can be passed within the expected number N of erase pulse cycle counts, the erase bias voltage can be adjusted (for example, adjusted by -0.5 volts) after the threshold voltage distribution has reached each erase verification voltage. In this way, by applying a combination of more erase pulses and increasing the erase bias voltage, the speed of the erase operation can be increased, and the degradation of the memory cell can be compensated, so that the erase time of a memory block (cycling block) that has undergone multiple cycles is close to the erase time of an unused memory block, or the erase speed is linearly related to time.

[0040] Figure 8 Shown as Figure 5The changes in the threshold voltage distribution in each stage of the erase method. In stage S901 before step S601, the memory block with the first threshold voltage distribution is erased. In stage S902, in response to passing step S603, the first threshold voltage distribution is moved to a second threshold voltage distribution that meets the first erase verification target (for example, moved to completely below the 1st EV). In stage S903, after several iterations, the threshold voltage distribution approaches a higher post-programming verification voltage 912. As shown, the higher post-programming verification voltage 912 is between the first erase verification target (1st EV) and the final post-programming verification voltage 911. In stage S904, Figure 5 After several iterations of the steps shown, the threshold voltage distribution is still between the higher post-programming verification voltage 912 and a certain erase verification voltage. In stage S905, in response to failing step S607, the tail of the threshold voltage distribution 901 is lower than the higher post-programming verification voltage 912, and then a post-programming procedure (e.g., S608) and iterations of step S607 are performed to shift threshold voltage 901 to threshold voltage 902, which is between the higher post-programming verification voltage 912 and the specific erase verification voltage. In one embodiment, the erase verification voltage can be adjusted according to a first step level and a second step level that is less than the first step level. After leakage current has been detected by the post-programming verification procedure (i.e., failing step S607), the second step level is used to slow down the change step of the erase verification voltage. Stage S906 is similar to stage S905, but threshold voltage 902 is at Figure 5 After several iterations of the steps shown, it becomes narrower. In stage S907, it is indicated that Figure 5 After several iterations of the steps shown, threshold voltage distribution 901 has been shifted to threshold voltage distribution 902, where threshold voltage distribution 902 is between final post-programming verification voltage 911 and final erase verification voltage N EV (final), and the erase procedure is considered complete (e.g., S611). As shown, the next erase verification voltage (e.g., 2 EV) is closer to the final post-programming verification voltage 911 than the current erase verification voltage (e.g., 1 EV), thereby gradually moving the threshold voltage distribution to between the final post-programming verification voltage 911 and the final erase verification voltage N EV (final).

[0041] According to embodiments of the present disclosure, in certain situations, such as when the leakage current is too high or when the threshold voltage distribution cannot be easily moved, the erase method can be applied to a portion of the memory block. When only a portion of the memory block is erased at a time, the erase method can also be applied. Figure 3 and Figure 5 The erasure method shown, but modified versions may also be applicable.

[0042] Fig.9Aand Fig. 9B Schematic diagrams showing displacement of threshold voltage distributions of some faster memory cells and some slower memory cells compared with the entire memory block after applying erase conditions to the entire memory block. The waveform of threshold voltage distribution of the entire memory block is larger, while the waveform of threshold voltage distribution of some faster memory cells and some slower memory cells is smaller. Fig.9A , which shows the threshold voltage distribution of the entire memory block and the threshold voltage distribution composed of some memory cells that move faster in the memory block (i.e., some faster memory cells). The characteristic of some faster memory cells is that when some faster memory cells have passed the erase verification target (e.g., EV1, EV2, etc.), the entire memory block has not passed the same erase verification target. Fig. 9B , which shows the threshold voltage distribution of the entire memory block and the threshold voltage distribution composed of some memory cells that move slower in the memory block (i.e., some slower memory cells). The characteristic of some slower memory cells is that when some slower memory cells have passed the erase verification target (e.g., EV1, EV2, etc.), most of the threshold voltage distribution of the entire memory block is too far away from the current erase verification target. In other words, if the entire memory block is always erased, many memory cells may experience erasure in the future.

[0043] In order to improve the problem mentioned in the previous paragraph, Fig. 10A and Fig. 10B Each shows a second embodiment of the erasure method, which slightly modifies the erasure verification procedure. Only the differences from the previous embodiment will be described below. In the second embodiment, a portion of the memory block (e.g. Fig.11 , preferably a portion of faster memory cells) rather than the entire memory block. In detail, in the first erase verification procedure, a test voltage or current is applied to determine whether the threshold voltage distribution of the portion of the memory block is lower than the first erase verification voltage. If it is determined that the threshold voltage distribution of the portion of the memory block is lower than the first erase verification voltage, it means that the first erase verification procedure is passed. Similarly, a second erase verification procedure and subsequent erase verification procedures are performed on a portion of the memory block rather than the entire memory block. However, when the memory device determines in step S609 that the current erase verification voltage is the final erase verification voltage, but when the current post-programming verification voltage is not the final post-programming verification voltage 1105, then the memory device will perform an erase verification procedure compared with the final erase verification voltage on the entire memory block before step S610. If the threshold voltage distribution of the memory block is completely lower than the final erase verification voltage, the process will proceed to step S610. In Fig. 10A, which shows an example where the threshold voltage distribution of faster memory cells is lower than the final erase verification voltage, while the threshold voltage distribution 1101 of the entire memory block is not lower than the final erase verification voltage. When this situation is detected, step S602 will be performed.

[0044] In the second embodiment, in step S607, the post-program verification procedure includes determining whether the threshold voltage distribution of the memory block is completely greater than the first post-program verification voltage 1104. Fig. 10B As shown, if it is detected that the threshold voltage distribution 1102 of the entire memory block is not completely greater than the first post-program verification voltage 1104, the post-program verification procedure will further include determining a portion of the memory block (eg, Fig.11 As shown, it is preferred that the threshold voltage distribution of some slower memory cells (partially slower memory cells) is greater than the first post-program verification voltage 1104. If so, the following modifications may be applied. In one embodiment, the erase condition (e.g., the erase bias voltage) may be reduced in step S610. In another embodiment, in step S610, the erase condition (e.g., the erase target) may be changed from the entire memory block to some slower memory cells, so that the erase pulse is only applied to some slower memory cells instead of the entire memory block. In an alternative embodiment, in step S610, the erase condition may be reduced (e.g., the step level for changing the erase bias voltage).

[0045] It is worth noting that Fig.11 As shown, although the entire memory block may include multiple partitions, a portion of the memory may be defined as some storage cells 1201 from each partition in a block, or only one byte of storage cells 1202 in a partition in a block.

[0046] According to the second embodiment, the erasing time can be further reduced, and the memory cell can be further prevented from being over-erased.

[0047] Fig.12 and Fig.13 Each shows a flash memory device for implementing an erasing method on a memory block 502. Figure 4. The flash memory device 1300 is an example of the memory device 500, for example, a NOR flash memory device. The flash memory device 1300 includes a memory array 501, the memory array 501 has at least one memory block 502 and a sense amplifier circuit, the sense amplifier circuit including a first transistor Q1, a second transistor Q2, a reference memory cell Q3 and an operational amplifier 1303. One of the drain terminal or the source terminal of the first transistor Q1 can be connected to the pull-up circuit 1302, and the other can be connected to the bit line (one of b0 to bN). In addition, one of the drain terminal or the source terminal of the second transistor Q2 can be connected to the pull-up circuit 1302, and the other can be connected to the ground through the reference memory cell Q3 to provide a reference current. The two input terminals of the operational amplifier 1303 are respectively coupled to the nodes where the first transistor Q1 and the second transistor Q2 are respectively coupled to the pull-up circuit 1302, so as to compare the bit line current with the reference current converted from the voltage, thereby outputting the voltage difference between the two. A bias erase voltage may be applied to the word line WL <0> To WL <m>.like Fig.12 As shown, the gate voltages of the first transistor Q1 and the second transistor Q2 may be the sense amplifier reference voltage SAVREF. It should be noted that, for ease of understanding, Fig.12 and Fig.13 Only one first transistor Q1 and one operational amplifier 1303 are shown, and those skilled in the art should know that the sense amplifier circuit may have more first transistors and operational amplifiers to sense the currents of all bit lines.

[0048] As the post-programming verification voltage for detecting leakage current increases, it may be more difficult to detect leakage current. In order to further improve the sensitivity of leakage current detection, the following variation is proposed. Fig.13 As shown, in the first variation, the gate voltage of the first transistor Q1 may be the sense amplifier reference voltage SAVREF plus the offset voltage ΔV. The offset voltage ΔV is, for example, a post-programming verification voltage. The gate voltage of the second transistor Q2 may be the sense amplifier reference voltage SAVREF. In other words, the gate voltage of the first transistor Q1 is made higher than the gate voltage of the second transistor Q2. When it is detected that the leakage current is higher than the threshold, the controller (e.g., 503) of the flash memory device 1300 may perform a post-programming operation. Fig.13 As shown, the leakage current of each bit line can be detected separately. In the second variation, the gate voltage of the first transistor Q1 can be configured to be greater than the bit line voltage for performing a normal read operation. In the third variation, as shown in FIG. Fig.12 As shown, a switch (not shown) can be configured to selectively couple the first transistor Q1 to multiple bit lines (as shown by the dotted line) in the post-programming verification step S607 to detect the leakage current of multiple bit lines together. In a fourth variation, the word line voltage can be configured to be greater than the voltage of the unselected word line for reading. The above four variations can be appropriately combined to further improve the sensitivity of leakage current detection.

[0049] In summary, the present disclosure is suitable for use in a memory device and is capable of erasing a memory block more efficiently by minimizing leakage current while preserving the number of erase pulses without significantly increasing the amount of time required to erase the memory block. Therefore, the present disclosure provides green technology by reducing the power consumption of a non-volatile memory device. In addition, since the reliability and durability of the non-volatile memory device of the present invention are improved, the present invention provides a sustainable non-volatile memory device to reduce resource waste.

[0050] Unless explicitly stated otherwise, none of the elements, actions, or instructions used in the detailed description of the disclosed embodiments of the present application should be considered absolutely critical or essential to the present disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the structures of the disclosed embodiments without departing from the scope or spirit of the present disclosure. In summary, the present disclosure is intended to cover various modifications and variations of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.< / m>

Claims

1. A method for erasing a non-volatile memory device, comprising: Initiating an erase operation of the memory block by applying an erase condition to the memory block; performing a first erase verification procedure compared with a first erase verification voltage on at least a portion of the memory block; adjusting the first erase verify voltage in response to at least the portion of the memory block having passed the first erase verify procedure; performing a second erase verification procedure on at least the portion of the memory block that is compared with the adjusted first erase verification voltage; Performing a post-program verification procedure on the memory block by comparing with a post-program verification voltage to detect over-erased memory cells or leakage current of the memory block; Determining whether the adjusted first erase verification voltage reaches a final erase verification voltage, and whether the post-program verification voltage reaches a final post-program verification voltage; as well as In response to the adjusted first erase verify voltage having reached the final erase verify voltage and the post program verify voltage having reached the final post program verify voltage, the erase operation is completed.

2. The erasing method according to claim 1, Wherein performing the first erasure verification procedure on at least the portion of the memory block comprises: determining whether a threshold voltage distribution of at least the portion of the memory block is lower than the first erase verification voltage; In response to the threshold voltage distribution of at least the portion of the memory block being lower than the first erase verification voltage, determining that at least the portion of the memory block has passed the first erase verification procedure; as well as In response to a portion of the threshold voltage distribution of at least the portion of the memory block not being lower than the first erase verification voltage, determining that at least the portion of the memory block has failed the first erase verification procedure, The performing of the second erasure verification procedure on at least the portion of the memory block comprises: determining whether a threshold voltage distribution of at least the portion of the memory block is lower than the adjusted first erase verification voltage; In response to the threshold voltage distribution of at least the portion of the memory block being lower than the adjusted first erase verification voltage, determining that at least the portion of the memory block has passed the second erase verification procedure; and In response to a portion of the threshold voltage distribution of at least the portion of the memory block not being lower than the adjusted first erase verify voltage, it is determined that at least the portion of the memory block has failed the second erase verify procedure.

3. The erasing method according to claim 2, wherein adjusting the first erase verification voltage in response to at least the portion of the memory block having passed the first erase verification procedure comprises: The first erase verify voltage is lowered to a second erase verify voltage in response to at least the portion of the memory block having passed the first erase verify procedure, wherein the second erase verify voltage is between the final erase verify voltage and the first erase verify voltage.

4. The erasing method according to claim 3, wherein: In response to the adjusted first erase verification voltage not reaching the final erase verification voltage or the post-program verification voltage not reaching the final post-program verification voltage, the second erase verification procedure is performed.

5. The erasing method according to claim 2, further comprising: In response to having determined that at least the portion of the memory block has failed the first erase verification procedure or the second erase verification procedure, the erase condition is again applied to the memory block.

6. The erasing method according to claim 2, further comprising: In response to determining that at least the portion of the memory block has failed the first erase verify procedure or the second erase verify procedure, increasing an erase pulse cycle count, wherein if the erase pulse cycle count is not greater than the expected number, the same erase condition is applied to the memory block again, and Wherein if the erase pulse cycle count is greater than the expected number, the erase condition will be adjusted and then applied to the memory block.

7. The erasing method according to claim 6, further comprising: before the leakage current has been detected by the post-program verification procedure, adjusting the erase condition according to a first step level; as well as After the leakage current has been detected by the post-program verification procedure, the erase condition is adjusted according to a second step level that is less than the first step level.

8. The erasing method according to claim 1, further comprising: In response to the threshold voltage distribution of the memory block being higher than the post-program verification voltage, determining that the post-program verification procedure is passed, In response to a portion of the threshold voltage distribution of the memory block being not higher than the post-program verification voltage, determining that the post-program verification procedure has not been passed, and In response to determining that the post-program verification procedure has not passed, the erase condition is changed to be applied to only a portion of the memory block instead of the entire memory block.

9. The erasing method according to claim 2, wherein the post-programming verification voltage is higher than the final post-programming verification voltage used to determine whether the memory block is over-erased, and a post-programming procedure is performed in response to failure to pass the post-programming verification procedure to increase the threshold voltage distribution of the over-erased storage cells of the memory block.

10. The erasing method according to claim 1, wherein the first erasure verification procedure is performed on a portion of the memory block instead of the entire memory block.

11. A memory device comprising: memory blocks, and A controller is coupled to the memory block and is configured to: initiating an erase operation of the memory block by applying an erase condition to the memory block; performing a first erase verification procedure compared with a first erase verification voltage on at least a portion of the memory block; adjusting the first erase verify voltage in response to at least the portion of the memory block having passed the first erase verify procedure; performing a second erase verification procedure on at least the portion of the memory block that is compared with the adjusted first erase verification voltage; Performing a post-program verification procedure on the memory block by comparing with a post-program verification voltage to detect over-erased memory cells or leakage current of the memory block; Determining whether the adjusted first erase verification voltage reaches a final erase verification voltage, and whether the post-program verification voltage reaches a final post-program verification voltage; as well as In response to the adjusted first erase verify voltage having reached the final erase verify voltage and the post program verify voltage having reached the final post program verify voltage, the erase operation is completed.

12. The memory device according to claim 11, The controller is configured to perform the first erasure verification procedure by: determining whether a threshold voltage distribution of at least the portion of the memory block is lower than the first erase verification voltage; In response to the threshold voltage distribution of at least the portion of the memory block being lower than the first erase verification voltage, determining that at least the portion of the memory block has passed the first erase verification procedure; as well as In response to a portion of the threshold voltage distribution of at least the portion of the memory block not being lower than the first erase verification voltage, determining that at least the portion of the memory block has failed the first erase verification procedure, The controller is configured to implement the second erasure verification procedure by: determining whether a threshold voltage distribution of at least the portion of the memory block is lower than the adjusted first erase verification voltage; In response to the threshold voltage distribution of at least the portion of the memory block being lower than the adjusted first erase verification voltage, determining that at least the portion of the memory block has passed the second erase verification procedure; as well as In response to a portion of the threshold voltage distribution of at least the portion of the memory block being not lower than the adjusted first erase verify voltage, it is determined that at least the portion of the memory block has not passed the second erase verify procedure.

13. The memory device of claim 12 , wherein the controller is configured to adjust the first erase verification voltage by: The first erase verify voltage is lowered to a second erase verify voltage in response to at least the portion of the memory block having passed the first erase verify procedure, wherein the second erase verify voltage is between the final erase verify voltage and the first erase verify voltage.

14. The memory device of claim 13, wherein the controller is further configured to: In response to the adjusted first erase verification voltage not reaching the final erase verification voltage or the post-program verification voltage not reaching the final post-program verification voltage, the second erase verification procedure is performed.

15. The memory device of claim 12, wherein the controller is further configured to: In response to having determined that at least the portion of the memory block has failed the first erase verification procedure or the second erase verification procedure, the erase condition is again applied to the memory block.

16. The memory device of claim 12, wherein the controller is further configured to: In response to determining that at least the portion of the memory block has failed the first erase verify procedure or the second erase verify procedure, increasing an erase pulse cycle count, wherein if the erase pulse cycle count is not greater than the expected number, the same erase condition is applied to the memory block again, and Wherein if the erase pulse cycle count is greater than the expected number, the erase condition will be adjusted and then applied to the memory block.

17. The memory device of claim 16, wherein the controller is further configured to: before the leakage current has been detected by the post-program verification procedure, adjusting the erase condition according to a first step level; and After the leakage current has been detected by the post-program verification procedure, the erase condition is adjusted according to a second step level that is less than the first step level.

18. The memory device of claim 11, wherein the controller is further configured to: In response to the threshold voltage distribution of the memory block being higher than the post-program verification voltage, determining that the post-program verification procedure is passed, In response to a portion of the threshold voltage distribution of the memory block being not higher than the post-program verification voltage, determining that the post-program verification procedure has not been passed, and In response to determining that the post-program verification procedure has not passed, the erase condition is changed to be applied to only a portion of the memory block instead of the entire memory block.

19. The memory device of claim 12, wherein the post-programming verification voltage is higher than the final post-programming verification voltage used to determine whether the memory block is over-erased, and a post-programming procedure is performed in response to failure to pass the post-programming verification procedure to increase the threshold voltage distribution of the over-erased memory cells of the memory block.

20. The memory device according to claim 11, further comprising a sense amplifier circuit, a pull-up circuit, the sense amplifier circuit comprising: Reference storage unit; A first transistor, coupled between the pull-up circuit and the memory block, configured to output a bit line current; A second transistor, coupled between the pull-up circuit and the reference memory cell, configured to output a reference current; as well as an operational amplifier, comparing the bit line current with the reference current, thereby outputting a voltage difference between the bit line current and the reference current, The controller is further configured to control one of the following or a combination thereof in the post-programming verification procedure: providing a gate voltage higher than a gate voltage of the second transistor to the first transistor; configuring a gate voltage of the first transistor to be greater than a bit line voltage for performing a normal read operation; coupling the first transistor to a plurality of bit lines of the memory block; as well as The word line voltage is configured to be greater than the voltage of the unselected word lines for reading.

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