Device for interconnection and packaging circuit

Abstract

The embodiment of the invention discloses a device for interconnection and a packaging circuit. The interconnect device includes a first signal trace and a second signal trace. The first signal trace includes a first portion at a first layer of the substrate and a plurality of disk-shaped portions at a second layer of the substrate, the first portion being connected to the plurality of disk-shaped portions through conductive vias. The second signal trace includes a first portion at the third layer of the substrate and a plurality of disk-shaped portions at the second layer of the substrate, the first portion being connected to the plurality of disk-shaped portions through conductive vias. In some embodiments, there is crosstalk between the first signal trace and the second signal trace, and a mutual capacitance between the plurality of disk-shaped portions of the first signal trace and the plurality of disk-shaped portions of the second signal trace may increase a mutual capacitance between the first signal trace and the second signal trace, which will counteract the mutual inductance, reducing crosstalk between the first signal trace and the second signal trace.

Description

Technical Field

[0001] The present invention relates generally to the field of integrated circuits, and more particularly to an apparatus and package for interconnecting circuits. Background Art

[0002] In 2.5D and 3D packaging technologies, multiple integrated circuit dies are located in the same package. The integrated circuit dies are interconnected by D2D (Die to Die). D2D interconnection requires low latency, low power consumption, and high reliability. When a signal line transmits a signal, an electric field and a magnetic field are generated. Crosstalk refers to the energy coupling from one signal line to an adjacent signal line due to the interaction of the electric field and the magnetic field generated by the signal line. As the communication frequency increases and the physical distance between signal lines decreases, crosstalk can have a negative impact on signal transmission. As the interconnection bandwidth requirements and chip performance increase, the IO frequency and signal line density of D2D increase accordingly, and crosstalk restricts the performance of D2D interconnection. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides a device for interconnecting integrated circuit dies and a packaging circuit to reduce crosstalk between signal traces.

[0004] According to a first aspect of an embodiment of the present invention, a device for interconnection is provided. The device includes: a first signal trace and a second signal trace. The first signal trace includes a first portion located on a first layer of a substrate and a plurality of disc-shaped portions located on a second layer of the substrate, and the first portion is connected to the plurality of disc-shaped portions through a conductive via. The second signal trace includes a first portion located on a third layer of the substrate and a plurality of disc-shaped portions located on the second layer of the substrate, and the first portion is connected to the plurality of disc-shaped portions through a conductive via.

[0005] Optionally, the first portion of the first signal trace and the first portion of the second signal trace extend along a first direction, and the plurality of disk-shaped portions of the first signal trace and the plurality of disk-shaped portions of the second signal trace are alternately arranged in the first direction.

[0006] Optionally, the first portion of the first signal trace and the first portion of the second signal trace are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals.

[0007] Optionally, the plurality of disk-shaped portions of the first signal trace and the plurality of disk-shaped portions of the second signal trace increase mutual capacitance to offset the mutual inductance.

[0008] Optionally, the device comprises a plurality of the first signal traces, a first portion of the first signal traces comprising a toothed portion; and / or the device comprises a plurality of the second signal traces, a first portion of the second signal traces comprising a toothed portion.

[0009] Optionally, adjacent first signal traces are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals, and the toothed portions of adjacent first signal traces increase the mutual capacitance to offset the mutual inductance; and / or adjacent second signal traces are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals, and the toothed portions of adjacent second signal traces increase the mutual capacitance to offset the mutual inductance.

[0010] Optionally, the first signal trace and the second signal trace comprise signal traces for a high speed memory package.

[0011] According to a second aspect of an embodiment of the present invention, there is provided a packaged circuit, comprising: a substrate; a first integrated circuit die and a second integrated circuit die located on the substrate; and a first signal trace and a second signal trace connecting the first integrated circuit die and the second integrated circuit die. The first signal trace comprises a first portion located on a first layer of the substrate and a plurality of disc-shaped portions located on a second layer of the substrate, the first portion being connected to the plurality of disc-shaped portions via a conductive via. The second signal trace comprises a first portion located on a third layer of the substrate and a plurality of disc-shaped portions located on a second layer of the substrate, the first portion being connected to the plurality of disc-shaped portions via a conductive via.

[0012] Optionally, the first portion of the first signal trace and the first portion of the second signal trace extend along a first direction, and the plurality of disk-shaped portions of the first signal trace and the plurality of disk-shaped portions of the second signal trace are alternately arranged in the first direction.

[0013] Optionally, the first portion of the first signal trace and the first portion of the second signal trace are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals.

[0014] Optionally, the plurality of disk-shaped portions of the first signal trace and the plurality of disk-shaped portions of the first signal trace increase mutual capacitance to offset the mutual inductance.

[0015] Optionally, the packaged circuit includes a plurality of the first signal traces, a first portion of the first signal traces includes a toothed portion; and / or the packaged circuit includes a plurality of the second signal traces, a first portion of the second signal traces includes a toothed portion.

[0016] Optionally, adjacent first signal traces are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals, and the toothed portions of adjacent first signal traces increase the mutual capacitance to offset the mutual inductance; and / or adjacent second signal traces are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals, and the toothed portions of adjacent second signal traces increase the mutual capacitance to offset the mutual inductance.

[0017] Optionally, the first integrated circuit die is a high-speed memory.

[0018] According to the interconnect device and packaged circuit of the embodiments of the present invention, the mutual capacitance between the multiple disk-shaped portions of the first signal trace and the multiple disk-shaped portions of the second signal trace can increase the mutual capacitance between the first signal trace and the second signal trace, which will offset the mutual inductance between the first signal trace and the second signal trace and reduce the crosstalk between the first signal trace and the second signal trace. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0020] Figure 1 is a top view of a packaged circuit according to an embodiment of the present invention;

[0021] Figure 2 is a cross-sectional view of a packaged circuit according to an embodiment of the present invention along a first direction;

[0022] Figure 3A is a partial cross-sectional view of an interconnection device of the related art along a first direction;

[0023] Figure 3B is a partial cross-sectional view of an interconnection device of the related art along a second direction;

[0024] Figure 4 is a partial cross-sectional view of an interconnection device according to an embodiment of the present invention along a first direction;

[0025] Figure 5A is a partial cross-sectional view of an interconnection device according to an embodiment of the present invention along a second direction;

[0026] Figure 5B yes Figure 5A a top view of a second layer of a substrate of an interconnect device;

[0027] Fig. 6A is a partial cross-sectional view of an interconnection device along a second direction according to another embodiment of the present invention;

[0028] Figure 6B yes Fig. 6A a top view of a second layer of a substrate of an interconnect device;

[0029] Figure 7 is a top view of a first portion of a plurality of first signal traces in one embodiment of the present invention;

[0030] Figure 8 is a top view of a first portion of a plurality of first signal traces in another embodiment of the present invention;

[0031] Figure 9A-9E are cross-sectional views of the interconnection device of the present invention at various stages of the manufacturing method;

[0032] Fig.10 A far-end crosstalk simulation method for an interconnect device of the present invention is shown;

[0033] Fig.11 The far-end crosstalk simulation result of the interconnection device of the present invention is shown;

[0034] Fig.12 is a schematic diagram of a testing method of an interconnection device of the present invention;

[0035] Fig.13 Shows Fig.12 Test results for the test method shown. DETAILED DESCRIPTION

[0036] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for those skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, flows, components and circuits are not described in detail.

[0037] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0038] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".

[0039] In the description of this application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0040] Figure 1 is a top view block diagram of an exemplary packaged circuit of the present invention. Figure 2is a cross-sectional view of the packaged circuit along a first direction. The first direction is Figure 1 The AA direction in the second direction is Figure 1 The BB direction in the figure is perpendicular to the first direction and the second direction. It should be understood that the sizes of the components are not necessarily to scale. For the purpose of illustrating the features described, some components may be exaggerated or emphasized in size or position. Figure 1 and Figure 2 As shown, the packaged circuit includes: a first integrated circuit die 101 and a second integrated circuit die 103, a device for interconnection 105, a package substrate 107, and a circuit board 109. The packaged circuit also includes a protection frame (not shown), and the first integrated circuit die 101, the second integrated circuit die 103 and the interconnection device 105 are accommodated in a space defined by the protection frame.

[0041] The packaged circuit includes at least two integrated circuit dies, thereby realizing computing power stacking or heterogeneous integration. The first integrated circuit die 101 and the second integrated circuit die 103 are bare dies. The first integrated circuit die 101 and the second integrated circuit die 103 are, for example, logic chips, high-speed memories, etc. Logic chips are, for example, CPUs, GPUs, and TPUs. High-speed memories are, for example, high-bandwidth memories (HBM).

[0042] The first integrated circuit die 101 and the second integrated circuit die 103 are arranged on the interconnection device 105. The first integrated circuit die 101 and the second integrated circuit die 103 communicate through the interconnection device 105, and are also connected to the package substrate 107 and the circuit board 109 through the interconnection device 105. The first integrated circuit die 101 and the second integrated circuit die 103 include a D2D interface circuit, and communicate according to one or more of the XSR protocol, the BoW protocol, the OpenHBI protocol, and the UCIe protocol.

[0043] The interconnection device 105 includes a substrate 106, solder balls 113 located on a first surface of the substrate 106, solder balls 117 located on a second surface of the substrate 106, and a signal trace 111. The first surface and the second surface are opposite. The solder balls 113 and 117 are, for example, C4 solder balls (C4 bumps) or C2 micro bumps (micro bumps), but are not limited to these two types. The first integrated circuit die 101 and the second integrated circuit die 103 are connected to the interconnection device 105 through the corresponding solder balls 113. The signal trace 111 connects the solder balls 113 corresponding to the D2D interface circuit of the first integrated circuit die 101 and the solder balls 113 corresponding to the D2D interface circuit of the second integrated circuit die 103, thereby realizing the interconnection of the first integrated circuit die 101 and the second integrated circuit die 103.

[0044] The interconnection device 105 also includes a signal trace 115. The signal trace 115 is used to connect the solder ball 113 on the first surface of the substrate 106 and the solder ball 117 on the second surface of the substrate 106. The signal trace 115 is, for example, a plated through-hole. The substrate 106 and the package substrate 107 are connected through the solder ball 117. The package substrate 107 and the circuit board 109 are connected through the solder ball 120. The solder ball 120 is, for example, a BGA solder ball. The solder ball 117 and the solder ball 120 are connected through the signal trace 119 in the package substrate 107. In this way, the communication between the first integrated circuit die 101 and the second integrated circuit die 103 and other external circuits can be realized.

[0045] In some embodiments, the interconnection device 105 is formed by forming signal traces and solder balls on a silicon substrate, and the interconnection device 105 is also called a silicon interposer. The interconnection device 105 of the present invention is not limited to a silicon interposer, but can also be a silicon bridge or the like.

[0046] The signal traces 111 are disposed on multiple layers of the substrate 106. The following description will be made by taking the case where the signal traces 111 are disposed on two layers of the substrate 106 as an example. Figure 2 As shown, the signal trace 111 includes a first signal trace 1111 and a second signal trace 1112. The first signal trace 1111 includes a first portion located on the first layer of the substrate 106, and the first portion is connected to the corresponding solder ball 113 through a conductive via. The second signal trace 1112 includes a first portion located on the third layer of the substrate 106, and the first portion is connected to the corresponding solder ball 113 through a conductive via. The first portion of the first signal trace 1111 and the first portion of the second signal trace 1112 are connected along a first direction (i.e., Figure 1 The first portion of the first signal trace 1111 and the first portion of the second signal trace 1112 are located below the gap between the first integrated circuit die 101 and the second integrated circuit die 103.

[0047] As the interconnection bandwidth requirements of integrated circuit dies and chip performance increase, the number of signal traces 111 increases, the physical distance between the first signal trace 1111 and the second signal trace 1112 decreases, and the crosstalk between the first signal trace 1111 and the second signal trace 1112 becomes more serious.

[0048] Figure 3A is a partial cross-sectional view of an interconnection device in the related art along a first direction. Figure 3B1 is a partial cross-sectional view of an interconnection device of the related art along the second direction. One method of reducing crosstalk in the related art is to set a ground layer 151 between the first signal trace 1111 and the second signal trace 1112, and the first signal trace 1111 and the second signal trace 1112 are shielded by the ground layer 151. Figure 3A and 3B As shown, a dielectric material layer 152 is further provided between the first layer where the first signal trace 1111 is located and the ground layer 151, and a dielectric material layer 153 is further provided between the third layer where the second signal trace 1112 is located and the ground layer 151. The ground layer 151 is a metal layer and is connected to the ground node VSS. Isolation and shielding through the ground layer 151 will not only increase the parasitic capacitance of the signal trace, increase the signal loss, and deteriorate the electrical performance, but also due to process and space limitations, the connection of VSS at different positions is not sufficient, resulting in poor crosstalk isolation effect, which will worsen the crosstalk.

[0049] The present invention proposes a crosstalk solution that does not require a ground plane. Crosstalk refers to energy from one signal crossing into the electric field or magnetic field (or both) of an adjacent signal line, thereby affecting the signal energy of the adjacent signal line. Crosstalk can have an electric component caused by an electric field, thereby producing a capacitive crosstalk component. Crosstalk can have a magnetic component caused by a magnetic field, thereby producing an inductive crosstalk component. Far-end crosstalk (FEXT) can be expressed as the difference between capacitive crosstalk and inductive crosstalk, and can be calculated by the following formula.

[0050]

[0051] Among them, a is the coupling coefficient, a specific circuit has a specific coupling coefficient, Cm is the mutual capacitance, Cs is the self-capacitance, Lm is the mutual inductance, and Ls is the self-inductance. At present, in 2.5D packaging, the far-end crosstalk between signals is dominated by inductive coupling, that is, Lm / Ls>Cm / Cs. In order to reduce far-end crosstalk, it is necessary to increase the mutual capacitance Cm so that Cm / Cs≈Lm / Ls.

[0052] Figure 4 is a partial cross-sectional view of an interconnection device according to an embodiment of the present invention along a first direction. Figure 4 It is a view looking into the interior of the interconnection device along the second direction. Figure 4 FIG. 1 shows a local area where the first signal trace 1111 and the second signal trace 1112 are located. Figure 4As shown, the first signal trace 1111 includes a first portion located on the first layer L1 of the substrate 106 and a plurality of disc-shaped portions 122 located on the second layer L2 of the substrate 106, the first portion being connected to the plurality of disc-shaped portions 122 through a conductive via 123, and the second signal trace 1112 includes a first portion located on the third layer L3 of the substrate 106 and a plurality of disc-shaped portions 124 located on the second layer L2 of the substrate 106, the first portion being connected to the plurality of disc-shaped portions 124 through a conductive via 125. The second layer L2 is located between the first layer L1 and the third layer L3. A dielectric material layer 121 is provided between the first layer L1 and the second layer L2, and between the second layer L2 and the third layer L3. The shapes of the disc-shaped portion 122 and the disc-shaped portion 124 are not limited, and may be, for example, a triangle, a rectangle, a diamond, a circle, etc. The shape of the disc-shaped portion 122 and the shape of the disc-shaped portion 124 may be the same or different.

[0053] According to an embodiment of the present invention, the first signal trace 1111 and the second signal trace 1112 are used to realize D2D interconnection between the first integrated circuit die 101 and the second integrated circuit die 103, and the signal is transmitted through the first signal trace 1111 and the first part of the second signal trace 1112. The first part of the first signal trace and the first part of the second signal trace are physically close, so that magnetic coupling is induced when the signal is transmitted, causing mutual inductance. The multiple disk-shaped portions 122 of the first signal trace 1111 and the multiple disk-shaped portions 124 of the second signal trace 1112 also have mutual capacitance, so that the mutual capacitance of the first signal trace 1111 and the second signal trace 1112 is increased to offset the mutual inductance. That is, the disk-shaped portion 122 and the disk-shaped portion 124 increase the capacitive coupling of the first signal trace 1111 and the second signal trace 1112, thereby reducing far-end crosstalk.

[0054] It should be understood that the physical proximity described in the embodiments of the present invention means that the physical distance is less than or equal to a predetermined value, wherein the size of the predetermined value is determined according to actual needs and processes, and the embodiments of the present invention do not limit this.

[0055] The material of the first portion of the first signal trace 1111 and the first portion of the second signal trace 1112 is metal. The material of the disc-shaped portions 122 and 124 is also metal. The material of the disc-shaped portions 122 and 124 and the material of the first portion may be the same or different.

[0056] Figure 5A is a partial cross-sectional view of an interconnection device according to an embodiment of the present invention along the second direction. Figure 5A It is a view looking into the interior of the interconnection device along the first direction. Figure 5B yes Figure 5A A top view of a second layer of a substrate of an interconnect device in FIG. Figure 5A and5B As shown, the plurality of disk-shaped portions 122 of the first signal trace 1111 and the plurality of disk-shaped portions 124 of the second signal trace 1112 are aligned in a first direction and are alternately arranged in the first direction. The first direction is the signal transmission direction of the first signal trace 1111 and the second signal trace 1112, and is also the extension direction of the first portion.

[0057] Fig. 6A is a partial cross-sectional view of an interconnection device according to another embodiment of the present invention along the second direction. Fig. 6A It is a view looking into the interior of the interconnection device along the first direction. Figure 6B yes Fig. 6A A top view of a second layer of a substrate of an interconnect device in FIG. Fig. 6A and 6B As shown, the plurality of disk-shaped portions 122 of the first signal trace 1111 and the plurality of disk-shaped portions 124 of the second signal trace 1112 are staggered in the first direction and are alternately arranged in the first direction. The staggered distance between the disk-shaped portions 122 of the first signal trace 1111 and the disk-shaped portions 124 of the second signal trace 1112 is S. The staggered disk-shaped portions 122 of the first signal trace 1111 and the disk-shaped portions 124 of the second signal trace 1112 means that the first portion of the first signal trace 1111 and the first portion of the second signal trace 1112 are staggered (from a top view).

[0058] Figure 7 FIG. 1 is a top view of a first portion of a plurality of first signal traces in one embodiment of the present invention. Figure 7 As shown, the first portions of the plurality of first signal traces are in the shape of strips and are parallel to each other.

[0059] As the interconnection bandwidth requirements of integrated circuit dies and chip performance increase, the physical spacing between the first signal traces 1111 gradually decreases, and the crosstalk between the first signal traces 1111 gradually increases. The embodiment of the present invention also provides a method for reducing the crosstalk between the first signal traces 1111. Figure 8 FIG. 1 is a top view of a first portion of a plurality of first signal traces in another embodiment of the present invention. Figure 8As shown, the first portion of the first signal trace 1111 includes a toothed portion 127. The toothed portion 127 is also located in the first layer L1, has the same material as other locations of the first portion and is formed simultaneously in the process. Adjacent first signal traces 1111A and 1111B (or 1111B and 1111C) are physically close, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals. The toothed portions 127 of adjacent first signal traces 1111 increase the relative area between adjacent first signal traces 1111, so that the mutual capacitance between adjacent first signal traces 1111 increases, thereby offsetting the mutual inductance and reducing far-end crosstalk. The shape of the toothed portion 127 is not limited, and can be rectangular, triangular, semicircular, etc.

[0060] It is understood that the second signal trace 1112 may also be provided with a toothed portion according to the above solution. The toothed portion of the second signal trace 1112 is provided on the third layer L3.

[0061] In some embodiments, one of the first signal trace 1111 and the second signal trace 1112 is provided with a toothed portion, while the other does not have a toothed portion. For example, if the crosstalk between the first signal trace 1111 and the second signal trace 1112 is not obvious, a toothed portion may not be provided.

[0062] Figure 9A-9E 1 is a cross-sectional view of the interconnection device 105 of the present invention at various stages of the manufacturing method. The interconnection device 105 can be formed by the following steps.

[0063] The first step, such as Fig.9A As shown, a first portion of a second signal trace 1112 is formed on a substrate 131, and a dielectric material layer 133 is covered on the first portion of the second signal trace 1112. It is understood that other functional layers may be provided between the substrate 131 and the first portion of the second signal trace 1112. The dielectric material layer 133 may be, for example, a silicon oxide layer and / or a silicon nitride layer, and the substrate 131 may be, for example, a silicon substrate. The first portion of the second signal trace 1112 may be formed by depositing a metal and then patterning it.

[0064] The second step is, Fig. 9B As shown, a conductive via 125 is formed in the dielectric material layer 133, and disc-shaped portions 122 and 124 are formed on the dielectric material layer 133. The disc-shaped portions 122 and 124 can be formed by depositing metal and then patterning. The conductive via 125 penetrates the dielectric material layer 133 to achieve electrical connection between the first portion of the second signal trace 1112 and the disc-shaped portion 124.

[0065] The third step is Fig. 9CAs shown, a dielectric material layer 135 is covered on the dielectric material layer 133 and the disk-shaped portions 122 and 124, and a conductive via 123 is formed in the dielectric material layer 135. The conductive via 123 penetrates the dielectric material layer 135 above the disk-shaped portion 122. The dielectric material layers 133 and 135 constitute Figure 4 , Figure 5A and Fig. 6A The dielectric material layer 121 in.

[0066] The fourth step is Fig.9D As shown, the first portion of the first signal trace 1111 is formed on the dielectric material layer 121. The first portion of the first signal trace 1111 can be formed by depositing metal and then patterning. The patterning process can also simultaneously form Figure 8 The toothed portion 127 is shown.

[0067] Step 5: Fig.9E As shown, a dielectric material layer 137 is covered on the first portion of the first signal trace 1111, a conductive via 141 penetrating the dielectric material layer 137 is formed, a conductive via 143 penetrating the dielectric material layer 137 and the dielectric material layer 121 is formed, and corresponding solder balls 113 are arranged above the conductive via 141 and the conductive via 143. The conductive via 141 connects the first portion of the first signal trace 1111, and the conductive via 143 connects the first portion of the second signal trace 1112. The conductive via 143 can be formed by the following steps: forming a portion penetrating the dielectric material layer 121, depositing the dielectric material layer 137, and then forming a portion penetrating the dielectric material layer 137.

[0068] In summary, the method for manufacturing the interconnection device according to the embodiment of the present invention is simple and can be realized under current process conditions without requiring any additional process improvement solutions.

[0069] Fig.10 The far-end crosstalk simulation method of the interconnection device of the present invention is shown. Fig.11 Figure 2 shows the simulation results of far-end crosstalk of the interconnection device of the present invention. Fig.10 As shown, when a signal sig1 is input at the left end of the first signal trace 1111, the signal transmission on the first signal trace 1111 affects the second signal trace 1112, wherein the impact on the left end of the second signal trace 1112 is called near-end crosstalk, and the impact on the right end of the second signal trace 1112 is called far-end crosstalk. In the simulation, when the signal sig1 is input at the left end of the first signal trace 1111, the detection signal sig2 at the right end of the second signal trace 1112 is simulated, and the far-end crosstalk generated by the first signal trace 1111 on the second signal trace 1112 is simulated. Fig.11 In the figure, the black line is the Figure 3A and 3BThe simulation results of the crosstalk reduction scheme are shown in red. Figure 4 The simulation results of the crosstalk reduction scheme. Fig.11 In the figure, the horizontal axis represents the frequency of the input signal, and the vertical axis represents the far-end crosstalk (in dB). Far-end crosstalk Y = b*lg(sig2 / sig1). For example, if the input signal sig1 is 1V, the detection signal is 0.01V, b = 20, and the far-end crosstalk is -40dB. Fig.11 As shown, the solution of the present invention reduces far-end crosstalk.

[0070] Fig.12 It is a schematic diagram of a testing method of the interconnection device of the present invention. Fig.13 Shows Fig.12 The test results of the test method shown. Fig.12 As shown, a signal IN1 is input at one end of the first signal trace 1111, a signal IN2 is input at one end of the second signal trace 1112, a signal OUT1 is detected at the other end of the first signal trace 1111, and a signal OUT2 is detected at the other end of the second signal trace 1112. That is, Fig.12 It is an eye diagram test. Eye diagram analysis is widely used in high-speed transmission interfaces. By superimposing signals on each other in a fixed period, the effects of noise and inter-symbol crosstalk can be analyzed. Eye diagram is an important tool for signal integrity analysis in high-speed interconnection systems. The larger the eye diagram opening, the smaller the inter-symbol interference. Conversely, the smaller the eye diagram opening, the greater the inter-symbol crosstalk. Fig.13 Figure A is the one using Figure 3A and 3B The eye diagram of the crosstalk reduction scheme is shown in Figure B. Figure 4 The eye diagram of the crosstalk reduction scheme. Fig.13 As shown, the eye opening degree and line width of Figure B are better than those of Figure A, indicating that the solution of the present invention reduces far-end crosstalk.

[0071] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A device for interconnection, comprising: a first signal trace, the first signal trace comprising a first portion located on a first layer of a substrate and a plurality of disk-shaped portions located on a second layer of the substrate, the first portion being connected to the plurality of disk-shaped portions via a conductive via; as well as The second signal trace includes a first portion located on the third layer of the substrate and a plurality of disk-shaped portions located on the second layer of the substrate, wherein the first portion is connected to the plurality of disk-shaped portions through a conductive via.

2. The device according to claim 1, wherein: The first portion of the first signal trace and the first portion of the second signal trace extend along a first direction, and the plurality of plate-shaped portions of the first signal trace and the plurality of plate-shaped portions of the second signal trace are alternately arranged in the first direction.

3. The device according to claim 1, wherein: The first portion of the first signal trace and the first portion of the second signal trace are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals.

4. The device according to claim 3, wherein: The plurality of disk-shaped portions of the first signal trace and the plurality of disk-shaped portions of the second signal trace increase mutual capacitance to cancel the mutual inductance.

5. The device according to claim 1, wherein: The device comprises a plurality of said first signal traces, a first portion of said first signal traces comprising a toothed portion, And / or, the device comprises a plurality of the second signal traces, a first portion of the second signal traces comprising a toothed portion.

6. The device according to claim 5, wherein: The adjacent first signal traces are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals, and the toothed portions of the adjacent first signal traces increase mutual capacitance to offset the mutual inductance. and / or, The adjacent second signal traces are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals, and the toothed portions of the adjacent second signal traces increase mutual capacitance to offset the mutual inductance.

7. The device according to any one of claims 1 to 6, wherein: The first signal trace and the second signal trace comprise signal traces for a high speed memory package.

8. A packaged circuit comprising: substrate; a first integrated circuit die and a second integrated circuit die located on the substrate; as well as a first signal trace and a second signal trace connecting the first integrated circuit die and the second integrated circuit die, The first signal trace includes a first portion located on a first layer of the substrate and a plurality of disk-shaped portions located on a second layer of the substrate, the first portion being connected to the plurality of disk-shaped portions via a conductive through hole, The second signal trace includes a first portion located on the third layer of the substrate and a plurality of pad-shaped portions located on the second layer of the substrate, wherein the first portion is connected to the plurality of pad-shaped portions through a conductive via.

9. The packaged circuit according to claim 8, wherein: The first portion of the first signal trace and the first portion of the second signal trace extend along a first direction, and the plurality of plate-shaped portions of the first signal trace and the plurality of plate-shaped portions of the second signal trace are alternately arranged in the first direction.

10. The packaged circuit according to claim 8, wherein: The first portion of the first signal trace and the first portion of the second signal trace are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals.

11. The packaged circuit according to claim 10, wherein: The plurality of plate-shaped portions of the first signal trace and the plurality of plate-shaped portions of the first signal trace increase mutual capacitance to cancel the mutual inductance.

12. The packaged circuit according to claim 8, wherein: The package circuit includes a plurality of the first signal traces, a first portion of the first signal traces includes a tooth portion, And / or, the packaged circuit includes a plurality of the second signal traces, and a first portion of the second signal traces includes a toothed portion.

13. The packaged circuit according to claim 12, wherein: The adjacent first signal traces are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals, and the toothed portions of the adjacent first signal traces increase mutual capacitance to offset the mutual inductance. and / or, The adjacent second signal traces are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals, and the toothed portions of the adjacent second signal traces increase mutual capacitance to offset the mutual inductance.

14. The packaged circuit according to any one of claims 8 to 13, wherein: The first integrated circuit die is a high-speed memory.

Images