SAW (Surface Acoustic Wave) semiconductor structure with high power tolerance and preparation process thereof

Abstract

The invention discloses a surface acoustic wave (SAW) semiconductor structure with high power tolerance and a preparation process thereof, and the SAW semiconductor structure comprises a polycrystalline silicon layer arranged on a substrate, a temperature compensation layer arranged on the polycrystalline silicon layer, a piezoelectric layer arranged on the temperature compensation layer, and an interdigital electrode formed on the piezoelectric layer. An electrode lead PAD is arranged on the interdigital electrode, and the electrode lead PAD penetrates through the interdigital electrode, the piezoelectric layer and the temperature compensation layer and then is connected with the polycrystalline silicon layer. An electrode lead PAD is in direct contact with a polycrystalline silicon layer or a substrate with a high thermal conductivity coefficient, so that a high-efficiency heat transfer path is formed, and the power tolerance of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of radio frequency filters, and in particular relates to a SAW semiconductor structure with high power tolerance and a preparation process thereof. Background Art

[0002] The main function of a radio frequency (RF) filter is to attenuate signals in certain unwanted frequency bands while having minimal impact on signals in the desired frequency bands. RF filters are used in communication systems that transmit information over wireless links. For example, RF filters can be found in the RF front end of cellular base stations, mobile phones and computing devices, satellite transceivers and ground base stations, IoT (Internet of Things) devices, laptops and tablets, fixed-point radio links, and other communication systems. RF filters are also used in radars, as well as electronic and information warfare systems.

[0003] High performance RF filters used in current communication systems typically contain acoustic wave resonators, including surface acoustic wave (SAW) resonators, bulk acoustic wave (BAW) resonators, film bulk acoustic wave resonators (FBARs), and laterally excited film bulk acoustic wave resonators (XBARs), among others.

[0004] SAW resonators usually adopt POI (Piezo-On-Insulator, piezoelectric film on insulator) structure. The POI substrate stack structure generally includes a piezoelectric layer, an oxide layer, a polysilicon layer and a substrate. Interdigital electrodes are formed on the piezoelectric layer, and electrode leads (PAD) are prepared on some of the interdigital electrodes. The structure is as follows Figure 1 . The piezoelectric layer generally uses lithium niobate or lithium tantalate, and the oxide layer generally uses silicon dioxide. Since there is an order of magnitude difference in the thermal conductivity of lithium niobate, lithium tantalate, silicon dioxide and silicon (the thermal conductivity of single crystal lithium tantalate is about 4.5W / (m·k), the thermal conductivity of silicon dioxide is about 27W / (m·k), and the thermal conductivity of silicon is about 148W / (m·k)), this difference seriously hinders the transfer of heat when the device is working and reduces the power tolerance of the device. With the popularization of 5G technology and the requirement for miniaturization of filters, higher requirements are placed on the power tolerance of SAW filters. Therefore, how to enhance the heat transfer efficiency to improve power tolerance has become a problem that needs to be solved urgently. Summary of the invention

[0005] In order to solve the above problems, the present invention provides a SAW semiconductor structure with high power tolerance and its preparation process. It forms a high-efficiency heat transfer path by directly contacting the electrode lead PAD with a polysilicon layer or substrate with high thermal conductivity, thereby improving the power tolerance of the device.

[0006] The technical solution adopted by the present invention is:

[0007] In the first aspect, the present application discloses a SAW semiconductor structure with high power tolerance, comprising: a polycrystalline silicon layer arranged on a substrate, a temperature compensation layer arranged on the polycrystalline silicon layer, a piezoelectric layer arranged on the temperature compensation layer, and interdigitated electrodes formed on the piezoelectric layer, wherein the interdigitated electrodes are provided with electrode leads PAD, and the electrode leads PAD pass through the interdigitated electrodes, the piezoelectric layer and the temperature compensation layer and then are connected to the polycrystalline silicon layer.

[0008] As an optional technical solution, the substrate is made of silicon Si, silicon carbide SiC, gallium nitride GaN, aluminum oxide Al2O3 or diamond material; and the temperature compensation layer is silicon dioxide.

[0009] As an optional technical solution, the piezoelectric layer uses piezoelectric materials such as lithium niobate, lithium tantalate, aluminum nitride or scandium-doped aluminum nitride.

[0010] As an optional technical solution, the interdigitated electrodes are made of at least two materials selected from the group consisting of metal titanium Ti, aluminum Al, copper Cu, silver Ag, molybdenum Mo, tungsten W, platinum pt, AlCu alloy and TiW alloy; the electrode lead PAD is made of at least two materials selected from the group consisting of metal aluminum Al, copper Cu, silver Ag, molybdenum Mo, tungsten W and AlCu alloy.

[0011] In a second aspect, the present application discloses a process for preparing the SAW semiconductor structure in the first aspect, comprising the following steps: providing a substrate, forming a polysilicon layer on the substrate, forming a temperature compensation layer on the polysilicon layer, and forming a piezoelectric layer on the temperature compensation layer. Forming interdigital electrodes on the piezoelectric layer, etching a first groove in the thickness direction of the interdigital electrodes, the piezoelectric layer, and the temperature compensation layer using a dry etching process, and exposing the polysilicon layer at the bottom of the first groove; or etching a first groove in the thickness direction of the piezoelectric layer and the temperature compensation layer using a dry etching process, and exposing the polysilicon layer at the bottom of the first groove, and then forming interdigital electrodes on the piezoelectric layer. Depositing an electrode lead PAD in the first groove, the bottom of the electrode lead PAD is in direct contact with the polysilicon layer after deposition.

[0012] In the third aspect, the present application discloses another SAW semiconductor structure with high power tolerance, including: a polycrystalline silicon layer arranged on a substrate, a temperature compensation layer arranged on the polycrystalline silicon layer, a piezoelectric layer arranged on the temperature compensation layer, and interdigitated electrodes formed on the piezoelectric layer, wherein the interdigitated electrodes are provided with electrode leads PAD; a second groove is provided in the thickness direction of the piezoelectric layer and the temperature compensation layer, and a thermal conductive layer is filled in the second groove, and both ends of the thermal conductive layer are directly in contact with the interdigitated electrodes and the polycrystalline silicon layer respectively.

[0013] As an optional technical solution, the heat-conducting layer extends along the thickness direction to directly contact the substrate.

[0014] In a fourth aspect, the present application discloses a process for preparing the SAW semiconductor structure in the third aspect, comprising the following steps: providing a substrate, forming a polysilicon layer on the substrate, forming a temperature compensation layer on the polysilicon layer, and forming a piezoelectric layer on the temperature compensation layer. A second groove is etched in the thickness direction of the piezoelectric layer and the temperature compensation layer using a dry etching process, and the polysilicon layer is exposed at the bottom of the second groove, and then the thermal conductive layer is filled in the second groove. Alternatively, a third groove is etched in the thickness direction of the piezoelectric layer, the temperature compensation layer, and the polysilicon layer using a dry etching process, and the substrate is exposed at the bottom of the third groove, and then the thermal conductive layer is filled in the third groove. A partial interdigitated electrode layer is formed above the thermal conductive layer, so that the two ends of the thermal conductive layer are in direct contact with the interdigitated electrode and the polysilicon layer, respectively, or the two ends of the thermal conductive layer are in direct contact with the interdigitated electrode and the substrate, respectively.

[0015] As an optional technical solution, the heat conducting layer is made of at least two materials selected from the group consisting of metal aluminum Al, copper Cu, silver Ag, molybdenum Mo, tungsten W and AlCu alloy.

[0016] The beneficial effects of the present invention are as follows: in the present application, the film layer below the electrode lead PAD is completely or partially etched away, so that the PAD is in direct contact with the polysilicon or supporting layer silicon with relatively high thermal conductivity, forming a highly efficient heat transfer path and improving the power tolerance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 FIG. 1 is a schematic diagram of a SAW semiconductor structure used for a SAW resonator in the prior art.

[0018] Figure 2 Schematic diagram of a SAW semiconductor structure with high power tolerance in Example 1.

[0019] Figure 3 Schematic diagram of another SAW semiconductor structure with high power tolerance in Example 1.

[0020] Figure 4 It is a schematic diagram of the semiconductor structure after the first groove is etched in Example 2.

[0021] Figure 5 It is a schematic diagram of the semiconductor structure after the first groove is directly etched on the piezoelectric layer and the temperature compensation layer in Example 2.

[0022] Figure 6 It is a schematic diagram of another SAW semiconductor structure with high power tolerance in Example 3.

[0023] Figure 7 It is a schematic diagram of another SAW semiconductor structure with high power tolerance in Example 3.

[0024] Figure 8 It is a schematic diagram of the semiconductor structure after etching the second groove on the piezoelectric layer and the temperature compensation layer in Example 4.

[0025] Fig. 9 It is a schematic diagram of the semiconductor structure after the heat conducting layer is filled in the second groove in Example 4.

[0026] Fig.10 It is a schematic diagram of the semiconductor structure after etching the third groove on the piezoelectric layer, the temperature compensation layer, and the polysilicon layer in Example 4.

[0027] Fig.11 It is a schematic diagram of the semiconductor structure after the heat conductive layer is filled in the third groove in Example 4. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0029] Example 1

[0030] like Figure 2As shown, this embodiment discloses a SAW semiconductor structure with high power tolerance, including: a polysilicon layer 2 arranged on a substrate 1, a temperature compensation layer 3 arranged on the polysilicon layer 2, a piezoelectric layer 4 arranged on the temperature compensation layer 3, and an interdigitated electrode 6 formed on the piezoelectric layer 4, wherein an electrode lead 7 (PAD) is arranged in a partial area of ​​the interdigitated electrode 6, and the bottom of the electrode lead 7 passes through the interdigitated electrode 6, the piezoelectric layer 4 and the temperature compensation layer 3 and is connected to the polysilicon layer 2. The electrode lead 7 is generally made of metal, such as metal aluminum Al (thermal conductivity of about 237W / (m·K)), copper Cu (thermal conductivity of about 401W / (m·K)), silver Ag (thermal conductivity of about 429W / (m·K)), molybdenum Mo (thermal conductivity of about 138W / (m·K)), tungsten W (thermal conductivity of about 180W / (m·K)) and AlCu alloy. The thermal conductivity of these materials is above 100W / (m·K), which is in the same order of magnitude as silicon 148W / (m·K). The electrode lead 7 made of these materials is directly in contact with the polysilicon layer 2, which can form a good heat transfer path, which is conducive to the transfer of heat to the back of the device and improves the power tolerance of the device.

[0031] As an optional implementation, the substrate 1 is made of silicon Si, silicon carbide SiC, gallium nitride GaN, aluminum oxide Al2O3 or diamond material; and the temperature compensation layer 3 is silicon dioxide.

[0032] As an optional implementation, the piezoelectric layer 4 is made of piezoelectric materials such as lithium niobate, lithium tantalate, aluminum nitride or scandium-doped aluminum nitride.

[0033] As an optional implementation, the interdigital electrodes 6 are made of at least two materials selected from the group consisting of metal titanium Ti, aluminum Al, copper Cu, silver Ag, molybdenum Mo, tungsten W, platinum pt, AlCu alloy and TiW alloy.

[0034] It should be noted that the bottom of the electrode lead 7 can also be directly connected to the substrate 1 to form a Figure 3 The semiconductor structure shown can also form a good heat transfer path to improve the power tolerance of the device.

[0035] Example 2

[0036] This embodiment also discloses a preparation process of the SAW semiconductor structure in Embodiment 1, comprising the following steps: providing a substrate 1; forming a polysilicon layer 2 on the substrate 1; forming a temperature compensation layer 3 on the polysilicon layer 2; and forming a piezoelectric layer 4 on the temperature compensation layer 3.

[0037] Afterwards, the interdigital electrodes 6 may be formed on the piezoelectric layer 4, and then part of the interdigital electrodes 6, the piezoelectric layer 4 and the temperature compensation layer 3 may be etched away along the thickness direction of the device to form a first groove 501, forming a Figure 4 The semiconductor structure shown in FIG. 1 is formed by exposing the polysilicon layer 2 at the bottom of the first groove 501; or, after forming the piezoelectric layer 4, the first groove 501 is etched to form a semiconductor structure shown in FIG. Figure 5 The semiconductor structure shown in FIG. 1 is further provided with interdigitated electrodes 6 formed on the piezoelectric layer 4 of the structure, thereby obtaining Figure 4 The semiconductor structure shown.

[0038] Finally, an electrode lead 7 is deposited in the first groove 501. After deposition, the bottom of the electrode lead 7 is in direct contact with the polysilicon layer 2, and the following is obtained: Figure 2 The semiconductor structure shown.

[0039] The entire process only requires slight adjustments to the original process, which will not increase the process complexity and cost, thereby improving the product's market competitiveness, which is crucial in the field of semiconductor manufacturing.

[0040] Example 3

[0041] This embodiment discloses another SAW semiconductor structure with high power tolerance. The inventive concept is basically the same as that of the first embodiment. Both embodiments directly contact the material with high thermal conductivity with the polysilicon layer 2 to form a good heat transfer path to efficiently transfer heat to the back of the device. Specifically, Figure 6 As shown, the SAW semiconductor structure of this embodiment includes: a polycrystalline silicon layer 2 arranged on a substrate 1, a temperature compensation layer 3 arranged on the polycrystalline silicon layer 2, a piezoelectric layer 4 arranged on the temperature compensation layer 3, and an interdigitated electrode 6 formed on the piezoelectric layer 4, and an electrode lead 7 is arranged on the interdigitated electrode 6; a second groove 502 is provided in the thickness direction of the piezoelectric layer 4 and the temperature compensation layer 3, and the second groove 502 is filled with a thermal conductive layer 5, and the two ends of the thermal conductive layer 5 are directly in contact with the interdigitated electrode 6 and the polycrystalline silicon layer 2 respectively.

[0042] It should be noted that the heat conducting layer 5 can also extend along the thickness direction to directly contact with the substrate 1, forming a Figure 7 The semiconductor structure shown.

[0043] Except for the interdigital electrodes 6 and the heat conductive layer 5, the materials used in the other layers are the same as those in Example 1. The interdigital electrodes 6 are made of at least two materials selected from the group consisting of metal aluminum Al, copper Cu, silver Ag, molybdenum Mo, tungsten W, and AlCu alloy; the heat conductive layer 5 can be made of the same material as the interdigital electrodes 6, or a material having a higher thermal conductivity than the interdigital electrodes 6.

[0044] Example 4

[0045] This embodiment discloses a preparation process of the SAW semiconductor structure in Embodiment 3, including the following steps: providing a substrate 1; forming a polysilicon layer 2 on the substrate 1; forming a temperature compensation layer 3 on the polysilicon layer 2; and forming a piezoelectric layer 4 on the temperature compensation layer 3.

[0046] Next, a dry etching process is used to etch a second groove 502 in the thickness direction of the piezoelectric layer 4 and the temperature compensation layer 3, as shown in FIG. Figure 8 As shown, the polysilicon layer 2 is exposed at the bottom of the second groove 502, and then the heat conducting layer 5 is filled in the second groove 502 to form a Fig. 9 Alternatively, a third groove 503 is etched in the thickness direction of the piezoelectric layer 4, the temperature compensation layer 3, and the polysilicon layer 2 by using a dry etching process, such as Fig.10 As shown, the substrate 1 is exposed at the bottom of the third groove 503, and then the heat conducting layer 5 is filled in the third groove 503 to form a Fig.11 The semiconductor structure shown.

[0047] Then, a forked electrode 6 is formed on the heat conducting layer 5 so that the two ends of the heat conducting layer 5 are in direct contact with the forked electrode 6 and the polysilicon layer 2 respectively. Finally, an electrode lead 7 is formed on the forked electrode 6 to obtain a Figure 6 Alternatively, the two ends of the thermal conductive layer 5 are directly in contact with the interdigital electrodes 6 and the substrate 1, and finally the electrode leads 7 are formed on the interdigital electrodes 6 to obtain the semiconductor structure shown in FIG. Figure 7 The semiconductor structure shown.

[0048] As an optional implementation, the heat conducting layer 5 is made of at least two materials selected from the group consisting of metal aluminum Al, copper Cu, silver Ag, molybdenum Mo, tungsten W and AlCu alloy.

[0049] It should be noted that the AlCu alloys used in the present application are all AlCu alloys having a thermal conductivity greater than 100 W / (m·K).

[0050] The above description is only a specific implementation mode of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. All technical solutions that fall within the scope defined by the claims of the present invention fall within the protection scope of the present invention.

Claims

1. A SAW semiconductor structure with high power tolerance, characterized in that: include: A polysilicon layer is arranged on a substrate, a temperature compensation layer is arranged on the polysilicon layer, a piezoelectric layer is arranged on the temperature compensation layer, and interdigitated electrodes are formed on the piezoelectric layer, and electrode leads PAD are arranged on the interdigitated electrodes, and the electrode leads PAD pass through the interdigitated electrodes, the piezoelectric layer and the temperature compensation layer and then are connected to the polysilicon layer.

2. The SAW semiconductor structure with high power tolerance according to claim 1, characterized in that: The substrate is made of silicon Si, silicon carbide SiC, gallium nitride GaN, aluminum oxide Al2O3 or diamond material; the temperature compensation layer is silicon dioxide.

3. The SAW semiconductor structure with high power tolerance according to claim 1, characterized in that: The piezoelectric layer is made of piezoelectric materials such as lithium niobate, lithium tantalate, aluminum nitride or scandium-doped aluminum nitride.

4. The SAW semiconductor structure with high power tolerance according to claim 1, characterized in that: The interdigitated electrodes are made of at least two materials selected from metal titanium Ti, aluminum Al, copper Cu, silver Ag, molybdenum Mo, tungsten W, platinum pt, AlCu alloy and TiW alloy; the electrode lead PAD is made of at least two materials selected from metal aluminum Al, copper Cu, silver Ag, molybdenum Mo, tungsten W and AlCu alloy.

5. A process for preparing a SAW semiconductor structure, characterized in that: The steps include: providing a substrate; forming a polysilicon layer on the substrate; forming a temperature compensation layer on the polysilicon layer; forming a piezoelectric layer on the temperature compensation layer; Forming interdigital electrodes on the piezoelectric layer, etching a first groove in the thickness direction of the interdigital electrodes, the piezoelectric layer, and the temperature compensation layer by a dry etching process, and exposing the polysilicon layer at the bottom of the first groove; or etching a first groove in the thickness direction of the piezoelectric layer and the temperature compensation layer by a dry etching process, and exposing the polysilicon layer at the bottom of the first groove, and then forming interdigital electrodes on the piezoelectric layer; An electrode lead PAD is deposited in the first groove, and after the deposition, the bottom of the electrode lead PAD is in direct contact with the polysilicon layer.

6. A SAW semiconductor structure having high power tolerance, characterized in that: include: A polysilicon layer is arranged on a substrate, a temperature compensation layer is arranged on the polysilicon layer, a piezoelectric layer is arranged on the temperature compensation layer, and interdigitated electrodes are formed on the piezoelectric layer, and an electrode lead PAD is arranged on the interdigitated electrodes; a second groove is arranged in the thickness direction of the piezoelectric layer and the temperature compensation layer, and a thermal conductive layer is filled in the second groove, and two ends of the thermal conductive layer are directly in contact with the interdigitated electrodes and the polysilicon layer respectively.

7. The SAW semiconductor structure with high power tolerance according to claim 6, characterized in that: The heat conducting layer extends along the thickness direction to directly contact with the substrate.

8. A process for preparing a SAW semiconductor structure, characterized in that: The steps include: providing a substrate; forming a polysilicon layer on the substrate; forming a temperature compensation layer on the polysilicon layer; forming a piezoelectric layer on the temperature compensation layer; A second groove is etched in the thickness direction of the piezoelectric layer and the temperature compensation layer by a dry etching process, and the polysilicon layer is exposed at the bottom of the second groove, and then the thermal conductive layer is filled in the second groove; or a third groove is etched in the thickness direction of the piezoelectric layer, the temperature compensation layer, and the polysilicon layer by a dry etching process, and the substrate is exposed at the bottom of the third groove, and then the thermal conductive layer is filled in the third groove; An interdigital electrode layer is formed above the heat conducting layer, so that two ends of the heat conducting layer are in direct contact with the interdigital electrodes and the polysilicon layer respectively, or two ends of the heat conducting layer are in direct contact with the interdigital electrodes and the substrate respectively.

9. The process for preparing a SAW semiconductor structure according to claim 8, characterized in that: The heat conducting layer is made of at least two materials selected from the group consisting of metal aluminum Al, copper Cu, silver Ag, molybdenum Mo, tungsten W and AlCu alloy.

Images