DS decoding optimization method and system supporting high-speed SpaceWire bus

Abstract

The present invention provides a method and system for optimizing DS decoding of a high-speed SpaceWire bus, including: a synchronous sampling module, a skew jitter error compensation module, an asynchronous buffer module and a DS decoding module; the synchronous sampling module synchronizes the input DS signal to the system sampling clock after three signal latches, and transmits the signal to the skew jitter error compensation module for data sampling compensation, and transmits the signal to the DS decoding module and the asynchronous buffer module after judging the valid data flag; the asynchronous buffer module shifts the buffer, converts the storage and marks the valid length of the data; the DS decoding module decodes, performs serial shift operations, and outputs data words and control words. The present invention realizes three-level synchronous sampling, reduces the risk of signal competition and risk; the bus has a high rate, and can realize the decoding function of the bus at 200Mbps~400Mbps; sampling compensation for sampling errors caused by DS signal jitter and skew, and at the same time adopts an optimized DS decoding algorithm to solve decoding errors caused by signal jitter and skew.

Description

Technical Field

[0001] The present invention belongs to the technical field of FPGA chips, and in particular, relates to a method and system for optimizing DS decoding of a SpaceWire bus supporting high-speed. Background Art

[0002] As SpaceWire bus technology matures, it has been widely used in spacecraft electronic systems. In addition, with the rapid development of the aerospace industry, the demand for SpaceWire bus in the communication of various functional modules of spacecraft continues to grow. At present, the SpaceWire bus used in spacecraft generally uses foreign SpaceWire transceivers, but there is still no domestically developed transceiver chip that meets the 200Mbps dedicated and stable requirements. Various research institutes generally use field programmable devices (FPGA) plus LVDS transceiver chips to realize SpaceWire communication functions, and some research institutes also use SOC chips to integrate SpaceWire bus functions.

[0003] However, no matter which technology route is used in the application of SpaceWire bus technology in spacecraft, there are more or less restrictions. The use of foreign SpaceWire chips is expensive, and due to risks such as supply period and embargo, it cannot be scaled up; the use of domestic SOC chips to integrate SpaceWire bus causes waste of resources, corresponding cost increase, and inflexible technology application; the use of FPGA to implement SpaceWire bus functions in China uses DS signal XOR clock as sampling clock, and the clock signal is very unstable; or the use of synchronous clock to directly sample DS signal is easily affected by signal jitter and skew, and cannot be effectively sampled at high speed; its performance generally cannot reach 200Mbps and higher bus speeds, and is basically applied at bus speeds of 50Mbps to 100Mbps.

[0004] Therefore, the present invention mainly aims at the disadvantage that the performance of SpaceWire bus implemented by using field programmable devices (FPGA) is not as good as that of using chips. The present invention achieves excellent performance of bus communication rate of 200Mbps~400Mbps by using three-level synchronous sampling of bus signals and DS decoding optimization algorithm.

[0005] In the prior art, the patent document "A SpaceWire bus node controller IP core for communication between satellite-borne devices" (CN117938574A) discloses a node controller IP core, which implements the composition of various modules of the node controller, including PHY module, data receiver module, composite module, receiving processing module, sending processing module, AMBA2.0 bus module, data transmitter module, link interface control module, and register configuration management module. However, it does not solve the high-rate downsampling error caused by the jitter and skew of the line signal in the DS decoding module, and cannot achieve high-rate sampling and DS encoding at low rates.

[0006] Patent document "A multi-channel spacewire bus monitoring method for transmission on a single time axis" (CN114625610A) discloses a SpaceWire bus detection method, which realizes the components of various modules of the bus detection system, including a dedicated signal simulation source, a spacewire monitoring device, a host computer and a PCIe module. However, it does not solve the high-rate downsampling error caused by the jitter and skew of the line signal in the receiving DS decoding module, and the deviation of DS decoding at low rate due to high-rate downsampling and low-rate DS decoding. Summary of the invention

[0007] In view of the defects in the prior art, the object of the present invention is to provide a method and system for optimizing DS decoding of a SpaceWire bus supporting high-speed.

[0008] A high-rate SpaceWire bus DS decoding optimization system provided by the present invention includes:

[0009] Synchronous sampling module, skew jitter error compensation module, asynchronous buffer module and DS decoding module.

[0010] The synchronous sampling module synchronizes the input DS signal to the system sampling clock through three signal latches and transmits it to the skew jitter error compensation module;

[0011] The skew jitter error compensation module performs data sampling compensation, and after judging the valid flag of the data, transmits it to the DS decoding module and the asynchronous buffer module;

[0012] The asynchronous cache module shifts the cache, converts the storage and marks the effective length of the data;

[0013] The DS decoding module decodes, performs serial shift operations, and outputs data words and control words.

[0014] Preferably, the synchronous sampling module uses the internal clock of the FPGA as the driving clock. According to the input DS signal, the first stage uses the rising edge of the clock to perform clock edge sampling and latching signals, which are recorded as a_d1 and a_s1;

[0015] The second stage uses the falling edge of the clock to latch the rising edge of the secondary signal, which is recorded as a_d2 and a_s2;

[0016] The third stage latches the latch signal again at the next clock falling edge, which is recorded as a_d0 and a_s0;

[0017] The latched DS signal is transmitted to the skew jitter error compensation module.

[0018] Preferably, the skew jitter error compensation module uses a high-frequency synchronous sampling clock to latch a_d0, a_s0, a_d1, and a_s1 in the DS signal again, and synchronizes the sampling of the falling edge to the rising edge, which are recorded as b_d0, b_s0, b_d1, and b_s1 respectively;

[0019] Determine the sampling error caused by DS signal jitter and skew, and perform sampling compensation;

[0020] The data is determined to be valid, and the generated data bits and data valid flag bits are passed to the DS decoding module.

[0021] Preferably, the sampling error judgment includes: obtaining the data error compensation point of b_d1 and b_s1, recorded as c_xor1;

[0022] If b_d0 XOR b_s0 XOR c_xor1 is 1, the b_d0 data is recorded as c_bit0. If b_d0 XOR b_s0 XOR c_xor1 is 0, the b_d1 data is recorded as c_bit0 and the b_d1 data is recorded as c_bit1.

[0023] The determining data validity includes: if b_d0 XOR b_s0 XOR c_xor1 is 1, or b_d0 XOR b_s0 XOR b_d1 XOR b_s1 is 1, then record c_val0 and determine c_bit0 data is valid; if b_d0 XOR b_s0 XOR c_xor1 is 1 and b_d0 XOR b_s0 XOR b_d1 XOR b_s1 is 1, then record c_val1 and determine c_bit1 is valid.

[0024] The data bits are c_bit0 and c_bit1.

[0025] The data valid flags are c_val0 and c_val1.

[0026] Preferably, the DS decoding module uses a low-frequency clock as a logic drive to decode the data in the cache, and after detecting that the data valid flag is 1, performs a serial shift operation on the parallel data within a later system clock period, and performs a DS decoding operation, and outputs data words and control words driven by the low-frequency clock.

[0027] The asynchronous cache module performs asynchronous communication between the high-frequency clock domain and the low-frequency clock domain, receives the data bits and data valid flag bits sent by the skew jitter error compensation module, performs shift cache, executes serial to parallel conversion storage, writes into the independent clock dual-port RAM, and marks the valid length of the data.

[0028] A high-speed SpaceWire bus DS decoding optimization method provided by the present invention includes:

[0029] Synchronous sampling steps: The input DS signal is latched three times and synchronized to the system sampling clock. The latched DS signal is transmitted to the skew jitter error compensation module.

[0030] The skew jitter error compensation step is to enable the skew jitter error compensation module to perform data sampling compensation, and after determining the data valid flag bit, transmit the data bit and the data valid bit to the DS decoding module and the asynchronous buffer module.

[0031] Asynchronous caching steps: instruct the asynchronous caching module to shift cache, convert storage and mark the effective length of data.

[0032] DS decoding steps: Instruct the DS decoding module to decode, perform serial shift operations, and output data words and control words.

[0033] Preferably, in the synchronous sampling step, the internal clock of the FPGA is used as the driving clock, and according to the input DS signal, the first stage uses the rising edge of the clock to perform clock edge sampling and latching signals, which are recorded as a_d1 and a_s1;

[0034] The second stage uses the falling edge of the clock to latch the rising edge of the secondary signal, which is recorded as a_d2 and a_s2;

[0035] The third stage latches the latch signal again at the next clock falling edge, which is recorded as a_d0 and a_s0;

[0036] The latched DS signal is transmitted to the skew jitter error compensation module.

[0037] Preferably, in the skew jitter error compensation step, a high-frequency synchronous sampling clock is used to latch a_d0, a_s0, a_d1, and a_s1 in the DS signal again, and the sampling of the falling edge is synchronized to the rising edge, which are recorded as b_d0, b_s0, b_d1, and b_s1 respectively;

[0038] Determine the sampling error caused by DS signal jitter and skew, and perform sampling compensation;

[0039] The data is determined to be valid, and the generated data bits and data valid flag bits are passed to the DS decoding module.

[0040] Preferably, the sampling error judgment includes: obtaining the data error compensation point of b_d1 and b_s1, recorded as c_xor1;

[0041] If b_d0 XOR b_s0 XOR c_xor1 is 1, the b_d0 data is recorded as c_bit0. If b_d0 XOR b_s0 XOR c_xor1 is 0, the b_d1 data is recorded as c_bit0 and the b_d1 data is recorded as c_bit1.

[0042] The determining data validity includes: if b_d0 XOR b_s0 XOR c_xor1 is 1, or b_d0 XOR b_s0 XOR b_d1 XOR b_s1 is 1, then record c_val0 and determine c_bit0 data is valid; if b_d0 XOR b_s0 XOR c_xor1 is 1 and b_d0 XOR b_s0 XOR b_d1 XOR b_s1 is 1, then record c_val1 and determine c_bit1 is valid.

[0043] The data bits are c_bit0 and c_bit1.

[0044] The data valid flags are c_val0 and c_val1.

[0045] Preferably, in the DS decoding step, a low-frequency clock is used as a logic drive to decode the data in the cache, and after detecting that the data valid flag is 1, a serial shift operation is performed on the parallel data within a later system clock period, and a DS decoding operation is performed to output data words and control words driven by the low-frequency clock.

[0046] In the asynchronous caching step, the high-frequency clock domain and the low-frequency clock domain are asynchronously communicated, the data bits and data valid flag bits sent by the skew jitter error compensation module are received, shift caching is performed, serial to parallel conversion storage is performed, written into the independent clock dual-port RAM, and the valid length of the data is marked.

[0047] Compared with the prior art, the present invention has the following beneficial effects:

[0048] 1. The bus of the present invention has a high rate and can realize the decoding function of the bus at 200Mbps~400Mbps by selecting different sampling clocks for different functional modules.

[0049] 2. The present invention realizes three-level synchronous sampling, and after three signal latches, synchronizes the input DS signal to the system sampling clock, thereby reducing the risk of signal competition.

[0050] 3. The present invention determines the sampling error caused by the jitter and skew of the DS signal, performs sampling compensation, and adopts an optimized DS decoding algorithm to solve the decoding error caused by the jitter and skew of the signal at the SpaceWire bus rate of 200Mbps and higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0052] Figure 1 Schematic diagram of the system architecture optimized to support high-speed SpaceWire bus DS decoding.

[0053] Figure 2 Schematic diagram of the application scenario of the DS decoding optimization system to support high-speed SpaceWire bus.

[0054] Figure 3 Schematic diagram of optimizing signal skew jitter to support high-rate SpaceWire bus DS decoding.

[0055] Figure 4 Schematic diagram of optimizing recovered clock error to support high-rate SpaceWire bus DS decoding.

[0056] Figure 5 Schematic diagram of general sampling error optimization to support high-rate SpaceWire bus DS decoding.

[0057] Figure 6 Schematic diagram of optimized compensation sampling to support high-rate SpaceWire bus DS decoding.

[0058] Figure 7 Schematic diagram of sampling timing optimization and compensation to support high-rate SpaceWire bus DS decoding. DETAILED DESCRIPTION

[0059] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0060] A DS decoding optimization system supporting high-rate SpaceWire bus provided by the present invention includes: a synchronous sampling module, a skew jitter error compensation module and an optimized DS decoding module.

[0061] The synchronous sampling module uses the internal clock of FPGA, that is, the clock frequency must be greater than or equal to the bus rate, as the driving clock of the entire module. It adopts three-level synchronous sampling: according to the input DS signal, the first level performs clock edge sampling (rising edge and falling edge) to latch the signal, the second level latches the secondary signal of the rising edge, and the third level latches the latched signal again. After three signal latches, the input DS signal is synchronized to the system sampling clock, eliminating the risk of logic competition caused by the input signal and avoiding pulse glitches caused by the sequence of signals.

[0062] Specifically, the rising edge of the clock is used to sample and latch the DS input signal, which is recorded as a_d1 and a_s1. The falling edge of the clock is used to latch the input DS signal once, which is recorded as a_d2 and a_s2. The latched signal is latched again at the next falling edge of the clock, which is recorded as a_d0 and a_s0. The three-latched DS signal is transmitted to the skew jitter error compensation module.

[0063] The skew jitter error compensation module is used to eliminate sampling data errors caused by the instability of the DS bus signal itself. A high-frequency synchronous sampling clock is used to judge the sampling errors caused by the jitter and skew of the DS signal, and sampling compensation is performed, which solves the sampling errors caused by the jitter and skew problems of the input signal at high bus speeds.

[0064] The inputs a_d0 and a_s0 and a_d1 and a_s1 of the synchronous sampling module are latched again to synchronize the sampling of the falling edge of the synchronous sampling module to the rising edge, which are recorded as b_d0 and b_s0 and b_d1 and b_s1 respectively.

[0065] Get the data error compensation point of b_d1 and b_s1, that is, when the values ​​of b_d1 and b_s1 are different (XOR), record them as c_xor1; when b_d0 XOR b_s0 XOR c_xor1 is 1, record b_d0 data as c_bit0, if it is 0, record b_d1 data as c_bit0, and record b_d1 data as c_bit1. So far, data sampling compensation caused by signal jitter and skew is completed.

[0066] After completing the sampling of the signal data bit, it is also necessary to judge the validity of the data. When b_d0 XOR b_s0 XOR c_xor1 is 1 or b_d0 XOR b_s0 XOR b_d1 XOR b_s1 (recorded as c_val0) is 1, the c_bit0 data is valid; when b_d0 XOR b_s0 XOR c_xor1 is 1 and b_d0 XOR b_s0 XOR b_d1 XOR b_s1 (recorded as c_val1) is 1, c_bit1 is valid. The generated data bits c_bit0 and c_bit1 and the data validity flag bits c_val0 and c_val1 are passed to the DS decoding module.

[0067] Conventional DS decoding generates a sampling clock CLK by performing XOR on the signal D and the signal S, and samples the D signal through the CLK. Correct decoding can only be performed if the D signal is valid at the CLK edge. If the valid D signal cannot be correctly determined, the decoded data will also be wrong. The present invention uses a high-frequency sampling clock for sampling and data validity determination. The correct valid data is determined to provide the DS decoding module with correct data collection, so that the signal can be synchronized to the sampling clock, avoiding sampling errors caused by timing instability caused by traditional recovery clock sampling.

[0068] In addition, an optimized DS decoding module is used to solve decoding errors caused by signal jitter and skew at SpaceWire bus rates of 200Mbps and higher.

[0069] Since the sampling clock uses a high-frequency clock, if the decoding clock also uses a high-frequency clock, it will cause timing pressure on the internal logic, sacrificing area for performance during compilation optimization, resulting in an increase in resource usage, which is not conducive to transplantation and expansion on FPGAs with small resources. Therefore, a low-frequency clock is used as the logic driver in the DS decoding module, and the clock frequency only needs to be greater than 1 / 4 of the bus rate.

[0070] The data bits and data valid bits sent by the skew jitter error compensation module are sent to the asynchronous cache module for shift caching, serial-to-parallel conversion storage, written into the independent clock dual-port RAM, and the valid length of the data is marked. The asynchronous cache module is an asynchronous bridge between the data valid latch module and the DS decoding module, that is, the high-frequency clock domain and the low-frequency clock domain communicate asynchronously. The output data has a customizable width, which is set to 4. When it is 4, the low-frequency clock is greater than 1 / 4 of the high-frequency sampling clock.

[0071] The other port of the dual-port RAM is connected to the DS decoding module to decode the data bits in the cache; when the data valid flag is 1, the valid data is decoded. When the DS decoding module detects the valid data, it will serialize the parallel data within a system clock period and perform DS decoding operations, and finally output data words, control words, etc. driven by a low-frequency clock.

[0072] The high bus rate of the present invention can realize the decoding function of the bus at 200Mbps~400Mbps (depending on the rate level of the FPGA), solves the problem that FPGA with limited resources can realize accurate DS decoding at a bus rate of more than 200Mbps, realizes a bus rate of more than 200Mbps on Xilinx Spartan 6 series FPGA, and realizes a bus rate of more than 400Mbps on Virtex series FPGA.

[0073] A high-speed SpaceWire bus DS decoding optimization method provided by the present invention includes:

[0074] Synchronous sampling steps: The input DS signal is latched three times and synchronized to the system sampling clock. The latched DS signal is transmitted to the skew jitter error compensation module.

[0075] The skew jitter error compensation step is to enable the skew jitter error compensation module to perform data sampling compensation, and after determining the data valid flag bit, transmit the data bit and the data valid bit to the DS decoding module and the asynchronous buffer module.

[0076] Asynchronous caching steps: instruct the asynchronous caching module to shift cache, convert storage and mark the effective length of data.

[0077] DS decoding steps: Instruct the DS decoding module to decode, perform serial shift operations, and output data words and control words.

[0078] In more preferred embodiments, the synchronous sampling step uses the internal clock of the FPGA as the driving clock, and according to the input DS signal, the first stage uses the rising edge of the clock to perform clock edge sampling and latching signals, which are recorded as a_d1 and a_s1;

[0079] The second stage uses the falling edge of the clock to latch the rising edge of the secondary signal, which is recorded as a_d2 and a_s2;

[0080] The third stage latches the latch signal again at the next clock falling edge, which is recorded as a_d0 and a_s0;

[0081] The latched DS signal is transmitted to the skew jitter error compensation module.

[0082] In more preferred embodiments, a high-frequency synchronous sampling clock is used in the skew jitter error compensation step to latch a_d0, a_s0, a_d1, and a_s1 in the DS signal again, and the sampling of the falling edge is synchronized to the rising edge, which are recorded as b_d0, b_s0, b_d1, and b_s1 respectively;

[0083] Determine the sampling error caused by DS signal jitter and skew, and perform sampling compensation;

[0084] The data is determined to be valid, and the generated data bits and data valid flag bits are passed to the DS decoding module.

[0085] In more preferred examples, the sampling error judgment includes: obtaining a data error compensation point of b_d1 and b_s1, recorded as c_xor1;

[0086] If b_d0 XOR b_s0 XOR c_xor1 is 1, the b_d0 data is recorded as c_bit0. If b_d0 XOR b_s0 XOR c_xor1 is 0, the b_d1 data is recorded as c_bit0 and the b_d1 data is recorded as c_bit1.

[0087] The determining data validity includes: if b_d0 XOR b_s0 XOR c_xor1 is 1, or b_d0 XOR b_s0 XOR b_d1 XOR b_s1 is 1, then record c_val0 and determine c_bit0 data is valid; if b_d0 XOR b_s0 XOR c_xor1 is 1 and b_d0 XOR b_s0 XOR b_d1 XOR b_s1 is 1, then record c_val1 and determine c_bit1 is valid.

[0088] The data bits are c_bit0 and c_bit1.

[0089] The data valid flags are c_val0 and c_val1.

[0090] In more preferred examples, a low-frequency clock is used as a logic drive in the DS decoding step to decode the data in the cache, and after detecting that the data valid flag is 1, a serial shift operation is performed on the parallel data within a later system clock period, and a DS decoding operation is performed to output data words and control words driven by the low-frequency clock.

[0091] In the asynchronous caching step, the high-frequency clock domain and the low-frequency clock domain are asynchronously communicated, the data bits and data valid flag bits sent by the skew jitter error compensation module are received, shift caching is performed, serial to parallel conversion storage is performed, written into the independent clock dual-port RAM, and the valid length of the data is marked.

[0092] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A high-speed SpaceWire bus DS decoding optimization system, characterized in that: include: Synchronous sampling module, skew jitter error compensation module, asynchronous buffer module and DS decoding module; The synchronous sampling module synchronizes the input DS signal to the system sampling clock after three signal latches, and transmits it to the skew jitter error compensation module; The synchronous sampling module uses the internal clock of the FPGA as the driving clock. According to the input DS signal, the first stage uses the rising edge of the clock to perform clock edge sampling and latching signals, which are recorded as a_d1 and a_s1; The second stage uses the falling edge of the clock to latch the rising edge signal, recorded as a_d2 and a_s2; The third stage latches the latch signal again at the next clock falling edge, which is recorded as a_d0 and a_s0; The latched DS signals a_d0, a_s0, a_d1, a_s1, a_d2 and a_s2 are transmitted to the skew jitter error compensation module; The skew jitter error compensation module performs data sampling compensation, and after judging the valid flag of the data, transmits it to the DS decoding module and the asynchronous buffer module; The skew jitter error compensation module uses a high-frequency synchronous sampling clock to latch a_d0, a_s0, a_d1, and a_s1 in the latched DS signal again, and synchronizes the sampling of the falling edge to the rising edge, which are recorded as b_d0, b_s0, b_d1, and b_s1 respectively; Determine the sampling error caused by DS signal jitter and skew, and perform sampling compensation; Determine the data is valid, and pass the generated data bits and data valid flag bits to the DS decoding module; The asynchronous cache module shifts the cache, converts the storage and marks the effective length of the data; The DS decoding module decodes, performs serial shift operations, and outputs data words and control words.

2. The high-rate SpaceWire bus DS decoding optimization system according to claim 1, characterized in that: The sampling error judgment includes: obtaining the data error compensation point of b_d1 and b_s1, recorded as c_xor1; If b_d0 XOR b_s0 XOR c_xor1 is 1, then b_d0 data is recorded as c_bit0; if b_d0 XOR b_s0 XOR c_xor1 is 0, then b_d1 data is recorded as c_bit0 and b_d1 data is recorded as c_bit1; The determining data validity comprises: if b_d0 XOR b_s0 XOR c_xor1 is 1, or b_d0 XOR b_s0 XOR b_d1 XOR b_s1 is 1, then c_val0 is recorded, and c_bit0 data is determined to be valid; if b_d0 XOR b_s0 XOR c_xor1 is 1 and b_d0 XOR b_s0 XOR b_d1 XOR b_s1 is 1, then c_val1 is recorded, and c_bit1 is determined to be valid; The data bits are c_bit0 and c_bit1; The data valid flags are c_val0 and c_val1.

3. The high-speed SpaceWire bus DS decoding optimization system according to claim 1, characterized in that: The DS decoding module uses a low-frequency clock as a logic drive to decode the data in the cache, and after detecting that the data valid flag is 1, performs a serial shift operation on the parallel data within a system clock period, and performs a DS decoding operation, and outputs a data word and a control word driven by the low-frequency clock; The asynchronous cache module performs asynchronous communication between the high-frequency clock domain and the low-frequency clock domain, receives the data bits and data valid flag bits sent by the skew jitter error compensation module, performs shift cache, executes serial to parallel conversion storage, writes into the independent clock dual-port RAM, and marks the valid length of the data.

4. A method for optimizing DS decoding for high-speed SpaceWire bus, characterized in that: include: Synchronous sampling step: the input DS signal is latched three times and synchronized to the system sampling clock. The latched DS signal is transmitted to the skew jitter error compensation module; In the synchronous sampling step, the internal clock of the FPGA is used as the driving clock. According to the input DS signal, the first stage uses the rising edge of the clock to perform clock edge sampling and latching signals, which are recorded as a_d1 and a_s1; The second stage uses the falling edge of the clock to latch the rising edge signal, recorded as a_d2 and a_s2; The third stage latches the latch signal again at the next clock falling edge, which is recorded as a_d0 and a_s0; The latched DS signals a_d0, a_s0, a_d1, a_s1, a_d2 and a_s2 are transmitted to the skew jitter error compensation module; The skew jitter error compensation step: the skew jitter error compensation module is made to perform data sampling compensation, and after determining the data valid flag bit, the data bit and the data valid bit are transmitted to the DS decoding module and the asynchronous buffer module; In the skew jitter error compensation step, a high-frequency synchronous sampling clock is used to latch a_d0, a_s0, a_d1, and a_s1 in the latched DS signal again, and the sampling of the falling edge is synchronized to the rising edge, which are recorded as b_d0, b_s0, b_d1, and b_s1 respectively; Determine the sampling error caused by DS signal jitter and skew, and perform sampling compensation; Determine the data is valid, and pass the generated data bits and data valid flag bits to the DS decoding module; Asynchronous caching step: the asynchronous caching module is instructed to perform shift caching, convert storage and mark the effective length of data; DS decoding steps: Instruct the DS decoding module to decode, perform serial shift operations, and output data words and control words.

5. The method for optimizing DS decoding for supporting high-speed SpaceWire bus according to claim 4, characterized in that: The sampling error judgment includes: obtaining the data error compensation point of b_d1 and b_s1, recorded as c_xor1; If b_d0 XOR b_s0 XOR c_xor1 is 1, then b_d0 data is recorded as c_bit0; if b_d0 XOR b_s0 XOR c_xor1 is 0, then b_d1 data is recorded as c_bit0 and b_d1 data is recorded as c_bit1; The determining data validity comprises: if b_d0 XOR b_s0 XOR c_xor1 is 1, or b_d0 XOR b_s0 XOR b_d1 XOR b_s1 is 1, then c_val0 is recorded, and c_bit0 data is determined to be valid; if b_d0 XOR b_s0 XOR c_xor1 is 1 and b_d0 XOR b_s0 XOR b_d1 XOR b_s1 is 1, then c_val1 is recorded, and c_bit1 is determined to be valid; The data bits are c_bit0 and c_bit1; The data valid flags are c_val0 and c_val1.

6. The method for optimizing DS decoding for supporting high-speed SpaceWire bus according to claim 4, characterized in that: In the DS decoding step, a low-frequency clock is used as a logic driver to decode the data in the cache, and after detecting that the data valid flag is 1, a serial shift operation is performed on the parallel data within a later period of a system clock, and a DS decoding operation is performed to output a data word and a control word driven by the low-frequency clock; In the asynchronous caching step, the high-frequency clock domain and the low-frequency clock domain are asynchronously communicated, the data bits and data valid flag bits sent by the skew jitter error compensation module are received, shift caching is performed, serial to parallel conversion storage is performed, written into the independent clock dual-port RAM, and the valid length of the data is marked.

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