Data acquisition method, device, equipment, storage medium and program product

Abstract

The present application relates to a data acquisition method, device, equipment, storage medium and program product. The method comprises: obtaining a first memory access request output by a C model corresponding to a chip in the process of processing a first verification request; according to the first memory access request, obtaining target data corresponding to the first memory access request from a data pool; wherein the target data is generated according to a second memory access request output by an RTL model corresponding to the chip in processing the first verification request; the first memory access request and the second memory access request are both used to request the acquisition of the target data; the target data is returned to the C model so that the C model can respond to the first verification request according to the target data. The use of this method can conveniently ensure that the RTL model and the C model obtain the same data during the joint simulation verification process to ensure accurate verification results.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a data acquisition method, device, equipment, storage medium and program product. Background Art

[0002] During chip functional simulation verification, there are situations where RTL (Register Transfer Level) models and C models are constructed for joint simulation verification. RTL models and C models are two abstract models described in different languages, which are used to describe and implement system functions. RTL models are closer to hardware implementation, while C models focus on functional implementation and do not involve specific hardware details. Due to the different focuses of building each model, the results obtained when accessing memory data during the joint simulation verification process of the RTL model and the C model are inconsistent.

[0003] In the related art, it is necessary to modify the implementation method of the C model, that is, the C model completely simulates the internal implementation of the RTL model to make it consistent with the implementation method of the RTL model. However, this process requires continuous iterative adjustments, which is labor-intensive and time-consuming. Summary of the invention

[0004] Based on this, it is necessary to provide a data acquisition method, device, equipment, storage medium and program product that can conveniently ensure that the RTL model and the C model obtain the same data during the joint simulation verification process to ensure accurate verification results in response to the above technical problems.

[0005] In a first aspect, the present application provides a data acquisition method. The method comprises:

[0006] Obtaining a first memory access request output by a C model corresponding to the chip during a process of processing a first verification request;

[0007] According to the first memory access request, target data corresponding to the first memory access request is obtained from the data pool; wherein the target data is generated according to the second memory access request output by the RTL model corresponding to the chip when processing the first verification request; the first memory access request and the second memory access request are both used to request to obtain the target data;

[0008] The target data is returned to the C model so that the C model responds to the first verification request according to the target data.

[0009] In one of the embodiments, the method further includes: obtaining a second memory access request output by the RTL model when processing the first verification request; determining whether the target data exists in the data pool based on the second memory access request; and if the target data exists in the data pool, returning the target data to the RTL model.

[0010] In one of the embodiments, a data pool includes a correspondence between multiple groups of cache data and memory access addresses; according to a first memory access request, target data corresponding to the first memory access request is obtained from the data pool, including: according to the first memory access request, determining the target address included in the first memory access request; determining from the data pool cache data corresponding to the memory access address identical to the target address as the target data; according to the second memory access request, determining whether the target data exists in the data pool, including: according to the second memory access request, determining the target address included in the second memory access request; determining whether there is cache data corresponding to the memory access address identical to the target address in the data pool, and if so, determining that the target data exists.

[0011] In one of the embodiments, the method further includes: when the target data does not exist in the data pool, generating the target data based on a preset generation function; returning the generated target data to the RTL model and storing the generated target data and the target address included in the second memory access request in the data pool in correspondence.

[0012] In one of the embodiments, determining cache data corresponding to the memory access address identical to the target address from the data pool as the target data includes: determining whether cache data corresponding to the memory access address identical to the target address exists in the data pool; if not, repeatedly querying whether cache data corresponding to the memory access address identical to the target address exists in the data pool, until cache data corresponding to the memory access address identical to the target address is obtained as the target data.

[0013] In one of the embodiments, the method further includes: if the target data is not obtained within the first waiting cycle, stopping the step of repeatedly querying whether there is cache data corresponding to the memory access address that is the same as the target address in the data pool, and returning an error message to the C model, wherein the error message is used to indicate that the target data has not been obtained.

[0014] In one of the embodiments, obtaining a first memory access request output by a C model corresponding to the chip during processing of a first verification request includes: obtaining the first memory access request output by the C model when the target data is not obtained from a first cache area in the C model during processing of the first verification request; obtaining a second memory access request output by the RTL model during processing of the first verification request includes: obtaining the second memory access request output by the RTL model when the target data is not obtained from a second cache area in the RTL model during processing of the first verification request.

[0015] In a second aspect, the present application also provides a data acquisition device. The device comprises:

[0016] A request acquisition module, used for acquiring a first memory access request output by a C model corresponding to the chip during processing of a first verification request;

[0017] A data acquisition module, configured to acquire target data corresponding to the first memory access request from a data pool according to the first memory access request; wherein the target data is generated according to a second memory access request output by an RTL model corresponding to the chip when processing the first verification request; and both the first memory access request and the second memory access request are used to request to acquire the target data;

[0018] The response module is used to return the target data to the C model so that the C model responds to the first verification request according to the target data.

[0019] In one of the embodiments, the device further includes a data returning module, configured to:

[0020] Obtaining a second memory access request output by the RTL model when processing the first verification request;

[0021] Determining, according to the second memory access request, whether the target data exists in the data pool;

[0022] In the case where the target data exists in the data pool, the target data is returned to the RTL model.

[0023] In one embodiment, the data pool includes a correspondence between multiple groups of cache data and memory access addresses; the data acquisition module is specifically used to: determine the target address included in the first memory access request according to the first memory access request; determine the cache data corresponding to the memory access address that is the same as the target address from the data pool as the target data;

[0024] The data return module is specifically used to: determine the target address included in the second memory access request according to the second memory access request; determine whether there is cache data corresponding to the memory access address same as the target address in the data pool, and if so, determine that the target data exists.

[0025] In one of the embodiments, the device also includes a data generation module, which is used to: generate the target data based on a preset generation function when the target data does not exist in the data pool; return the generated target data to the RTL model and store the generated target data and the target address included in the second memory access request in the data pool correspondingly.

[0026] In one of the embodiments, the data acquisition module is specifically used to: determine whether there is cache data corresponding to the memory access address that is the same as the target address in the data pool; if not, repeatedly query whether there is cache data corresponding to the memory access address that is the same as the target address in the data pool, until the cache data corresponding to the memory access address that is the same as the target address is obtained as the target data.

[0027] In one of the embodiments, the device also includes a query module, which is used to: if the target data is not obtained within the first waiting cycle, stop the step of repeatedly querying whether there is cache data corresponding to the memory access address that is the same as the target address in the data pool, and return an error message to the C model, wherein the error message is used to indicate that the target data has not been obtained.

[0028] In one embodiment, the request acquisition module is specifically used to: acquire the first memory access request output by the C model when the target data is not acquired from the first buffer area in the C model during the process of processing the first verification request;

[0029] The request acquisition module is further specifically used to: acquire the second memory access request output by the RTL model when the target data is not acquired from the second buffer area in the RTL model during the process of processing the first verification request.

[0030] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the methods described in the first aspect when executing the computer program.

[0031] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any one of the methods described in the first aspect above.

[0032] In a fifth aspect, the present application further provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps of any one of the methods described in the first aspect are implemented.

[0033] The above-mentioned data acquisition method, device, equipment, storage medium and program product can obtain the first memory access request output by the C model corresponding to the chip in the process of processing the first verification request; according to the first memory access request, obtain the target data corresponding to the first memory access request from the data pool; return the target data to the C model, so that the C model can respond to the first verification request according to the target data. Wherein, the target data is generated according to the second memory access request output by the RTL model corresponding to the chip when processing the first verification request; the first memory access request and the second memory access request are both used to request to obtain the target data; in this way, it can be ensured that the C model and the RTL model determine accurate verification results based on the same target data for the same first verification request. Since there is no need to modify the C model and the RTL model, it is only necessary to deploy the data pool during the verification process, so it is convenient to ensure that the RTL model and the C model obtain the same data during the joint simulation verification process to ensure accurate verification results. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 A schematic diagram of a flow chart of a data acquisition method in an embodiment;

[0036] Figure 2 A schematic diagram of a process of returning target data to an RTL model in one embodiment;

[0037] Figure 3 A schematic diagram of a process for obtaining target data in one embodiment;

[0038] Figure 4 A schematic diagram of another process of acquiring target data in one embodiment;

[0039] Figure 5 A schematic diagram of a process of returning target data to a C model in one embodiment;

[0040] Figure 6 A schematic diagram of another process of acquiring target data in one embodiment;

[0041] Figure 7 A schematic diagram of a verification environment in one embodiment;

[0042] Figure 8 is a structural block diagram of a data acquisition device in one embodiment;

[0043] Fig. 9 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0044] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. It should be understood that many specific details are set forth in the following description to facilitate a full understanding of the present application, but the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0046] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.

[0047] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0048] Chip functional simulation verification is applied to joint simulation with cache modules. Among them, cache is widely present in various memory access modules, which contain the most recent access data, and use spatial locality and temporal locality to reduce unnecessary external memory access. For example, during chip functional simulation verification, RTL model and C model are currently constructed for joint simulation verification. Both RTL model and C model contain cache modules, which are used to store the data accessed by the model in the recent period of time in the cache module. As time goes by, the data stored in the cache module will be continuously updated based on the replacement strategy of the model.

[0049] Among them, the RTL model and the C model are two abstract models described in different languages, which are used to describe and implement the functions of the system. The RTL model usually contains a pipeline structure, which is closer to hardware implementation. While implementing the function, it is necessary to balance the area, power consumption and time consumption; while the C model focuses on functional implementation, does not involve specific hardware details, and does not need to consider area, power consumption, etc. This difference leads to different performances in cache behavior, especially in cache line replacement and hit / miss.

[0050] Specifically, the pipeline design in the RTL model is to improve processing speed and throughput. By breaking down complex operations into multiple stages and using registers between each stage to store intermediate results, parallel processing can be achieved, thereby improving system performance. The C model is usually used for algorithm development and verification, and it does not contain any hardware-specific implementation details such as pipeline structure. Therefore, the C model is mainly used to verify the functional correctness of the system, not the performance.

[0051] Since the C model does not consider the details of the hardware implementation, it does not simulate the pipeline behavior in the RTL model. This means that in terms of cache behavior, the C model may not accurately predict the performance of the RTL model on the actual hardware, and its cache behavior may be different from the RTL model. In other words, the RTL model uses a pipeline design to replace and update the data stored in the cache module, while the C model replaces and updates the data in the cache module based on other strategies.

[0052] Based on this, we can know that at the same time, the data stored in the cache modules in the C model and the RTL model may be different. Therefore, for the same verification request, when obtaining the same data, it is possible that the RTL model can obtain the data from its own cache module, while the C model cannot obtain the data from its own cache module, that is, the RTL model hits but the C model misses; or the C model hits but the RTL model misses. In this case, data needs to be obtained from the outside.

[0053] In related technologies, in order to make the data obtained by the two models consistent, the approach is to make the implementation of the C model and the RTL model completely consistent, that is, the C model completely simulates the internal implementation of the RTL model, and even the C model needs to obtain the internal state of the RTL by calling DPI (Direct Programming Interface) to achieve the purpose of completely consistent output of the C model and the RTL model every time. However, this is very time-consuming, the workload is too large, and it takes a long time and is not convenient.

[0054] In view of this, an embodiment of the present application provides a data acquisition method, which can conveniently ensure the consistency of data acquired by the RTL model and the C model.

[0055] It should be noted that the data acquisition method provided in the embodiments of the present application may be executed by a data acquisition device, which may be implemented as part or all of a computer device through software, hardware, or a combination of software and hardware. The computer device may be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, or servers, and the server may be implemented as an independent server or a server cluster composed of multiple servers. In the following method embodiments, the execution subject is described as a computer device.

[0056] In one embodiment, Figure 1 As shown, a data acquisition method is provided, comprising the following steps:

[0057] Step 101: Obtain a first memory access request output by a C model corresponding to the chip during a process of processing a first verification request.

[0058] Among them, the C model and RTL model of the chip can be constructed according to the functional description document of the chip. The C model is written in a first programming language, such as C or C++. The RTL model is written in a second programming language, such as VHDL or Verilog.

[0059] The functions of the C model and the RTL model are the same, and both describe the functions of the chip.

[0060] In the process of chip function verification, the main verification object can be considered as the RTL model, and the correctness of the function implementation of the RTL model is verified. In this process, the processing results of the C model are taken as the basis, and the processing results of the RTL model are compared with the processing results of the C model to verify whether the functions implemented by the RTL model are correct, and then whether the functional design of the chip is correct can be determined. Therefore, the C model and the RTL model are used for joint simulation verification in the verification process.

[0061] During the verification process, the RTL model and the C model receive the same stimulus and are expected to have the same output. For example, the RTL model and the C model receive the same verification request and process the same verification request. It is expected that the processing results of the same verification request are consistent, for example, the data corresponding to the verification request is consistent.

[0062] Optionally, a verification environment (Testbench) is deployed in the computer device, and the RTL model and the C model are jointly functionally simulated in the verification environment. Also, the data pool mentioned later can also be deployed in the verification environment. It is understandable that the verification environment and each model can be implemented by a software algorithm.

[0063] The C model can output a first memory access request during processing of the first verification request. The first memory access request is used to request to obtain target data. The C model includes a cache module, namely, a first cache area.

[0064] In an optional implementation, obtaining the first memory access request output by the C model corresponding to the chip in the process of processing the first verification request includes: obtaining the first memory access request output by the C model when the target data is not obtained from the first cache area in the C model in the process of processing the first verification request. In other words, the C model can first query whether the target data to be obtained exists in the cache module according to the first verification request. If so, the target data is directly obtained from the cache module to process the first verification request; if not, the first memory access request can be output.

[0065] Alternatively, in another optional implementation, the C model may directly generate a first memory access request according to the first verification request and output the first memory access request. Here, the first verification request may include a target address corresponding to the target data, where the target address is a memory access address indicating the acquisition of the target data; usually, the target data is cached corresponding to the target address. Correspondingly, the first memory access request may include the target address.

[0066] The RTL model can output a second memory access request during processing of the first verification request. The second memory access request is used to request to obtain target data. The RTL model includes a cache module, namely, a second cache area.

[0067] In an optional implementation, the process of obtaining the second memory access request output by the RTL model in the process of processing the first verification request includes: obtaining the second memory access request output by the RTL model when the target data is not obtained from the second cache area in the RTL model in the process of processing the first verification request. In other words, the RTL model can first query whether the target data to be obtained exists in the cache module according to the first verification request, and if so, directly obtain the target data from the cache module to process the first verification request; if not, the second memory access request can be output.

[0068] Alternatively, in another optional implementation, the RTL model may directly generate a second memory access request according to the first verification request and output the second memory access request. Correspondingly, the second memory access request may include the target address.

[0069] Optionally, the C model and the RTL model may receive the first verification request at the same time, or may not receive the first verification request at the same time.

[0070] Step 102: According to the first memory access request, obtain target data corresponding to the first memory access request from a data pool.

[0071] The target data is generated according to the second memory access request output by the RTL model corresponding to the chip when processing the first verification request.

[0072] Exemplarily, the second memory access request is first output from the RTL model, and in the verification environment, the target data can be generated according to the second memory access request and stored in the data pool. When the first memory access request is output from the C model, the target data can be directly obtained from the data pool according to the first memory access request.

[0073] Alternatively, if the first memory access request is output from the C model first, if the target data has not been generated according to the second memory access request, a waiting action may be performed first until the target data is generated according to the second memory access request.

[0074] It can be understood that the second buffer area in the RTL model stores the data acquired by the RTL model in the most recent period of time. For a certain data that has not been read before, it is only generated outside the RTL model, stored in the data pool, returned to the RTL model, and then may be stored in the second buffer area. Therefore, the data pool can gradually store all the data that needs to be acquired during the RTL model verification process. Correspondingly, the C model can acquire these data in the data pool, and the data acquired by the two can be consistent.

[0075] The embodiment of the present application does not specifically limit the type and content of the target data.

[0076] Step 103, returning the target data to the C model, so that the C model can respond to the first verification request according to the target data.

[0077] The C model may process the first verification request according to the target data, or respond to the first verification request using the target data as a verification result.

[0078] It is understandable that after acquiring the target data, the C model can determine whether to store the target data in the first cache area according to the cache replacement strategy of the C model.

[0079] The above data acquisition method can obtain the first memory access request output by the C model corresponding to the chip in the process of processing the first verification request; according to the first memory access request, obtain the target data corresponding to the first memory access request from the data pool; return the target data to the C model, so that the C model can respond to the first verification request according to the target data. Wherein, the target data is generated according to the second memory access request output by the RTL model corresponding to the chip when processing the first verification request; the first memory access request and the second memory access request are both used to request to obtain the target data; in this way, it can be ensured that the C model and the RTL model determine accurate verification results based on the same target data for the same first verification request. Since there is no need to modify the C model and the RTL model, it is only necessary to deploy the data pool during the verification process, so it is convenient to ensure that the RTL model and the C model obtain the same data during the joint simulation verification process to ensure accurate verification results.

[0080] In one embodiment, a first proxy module is deployed in the verification environment, which is used to receive a first memory access request, obtain target data according to the first memory access request, and return the target data to the C model. A second proxy module is also deployed in the verification environment, which is used to receive a second memory access request, obtain target data according to the second memory access request, and return the target data to the RTL model.

[0081] Exemplarily, the second agent module may be a BFM (Bus Function Model) component in a testbench verification environment, responsible for processing memory access requests from the RTL.

[0082] As mentioned above, the C model is the first programming language and cannot directly interact with the second programming language (such as Verilog) of the RTL model, and needs to be implemented through DPI. The first proxy module contains all DPIs, so the second proxy module can be used to implement the interaction between the C model and the verification environment and obtain the target data.

[0083] In an embodiment of the present application, the first proxy module and the second proxy module are used to process the memory access requests of the C model and the RTL model respectively, so as to achieve the docking of the two models and ensure that the requests of the two models are accurately responded to to avoid conflicts, thereby ensuring the accuracy of the verification results.

[0084] The process of obtaining target data is described below.

[0085] In one embodiment, Figure 2 A schematic diagram of a process of returning target data to an RTL model is shown. The method also includes:

[0086] Step 201: Obtain a second memory access request output by the RTL model when processing a first verification request.

[0087] Step 202: Determine whether target data exists in the data pool according to the second memory access request.

[0088] The second memory access request includes memory access information corresponding to the target data, and in the data pool, the memory access information is stored in association with the target data.

[0089] Therefore, the memory access information in the second memory access request can be determined, and the data pool can be queried based on the memory access information to obtain the target data.

[0090] Exemplarily, the memory access information is the memory access address of the target data, and the first verification request may include the memory access address. Figure 3 The schematic diagram of a process of obtaining target data is exemplified. According to the second memory access request, determining whether the target data exists in the data pool includes:

[0091] Step 301: Determine, according to a second memory access request, a target address included in the second memory access request.

[0092] That is, the access address of the target data is used as the target address.

[0093] Step 302, determining whether there is cache data corresponding to the same memory access address as the target address in the data pool, and if so, determining that the target data exists.

[0094] In other words, the data pool includes a correspondence between multiple sets of cache data and access addresses. The target address can be compared with all access addresses in the data pool and the target address. When the access address that is the same as the target address is determined, the cache data corresponding to the access address is associated with the target address as the target data.

[0095] Step 203: if the target data exists in the data pool, the target data is returned to the RTL model.

[0096] In addition, if Figure 4 Another schematic diagram of a process for obtaining target data is shown, the method further comprising:

[0097] Step 401: if target data does not exist in the data pool, generate target data based on a preset generation function.

[0098] Step 402: Return the generated target data to the RTL model and store the generated target data and the target address included in the second memory access request in a data pool in correspondence thereto.

[0099] In other words, if the target data does not exist in the data pool, which means that the target data has not been accessed and obtained before, the target data can be generated and stored in the data pool.

[0100] Optionally, taking the RTL model using Verilog language as an example, SystemVerilog has various random functions inside, so the preset generation function can be a random function, such as the urandom_range function, which is used to generate unsigned random integers within a specified range.

[0101] It should be noted that the reason for returning random numbers is to simulate the actual working conditions of the chip. In practice, the data returned by memory access can be considered random.

[0102] Based on this, it can be understood that if the target data has been stored in the data pool, it means that the RTL model has accessed and obtained the target data during the historical verification process, so the data is generated and stored. If it is not stored in the data pool, the target data can be generated.

[0103] Optionally, the data pool can be empty upon initialization.

[0104] Optionally, the data pool can be implemented using an associative array in SystemVerilog, so that data can be indexed by accessing the memory address.

[0105] In the embodiment of the present application, the target data can be quickly and accurately obtained from the data pool based on the target address, ensuring that the target data is obtained accurately. In addition, the target data is stored in the data pool after the initial generation, so that when the address in the second memory access request output by the subsequent RTL is still the target address, there is no need to generate the target data again, but the target data can be directly obtained from the data pool, thereby improving the efficiency of obtaining the target data in the entire verification process.

[0106] In one embodiment, Figure 5 A schematic diagram of a process of returning target data to a C model is shown. According to a first memory access request, the target data corresponding to the first memory access request is obtained from a data pool, including:

[0107] Step 501: According to a first memory access request, determine a target address included in the first memory access request.

[0108] Step 502: determine cache data corresponding to the memory access address identical to the target address from the data pool as the target data.

[0109] Optionally, the first proxy module calls the exist function to query whether there is a memory access address identical to the target address in the data pool.

[0110] In the embodiment of the present application, since the data in the data pool is generated based on the second memory access request of the RTL, it ensures that the target data obtained by the RTL model and the C model during the processing of the same first verification request are consistent, thereby ensuring the accuracy of the verification result.

[0111] In one embodiment, Figure 6 Another schematic diagram of the process of obtaining target data is shown. Determining cache data corresponding to the access address identical to the target address from the data pool as the target data includes:

[0112] Step 601, determining whether there is cache data corresponding to the same memory access address as the target address in the data pool.

[0113] It is understandable that if the first memory access request is output first and the second memory access request is output later, at this time, after the first proxy module obtains the first memory access request, it will find that the target data cannot be queried in the data pool. Therefore, there will be a situation where there is no cache data corresponding to the memory access address that is the same as the target address in the data pool.

[0114] Step 602: If not, repeatedly query whether there is cache data corresponding to the same access address as the target address in the data pool, until the cache data corresponding to the same access address as the target address is obtained as the target data.

[0115] Optionally, a repeated query may be performed within the first waiting period to determine whether there is cache data corresponding to the same access address as the target address in the data pool. Optionally, the frequency of the repeated query may be preset.

[0116] In an embodiment of the present application, it is possible to repeatedly query whether the target data exists in the data pool, rather than directly returning empty information to the C model after a single query, thereby avoiding the C model from repeatedly outputting the first memory access request and saving computing resources.

[0117] In one embodiment, the method further includes: if the target data is not obtained within the first waiting cycle, stopping the step of repeatedly querying whether there is cache data corresponding to the memory access address that is the same as the target address in the data pool, and returning an error message to the C model, wherein the error message is used to indicate that the target data is not obtained.

[0118] In this way, by setting the first waiting period, a long waiting time is avoided, thereby delaying the response of the C model to the first verification request. Moreover, it can be understood that if the target data is not obtained within the first waiting period, it means that there is a problem in the verification process of the RTL model, and the returned error information can indicate that there is an error in the verification process for the first verification request, which helps to improve the verification result.

[0119] For ease of understanding, the joint simulation method provided by the present application is described below with a complete embodiment. Figure 7 In the verification environment shown.

[0120] During chip functional simulation verification, RTL model and C model are constructed, and joint functional simulation of RTL model and C model is performed in the verification environment. The verification environment includes the proxy model and BFM model of the C model and the data pool.

[0121] When the RTL model and the C model process the same target request, they can both query the data corresponding to the memory access address from their own cache modules based on the memory access address corresponding to the target request. If the required data does not exist in the cache module, a memory access request is issued to the outside.

[0122] Specifically, for the RTL model, the BMF model obtains the memory access request issued by the RTL model to the outside, and the memory access request includes the memory access address. The BFM queries the received memory access address in the data pool. If the memory access address exists, the target data corresponding to the memory access address in the data pool is returned to the RTL model. If the memory access address does not exist, a preset generation function such as a random function is called to generate random data, and the random data is returned to the RTL model as the target data, and the generated random data is stored in the data pool. Based on this, multiple sets of memory access addresses and random data are stored in the data pool in a one-to-one correspondence.

[0123] For the C model, the proxy model obtains the memory access request sent by the C model to the outside, and calls the exist function according to the memory access address contained in the memory access request to query whether the target data corresponding to the memory access address exists in the data pool. If it exists, the target data is returned to the C model. If not, it waits for the target data to appear. If the waiting time exceeds a certain time, an error message is returned to the C model.

[0124] This method does not need to spend time aligning the implementation details of the C model and the RTL model, and can conveniently complete the joint simulation of chip models with different implementation methods.

[0125] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0126] Based on the same inventive concept, the embodiment of the present application also provides a data acquisition device for implementing the data acquisition method involved above. The implementation solution provided by the device to solve the problem is similar to the implementation solution recorded in the above method, so the specific limitations in one or more data acquisition device embodiments provided below can refer to the limitations on the data acquisition method above, and will not be repeated here.

[0127] In one embodiment, Figure 8 As shown, a data acquisition device is provided, and the data acquisition device 800 includes: a request acquisition module 801, a data acquisition module 802 and a response module 803, wherein:

[0128] A request acquisition module 801 is used to acquire a first memory access request output by a C model corresponding to the chip during processing of a first verification request;

[0129] The data acquisition module 802 is used to acquire target data corresponding to the first memory access request from the data pool according to the first memory access request; wherein the target data is generated according to the second memory access request output by the RTL model corresponding to the chip when processing the first verification request; the first memory access request and the second memory access request are both used to request to acquire the target data;

[0130] The response module 803 is used to return the target data to the C model so that the C model can respond to the first verification request according to the target data.

[0131] In one embodiment, the device further includes a data returning module, configured to:

[0132] Obtaining a second memory access request output by the RTL model when processing the first verification request;

[0133] Determining, according to the second memory access request, whether the target data exists in the data pool;

[0134] In the case where the target data exists in the data pool, the target data is returned to the RTL model.

[0135] In one embodiment, the data pool includes a correspondence between multiple groups of cache data and memory access addresses; the data acquisition module 802 is specifically used to: determine the target address included in the first memory access request according to the first memory access request; determine the cache data corresponding to the memory access address that is the same as the target address from the data pool as the target data;

[0136] The data return module is specifically used to: determine the target address included in the second memory access request according to the second memory access request; determine whether there is cache data corresponding to the memory access address same as the target address in the data pool, and if so, determine that the target data exists.

[0137] In one embodiment, the device also includes a data generation module, which is used to: generate the target data based on a preset generation function when the target data does not exist in the data pool; return the generated target data to the RTL model and store the generated target data and the target address included in the second memory access request in the data pool accordingly.

[0138] In one embodiment, the data acquisition module 802 is specifically used to: determine whether there is cache data corresponding to the memory access address that is the same as the target address in the data pool; if not, repeatedly query whether there is cache data corresponding to the memory access address that is the same as the target address in the data pool, until the cache data corresponding to the memory access address that is the same as the target address is obtained as the target data.

[0139] In one embodiment, the device also includes a query module, which is used to: if the target data is not obtained within the first waiting cycle, stop the step of repeatedly querying whether there is cache data corresponding to the memory access address that is the same as the target address in the data pool, and return an error message to the C model, wherein the error message is used to indicate that the target data has not been obtained.

[0140] In one embodiment, the request acquisition module 801 is specifically used to: acquire the first memory access request output by the C model when the target data is not acquired from the first buffer area in the C model during the process of processing the first verification request;

[0141] The request acquisition module 801 is further specifically used to: acquire the second memory access request output by the RTL model when the target data is not acquired from the second buffer area in the RTL model during the process of processing the first verification request.

[0142] Each module in the above data acquisition device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0143] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Fig. 9As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data and acquire data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a data acquisition method is implemented.

[0144] Those skilled in the art will understand that Fig. 9 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0145] In one embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.

[0146] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0147] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0148] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0149] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0150] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0151] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A data acquisition method, characterized in that: The method comprises: Obtaining a first memory access request output by a C model corresponding to the chip during a process of processing a first verification request; According to the first memory access request, the target data corresponding to the first memory access request is obtained from the data pool; wherein the target data is generated according to the second memory access request output by the RTL model corresponding to the chip when processing the first verification request; the first memory access request and the second memory access request are both used to request to obtain the target data; Returning the target data to the C model, so that the C model responds to the first verification request according to the target data; The method further comprises: Acquire a second memory access request output by the RTL model when processing the first verification request; Determining, according to the second memory access request, whether the target data exists in the data pool; In the case where the target data exists in the data pool, returning the target data to the RTL model; When the target data does not exist in the data pool, generating the target data based on a preset generation function; The generated target data is returned to the RTL model, and the generated target data is stored in the data pool in correspondence with the target address included in the second memory access request.

2. The method according to claim 1, characterized in that The data pool includes a correspondence relationship between multiple groups of cache data and memory access addresses; the step of obtaining target data corresponding to the first memory access request from the data pool according to the first memory access request includes: Determining, according to the first memory access request, a target address included in the first memory access request; Determine cache data corresponding to the access address identical to the target address from the data pool as the target data; The determining, according to the second memory access request, whether the target data exists in the data pool includes: Determining, according to the second memory access request, the target address included in the second memory access request; Determine whether cache data corresponding to the same memory access address as the target address exists in the data pool; if so, determine that the target data exists.

3. The method according to claim 2, characterized in that The step of determining, from the data pool, cache data corresponding to the access address identical to the target address as the target data includes: Determine whether there is cache data corresponding to the same memory access address as the target address in the data pool; If not, repeatedly query whether there is cache data corresponding to the same access address as the target address in the data pool, until the cache data corresponding to the same access address as the target address is obtained as the target data.

4. The method according to claim 3, characterized in that The method further comprises: If the target data is not obtained within the first waiting cycle, the step of repeatedly querying whether there is cache data corresponding to the same memory access address as the target address in the data pool is stopped, and an error message is returned to the C model, wherein the error message is used to indicate that the target data is not obtained.

5. The method according to claim 1, characterized in that The obtaining of a first memory access request output by a C model corresponding to the chip during processing of a first verification request includes: Acquire the first memory access request output by the C model when the target data is not acquired from the first buffer area in the C model during the process of processing the first verification request; The process of obtaining the second memory access request output by the RTL model during the process of processing the first verification request includes: The second memory access request outputted by the RTL model when the target data is not obtained from the second cache area in the RTL model during the process of processing the first verification request is obtained.

6. A data acquisition device, characterized in that: The device comprises: A request acquisition module, used for acquiring a first memory access request output by a C model corresponding to the chip during processing of a first verification request; A data acquisition module, configured to acquire target data corresponding to the first memory access request from a data pool according to the first memory access request; wherein the target data is generated according to the second memory access request output by the RTL model corresponding to the chip when processing the first verification request; and both the first memory access request and the second memory access request are used to request to acquire the target data; a response module, configured to return the target data to the C model, so that the C model can respond to the first verification request according to the target data; a data return module, configured to obtain a second memory access request output by the RTL model when processing the first verification request; determine whether the target data exists in the data pool according to the second memory access request; and return the target data to the RTL model if the target data exists in the data pool; A data generation module is used to generate the target data based on a preset generation function when the target data does not exist in the data pool; return the generated target data to the RTL model and store the generated target data and the target address included in the second memory access request in the data pool in correspondence.

7. The device according to claim 6, characterized in that The data pool includes a correspondence between multiple groups of cache data and memory access addresses; The data acquisition module is specifically configured to: determine, according to the first memory access request, a target address included in the first memory access request; determine, from the data pool, cache data corresponding to a memory access address identical to the target address as the target data; The data return module is specifically used to: determine the target address included in the second memory access request according to the second memory access request; determine whether there is cache data corresponding to the memory access address identical to the target address in the data pool, and if so, determine that the target data exists.

8. The device according to claim 7, characterized in that A data acquisition module, specifically used to determine whether there is cache data corresponding to the same access address as the target address in the data pool; If not, repeatedly query whether there is cache data corresponding to the same access address as the target address in the data pool, until the cache data corresponding to the same access address as the target address is obtained as the target data.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

11. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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