Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a substrate, a gate electrode disposed in the substrate, a channel region disposed over the gate electrode, a gate dielectric layer disposed between the gate electrode and the channel region, and at least two source / drain regions in contact with the channel region. The channel region includes at least one boron-carbon-nitrogen single-walled nanotube. Boron-carbon-nitrogen single-walled nanotubes enhance their semiconductor characteristics and reduce their metallic characteristics, thereby serving as channel regions in semiconductor transistor devices.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having semiconducting carbon nanotubes and a method for manufacturing the same. Background Art

[0002] Integrated circuit (IC) devices (also called semiconductor chips) can contain millions of transistors and other circuit elements, which are manufactured on a single silicon crystal substrate (wafer). In recent years, with the further reduction of technology nodes, device size has continued to shrink. At the same time, the channel resistance has also become lower, and channel leakage current may form. This phenomenon may make contemporary metal oxide semiconductor field effect transistor channels less useful for providing infinitely small memory cells. Therefore, it is necessary to find alternative methods with other feasible mechanisms compatible with the reduced memory cell geometry. Summary of the invention

[0003] The present disclosure provides an innovative semiconductor device and a manufacturing method thereof to solve the problems of the prior art.

[0004] In some embodiments of the present disclosure, a semiconductor device includes a substrate, a gate electrode disposed in the substrate, a channel region disposed above the gate electrode, a gate dielectric layer disposed between the gate electrode and the channel region, and at least two source / drain regions in contact with the channel region. The channel region includes at least one BCN single-walled nanotube.

[0005] In some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes the following steps: forming a gate electrode in a substrate; forming a gate dielectric layer above the gate electrode; forming at least one BCN single-walled nanotube on the gate dielectric layer; and forming at least two source / drain regions in contact with the BCN single-walled nanotube.

[0006] In some embodiments of the present disclosure, the BCN single-walled nanotubes contain less than 10 wt % of boron atoms and nitrogen atoms.

[0007] In some embodiments of the present disclosure, the BCN single-walled nanotubes contain 3 wt % to 5 wt % of boron atoms.

[0008] In some embodiments of the present disclosure, the BCN single-walled nanotubes contain 3 wt % to 5 wt % of nitrogen atoms.

[0009] In some embodiments of the present disclosure, the BCN single-walled nanotubes contain 3 wt % to 5 wt % of boron atoms and 3 wt % to 5 wt % of nitrogen atoms.

[0010] In some embodiments of the present disclosure, the BCN single-walled nanotubes include sp2-mixed carbon atoms, boron atoms, and nitrogen atoms.

[0011] In some embodiments of the present disclosure, the gate dielectric layer includes hafnium dioxide.

[0012] In some embodiments of the present disclosure, BCN SWNTs are synthesized by chemical vapor deposition or laser ablation.

[0013] In summary, the semiconductor device and the manufacturing method thereof disclosed herein utilize BCN single-walled nanotubes to enhance their semiconductor properties and reduce their metallic properties, so as to be used as a channel region in a semiconductor transistor device.

[0014] The above description will be described in detail below with reference to implementation examples, and further explanations will be provided for the technical solutions disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the accompanying drawings are described as follows:

[0016] Figure 1 A three-dimensional diagram illustrating a semiconductor transistor according to some embodiments of the present disclosure;

[0017] Figure 2 To illustrate Figure 1 A partial cross-sectional view of a semiconductor transistor; and

[0018] Figure 3 FIG. 4 is a graph showing the performance of three types of single-walled carbon nanotubes according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0019] In order to make the description of the present disclosure more detailed and complete, reference may be made to the attached drawings and various embodiments described below, in which the same numbers represent the same or similar elements. On the other hand, well-known elements and steps are not described in the embodiments to avoid unnecessary limitations on the present disclosure.

[0020] Please refer to Figure 1 , Figure 2 , Figure 1 A three-dimensional diagram of a semiconductor transistor according to some embodiments of the present disclosure is shown. Figure 2 Draw Figure 1 This figure shows a semiconductor transistor device 100 using at least one single-walled nanotube (SWNT) 108 as its channel region. A single-walled carbon nanotube refers to a single layer of graphene rolled into a seamless cylinder, with a diameter of typically nanometers (10 -9 Single-walled carbon nanotubes can range in length from a few nanometers to several centimeters. They have a high aspect ratio, meaning that their length is much greater than their diameter.

[0021] The semiconductor transistor device 100 mainly includes a semiconductor substrate 102, a gate dielectric layer 104, a gate electrode 110, at least one boron-carbon-nitrogen single-walled nanotube 108, and at least two source / drain regions 106. The gate electrode 110 is a conductor that controls the current flowing through the channel region of the transistor. When a voltage is applied to the gate electrode 110, an electric field is generated on the gate dielectric layer 104, and the electric field affects the conductivity of the channel region. By modulating the gate voltage, the transistor can control the current flowing through the channel, thereby realizing the transistor switching and amplification functions.

[0022] The gate electrode 110 is usually made of a highly conductive material that effectively controls the channel current. Commonly used gate electrode materials include doped polysilicon, metal films (such as aluminum or tungsten), or metal silicides (such as titanium silicide or tungsten silicide). In some embodiments of the present disclosure, the gate electrode 110 is formed to be embedded in the semiconductor substrate 102. The material of the gate electrode 110 is selected based on its conductivity and compatibility with the manufacturing process and is deposited on top of the gate dielectric layer. This can be done using techniques such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or sputtering. Photolithography is used to define the shape and size of the gate electrode. A photoresist material is applied to the gate electrode layer, exposed to ultraviolet light through a mask, and then developed. The developed photoresist acts as a protective layer for the area that will remain as the gate electrode. Plasma etching or other etching techniques are used to selectively remove the gate electrode material that is not protected by the developed photoresist. This step creates the desired gate electrode structure with precise size and alignment. In some cases, the gate electrode material can be doped to enhance its conductivity. Dopants are introduced into the gate electrode layer by ion implantation or diffusion processes. Doping helps improve the overall performance of the transistor. After the gate electrode is formed, contact structures are created to establish electrical connections to the source and drain regions of the transistor. These contacts enable current to flow through the channel when the appropriate voltage is applied.

[0023] The gate dielectric layer 104 is an insulating material, such as a single-walled nanotube 108, disposed between the gate electrode 110 and the channel region. The gate dielectric layer 104 acts as an electrical barrier to prevent current from flowing between the gate electrode and the channel when no voltage is applied. Traditionally, silicon dioxide (SiO2) is widely used as a gate dielectric material. However, as the size of transistors decreases, alternative materials with higher dielectric constants, namely high-k dielectrics, are used. Common high-k materials include hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium dioxide (ZrO2), and titanium dioxide (TiO2). The choice of material depends on factors such as the dielectric constant, compatibility with the manufacturing process, and the desired transistor performance. In some embodiments of the present disclosure, the gate dielectric layer 104 is hafnium dioxide (HfO2) coated on the gate electrode 110 and the semiconductor substrate 102. The use of hafnium dioxide (HfO2) as a gate dielectric has become common in advanced semiconductor technologies such as CMOS (complementary metal oxide semiconductor) transistors because of its superior electrical properties compared to traditional SiO2. HfO2 gate dielectrics enable better gate control, reduce power consumption, improve transistor performance, and enhance device scalability of modern semiconductor transistors. The gate dielectric layer 104 is typically formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). In the CVD process, precursor gases are introduced into a reaction chamber where they undergo a chemical reaction to form the desired dielectric material. The gas decomposes and is deposited on the substrate as a thin film. CVD can precisely control the thickness and uniformity of the gate dielectric layer. ALD is a deposition technique that involves exposing a substrate to different precursor gases in sequence. Each gas reacts with the surface, depositing one atomic layer at a time. ALD provides excellent control over film thickness, uniformity, and interface quality. PVD methods, such as sputtering or evaporation, involve physically depositing materials directly onto a substrate. These techniques rely on evaporation or sputtering of dielectric materials, which condense as a thin film on a substrate. After deposition, the gate dielectric layer may undergo annealing or other post-processing steps to improve its properties. Annealing can improve dielectric quality, reduce defects, and stabilize the material structure. The thickness of the gate dielectric layer 104 is critical to achieving the desired transistor performance. Advanced technology nodes often require ultra-thin dielectric layers, typically in the range of a few nanometers.

[0024] In order to make the single-walled nanotube (SWNT) 108 have semiconductor behavior, a combination of synthesis techniques and post-processing methods can be performed. In some embodiments of the present disclosure, the single-walled nanotube 108 can be a boron-carbon-nitrogen single-walled nanotube (BCN-SWNT), which involves a combination of synthesis techniques and post-processing methods to introduce boron and nitrogen dopants into the carbon nanotube structure. Boron and nitrogen atoms replace carbon atoms in the graphene lattice of the single-walled carbon nanotube, forming boron-carbon and nitrogen-carbon covalent bonds. This process changes the electronic structure and properties of the single-walled carbon nanotube.

[0025] Single-walled carbon nanotubes can be synthesized using techniques such as chemical vapor deposition (CVD) or laser ablation. The synthesis process involves growing carbon nanotubes from a carbonaceous precursor gas in the presence of a catalyst.

[0026] The first step of the chemical vapor deposition method is to prepare a catalyst, which is usually a transition metal catalyst supported on a substrate. Common catalyst materials include iron (Fe), cobalt (Co), nickel (Ni) or a combination thereof. Catalyst nanoparticles are usually dispersed on a substrate, such as silicon dioxide, aluminum oxide or magnesium oxide. The catalyst is then activated by a pretreatment process, such as reduction in a hydrogen atmosphere or exposure to other reaction gases. This step helps to create active catalytic sites on the catalyst surface. The substrate loaded with the catalyst is placed in a growth chamber, which is then evacuated and purged with an inert gas (such as argon or nitrogen) to form a controlled atmosphere. A carbon feedstock gas, such as a hydrocarbon (e.g., methane, ethylene, acetylene) or carbon monoxide is introduced into the growth chamber. The choice of carbon feedstock can affect the growth mechanism and final performance of single-walled carbon nanotubes. The growth chamber is heated to a high temperature, typically in the range of 600 to 1000 degrees Celsius. The duration of growth depends on the desired length and density of the single-walled carbon nanotubes. In the presence of an activated catalyst and at a high growth temperature, the carbon feedstock decomposes and carbon atoms are deposited on the catalyst surface. The carbon atoms then diffuse and form a tubular structure, resulting in the growth of single-walled carbon nanotubes.

[0027] In the case of laser ablation, a catalyst material (such as a transition metal) is mixed with a carbon source (usually graphite powder) to produce a composite target. The composite target is placed in a reaction chamber, which is then evacuated or filled with an inert gas. A high-power laser is focused onto the target, causing the catalyst and carbon source to vaporize and ablate. The vaporized carbon and catalyst material condense and cool in the reaction chamber, and single-walled carbon nanotubes are formed when the carbon atoms reassemble into a tubular structure.

[0028] In CVD and laser ablation methods, the choice of catalyst materials and their preparation significantly affect the growth and performance of single-walled carbon nanotubes. Commonly used catalysts include iron, cobalt, nickel or a combination thereof. The composition, size and distribution of the catalyst affect the diameter, chirality and quality of the synthesized single-walled carbon nanotubes.

[0029] Several different approaches are presented below to introduce boron and nitrogen dopants into single-walled carbon nanotube (SWCNT) structures.

[0030] Co-synthesis: During the synthesis process, a boron source and a nitrogen source can be introduced together with the carbonaceous precursor gas. By carefully selecting the appropriate boron source and nitrogen source, controlled amounts of boron and nitrogen can be incorporated into the carbon nanotube structure during the growth process.

[0031] Post-synthesis doping: After the synthesis of single-walled carbon nanotubes (SWCNTs), post-treatment processes can be applied to introduce boron and nitrogen dopants. For example, the SWCNTs can be exposed to a dopant-containing gas or chemically reacted to incorporate boron and nitrogen atoms into the carbon lattice. This can be achieved through techniques such as chemical vapor deposition or plasma processes.

[0032] After the doping step, the BCN SWNTs need to be characterized and separated from other CNTs and impurities. Techniques such as density gradient ultracentrifugation, gel-based separations, or size exclusion chromatography can be used to separate and purify the BCN SWNTs based on their properties, such as size or electronic behavior. The synthesized BCN SWNTs need to be characterized to verify their composition, structure, and properties. Techniques such as transmission electron microscopy (TEM), scanning electron microscopy (SEM), Raman spectroscopy, and X-ray photoelectron spectroscopy (XPS) can be used to analyze the BCN SWNTs.

[0033] In some embodiments of the present disclosure, the BCN single-walled nanotubes may include sp2 hybridization of carbon, boron and nitrogen atoms. In carbon nanotubes, each carbon atom is bonded to three adjacent carbon atoms in a hexagonal lattice pattern. These bonds are formed by sharing electrons, and the electron orbitals involved in the bonding are hybridized. In sp2 hybridization, three atomic orbitals belonging to carbon atoms combine to form three new hybrid orbitals that point to the corners of the triangular planar arrangement.

[0034] The resulting sp2 hybrid orbital has 33% s-character and 67% p-character, producing a planar structure and allowing carbon atoms to form strong sigma (σ) bonds with their neighbors. These sigma bonds are formed by the overlap of the sp2 hybrid orbitals.

[0035] In BCN single-walled nanotubes, boron and nitrogen atoms are incorporated into the carbon lattice, introducing additional atoms with different electronic configurations. However, the carbon-carbon bonds within the nanotube still retain sp2 hybridization and the resulting sp2 bonding.

[0036] The sp2 bonding in BCN single-walled nanotubes contributes to the unique electronic properties of these nanotubes. It affects the band structure, conductivity and other properties, making BCN single-walled nanotubes potentially useful in semiconductor crystals.

[0037] In some embodiments of the present disclosure, the BCN single-walled nanotubes may be manufactured to have less than 10 wt% of boron and nitrogen atoms. In some embodiments of the present disclosure, the BCN single-walled nanotubes may be manufactured to have 3 wt% to 5 wt% of boron atoms or 3 wt% to 5 wt% of nitrogen atoms. In some embodiments of the present disclosure, the BCN single-walled nanotubes may be manufactured to have 3 wt% to 5 wt% of boron atoms and 3 wt% to 5 wt% of nitrogen atoms.

[0038] The source / drain regions 106 are spaced apart from each other and in contact with the gate dielectric layer 104 and the single-walled nanotubes 108. The source / drain regions 106 are manufactured in a series of steps using various techniques. The material used for the source and drain regions 106 is typically doped silicon. Dopant atoms are introduced into the silicon lattice to change its electrical properties. The specific dopant used depends on the type of transistor being manufactured. For n-channel transistors, commonly used dopants include phosphorus or arsenic, which introduce additional electrons (n-type doping). For p-channel transistors, boron or indium can be used, which introduce holes (p-type doping).

[0039] The source / drain regions 106 may be formed by epitaxial growth to deposit a thin layer of doped silicon onto the gate dielectric layer 104 using techniques such as chemical vapor deposition (CVD) or molecular beam epitaxy. Dopant atoms are incorporated into the growing silicon layer to form the source and drain regions. After the deposition step, the wafer is subjected to a thermal annealing process. This step is critical to activating the dopant atoms, repairing any lattice damage caused by the deposition process, and optimizing the electrical properties of the source and drain regions.

[0040] Please refer to Figure 3 , which depicts the performance graphs of three types of single-walled carbon nanotubes according to some embodiments of the present disclosure. Using BCN single-walled nanotubes as channels, the channel region can have more than 90% semiconductor characteristics and less than 10% metal characteristics. Although the channel region uses conventional carbon-single-walled nanotubes I or carbon-single-walled nanotubes II, the channel region is only equipped with about 60%-70% semiconductor characteristics and less than 20%-30% metal characteristics.

[0041] In summary, the semiconductor device and the manufacturing method thereof disclosed herein utilize BCN single-walled nanotubes to enhance their semiconductor properties and reduce their metallic properties, so as to be used as a channel region in a semiconductor transistor device.

[0042] Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the definition of the attached claims.

[0043]

Explanation of symbols

[0044] In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the attached symbols are explained as follows:

[0045] 100:Semiconductor transistor device

[0046] 102: Base material

[0047] 104: Gate dielectric layer

[0048] 106: Source / drain region

[0049] 108: Single-walled nanotubes

[0050] 110: Gate electrode.

Claims

1. A semiconductor device, characterized in that: Include: Base material; A gate electrode is disposed in the substrate; A channel region is disposed above the gate electrode, wherein the channel region comprises at least one boron carbon nitrogen single-walled nanotube; A gate dielectric layer is disposed between the gate electrode and the channel region; as well as At least two source / drain regions are in contact with the channel region. 2 . The semiconductor device according to claim 1 , wherein the BCN single-walled nanotube comprises less than 10 wt % of boron atoms and nitrogen atoms. 3 . The semiconductor device according to claim 1 , wherein the BCN single-walled nanotube comprises 3 wt % to 5 wt % of boron atoms. 4 . The semiconductor device according to claim 1 , wherein the BCN single-walled nanotube comprises 3 wt % to 5 wt % of nitrogen atoms. 5 . The semiconductor device according to claim 1 , wherein the BCN single-walled nanotube comprises 3 wt % to 5 wt % of boron atoms and 3 wt % to 5 wt % of nitrogen atoms.

6. The semiconductor device according to claim 1, wherein the BCN single-walled nanotube comprises sp2-mixed carbon atoms, boron atoms and nitrogen atoms. The semiconductor device of claim 1 , wherein the gate dielectric layer comprises hafnium dioxide.

8. A method for manufacturing a semiconductor device, characterized in that: Include: forming a gate electrode in a substrate; forming a gate dielectric layer over the gate electrode; forming at least one BCN single-walled nanotube on the gate dielectric layer; and At least two source / drain regions are formed to contact the BCN single-walled nanotube. 9 . The manufacturing method according to claim 8 , wherein the BCN single-walled nanotube contains less than 10 wt % of boron atoms and nitrogen atoms. 10 . The manufacturing method according to claim 8 , wherein the BCN single-walled nanotube contains 3 wt % to 5 wt % of boron atoms. 11 . The manufacturing method according to claim 8 , wherein the BCN single-walled nanotube contains 3 wt % to 5 wt % of nitrogen atoms. 12 . The manufacturing method according to claim 8 , wherein the BCN single-walled nanotube comprises 3 wt % to 5 wt % of boron atoms and 3 wt % to 5 wt % of nitrogen atoms.

13. The manufacturing method according to claim 8, wherein the BCN single-walled nanotube comprises sp2-mixed carbon atoms, boron atoms and nitrogen atoms. The method according to claim 8 , wherein the gate dielectric layer comprises hafnium dioxide. 15 . The manufacturing method according to claim 8 , wherein the BCN single-walled nanotube is synthesized by chemical vapor deposition or laser ablation.

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