Semiconductor structure and manufacturing method thereof, ferroelectric memory and electronic equipment
By using graphene as an isolation layer in the semiconductor structure to block the passage of oxygen, the problem of reducing fatigue characteristics and maintenance characteristics of ferroelectric memory in oxygen-containing conditions is solved, and the performance of the memory is significantly improved.
Patent Information
- Application Number
- CN202310780904.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-28
- Publication Date
- 2024-12-31
AI Technical Summary
In the case of oxygen-containing ferroelectric memory, the residual polarization value gradually decreases, resulting in the problem of decreasing fatigue characteristics and maintenance characteristics.
A first isolation layer is provided in the semiconductor structure, and the material is graphene, which is located between the substrate and the ferroelectric layer to block the passage of oxygen and prevent the formation of the interface layer, thereby improving the fatigue characteristics and maintenance characteristics of the ferroelectric memory.
The interface layer that effectively prevents oxidation and improves the performance of ferroelectric memory, especially fatigue characteristics and maintenance characteristics, and extends the service life of the memory.
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Figure CN119233646A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof, a ferroelectric memory and an electronic device. Background Art
[0002] Ferroelectric memory has multiple functions and tunable properties, and has broad application prospects in low-power sensors, non-volatile data storage, and emerging artificial synapses.
[0003] However, in the case of oxygen-containing ferroelectric layers included in current ferroelectric memories, the residual polarization value will gradually decrease, and the fatigue characteristics or retention characteristics of the ferroelectric memories will be reduced. Summary of the invention
[0004] In view of the shortcomings of the existing methods, the present application proposes a semiconductor structure and a manufacturing method thereof, a ferroelectric memory and an electronic device to solve the technical problem of reduced fatigue characteristics or retention characteristics of the existing ferroelectric memory.
[0005] In a first aspect, an embodiment of the present application provides a semiconductor structure, including:
[0006] substrate;
[0007] A first isolation layer, disposed on one side of the substrate;
[0008] A ferroelectric layer, disposed on a side of the first isolation layer away from the substrate;
[0009] The electrode layer is arranged on a side of the ferroelectric layer away from the first isolation layer.
[0010] Optionally, the material of the first isolation layer includes graphene.
[0011] Optionally, the semiconductor structure comprises a ferroelectric field effect transistor;
[0012] The substrate comprises a first substrate; the first isolation layer is arranged on a side of the ferroelectric layer close to a channel region of the first substrate;
[0013] The electrode layer includes a gate electrode layer, and the gate electrode layer is arranged on a side of the ferroelectric layer away from the first isolation layer.
[0014] Optionally, the ferroelectric field effect transistor further includes a second isolation layer disposed between the ferroelectric layer and the gate electrode layer, and a material of the second isolation layer includes graphene.
[0015] Optionally, an orthographic projection of the first isolation layer on the first substrate coincides with a channel region of the first substrate.
[0016] Optionally, the semiconductor structure includes a ferroelectric capacitor structure;
[0017] The substrate includes a second substrate;
[0018] The ferroelectric capacitor structure includes a first electrode, and the electrode layer includes a second electrode; the first electrode, the first isolation layer, the ferroelectric layer and the second electrode are sequentially arranged on one side of the second substrate.
[0019] Optionally, the ferroelectric capacitor structure further includes a third isolation layer, wherein the third isolation layer is disposed between the ferroelectric layer and the second electrode, and a material of the third isolation layer includes graphene.
[0020] Optionally, the conductive material of the first electrode and the conductive material of the second electrode are both selected from at least one of titanium, ruthenium, tungsten, platinum, tantalum, molybdenum, and P-type silicon.
[0021] In a second aspect, an embodiment of the present application provides a ferroelectric memory, comprising: the semiconductor structure described in the first aspect.
[0022] In a third aspect, an embodiment of the present application provides an electronic device, comprising: the ferroelectric memory described in the second aspect.
[0023] In a fourth aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising:
[0024] A first isolation layer, a ferroelectric layer and an electrode layer are sequentially manufactured on one side of a substrate, wherein the material of the first isolation layer comprises graphene.
[0025] Optionally, a first isolation layer, a ferroelectric layer and an electrode layer are sequentially manufactured on one side of the substrate, comprising:
[0026] An initial first isolation layer, an initial ferroelectric layer and an initial gate electrode layer are sequentially manufactured on one side of the first substrate where the channel region is located, wherein the substrate comprises a first substrate;
[0027] The initial first isolation layer, the initial ferroelectric layer and the initial gate electrode layer are patterned to obtain a stacked first isolation layer, the ferroelectric layer and the gate electrode layer, so that the orthographic projections of the first isolation layer, the ferroelectric layer and the gate electrode layer on the first substrate coincide with the channel region of the first substrate, wherein the electrode layer includes a gate electrode layer.
[0028] Optionally, an initial first isolation layer, an initial ferroelectric layer, and an initial gate electrode layer are sequentially manufactured on a side of the first substrate where the channel region is located, including:
[0029] Fabricate an initial second isolation layer on a side of the initial ferroelectric layer away from the initial first isolation layer;
[0030] And, patterning the initial first isolation layer, the initial ferroelectric layer and the initial gate electrode layer to obtain the stacked first isolation layer, the ferroelectric layer and the gate electrode layer, comprising:
[0031] The initial second isolation layer is patterned to obtain a second isolation layer, so that an orthographic projection of the second isolation layer on the first substrate coincides with a channel region of the first substrate.
[0032] Optionally, manufacturing an initial first isolation layer on a side of the first substrate where the channel region is located includes:
[0033] The initial first isolation layer is obtained on the side of the first substrate where the channel region is located based on an epitaxial process; or the initial first isolation layer is transferred to the side of the first substrate where the channel region is located based on a transfer process.
[0034] Optionally, a first isolation layer, a ferroelectric layer and an electrode layer are sequentially manufactured on one side of the substrate, comprising:
[0035] A first electrode, a first isolation layer, a ferroelectric layer and a second electrode are sequentially manufactured on one side of a second substrate, wherein the substrate includes the second substrate, and the electrode layer includes the second electrode.
[0036] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:
[0037] The first isolation layer is provided between the substrate and the ferroelectric layer, which can prevent or eliminate the interface layer formed by oxidation of one side of the substrate caused by oxygen introduced during the growth of the ferroelectric layer, and can improve the fatigue characteristics and retention characteristics of the ferroelectric memory.
[0038] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0040] Figure 1 A cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of the present application;
[0041] Figure 2 A cross-sectional schematic diagram of a ferroelectric field effect transistor in a semiconductor structure provided in an embodiment of the present application;
[0042] Figure 3 A cross-sectional schematic diagram of another ferroelectric field effect transistor in a semiconductor structure provided in an embodiment of the present application;
[0043] Figure 4A schematic cross-sectional view of a ferroelectric capacitor structure in a semiconductor structure provided in an embodiment of the present application;
[0044] Figure 5 A cross-sectional schematic diagram of another ferroelectric capacitor structure in a semiconductor structure provided in an embodiment of the present application;
[0045] Figure 6 A schematic diagram of a process for manufacturing a ferroelectric effect transistor in a semiconductor structure manufacturing method provided in an embodiment of the present application;
[0046] Figure 7 A schematic cross-sectional view of a first substrate provided in manufacturing a ferroelectric effect transistor in a semiconductor structure manufacturing method provided in an embodiment of the present application;
[0047] Figure 8 A schematic cross-sectional view obtained after manufacturing a first source and drain region, a second source and drain region, and a channel region in a first substrate in manufacturing a ferroelectric effect transistor in a semiconductor structure manufacturing method provided in an embodiment of the present application;
[0048] Fig. 9 A schematic cross-sectional view obtained after sequentially manufacturing an initial first isolation layer, an initial ferroelectric layer, and an initial gate electrode layer on a side where a channel region of a first substrate is located in a ferroelectric effect transistor manufactured in a semiconductor structure manufacturing method provided in an embodiment of the present application;
[0049] Fig.10 A schematic cross-sectional view obtained after sequentially manufacturing an initial first isolation layer, an initial ferroelectric layer, an initial second isolation layer and an initial gate electrode layer on one side of a first substrate where a channel region is located in a ferroelectric effect transistor in a semiconductor structure manufacturing method provided in an embodiment of the present application;
[0050] Fig.11 A schematic cross-sectional view obtained after manufacturing a first electrode on one side of a second substrate in manufacturing a ferroelectric capacitor structure in a semiconductor structure manufacturing method provided in an embodiment of the present application;
[0051] Fig.12 This is a schematic cross-sectional view obtained after manufacturing a first isolation layer on a side of a first electrode away from a second substrate in manufacturing a ferroelectric capacitor structure in a semiconductor structure manufacturing method provided in an embodiment of the present application.
[0052] Description of reference numerals:
[0053] 1-semiconductor structure; 11-substrate; 12-first isolation layer; 13-ferroelectric layer; 14-electrode layer;
[0054] 2- ferroelectric field effect transistor; 21- first substrate; 211- channel region; 212- first source and drain region; 213- second source and drain region; 22- gate electrode layer; 23- second isolation layer;
[0055] 3- ferroelectric capacitor structure; 31- second substrate; 32- first electrode; 33- second electrode; 34- third isolation layer;
[0056] 41 - initial first isolation layer; 42 - initial ferroelectric layer; 43 - initial gate electrode layer; 44 - initial second isolation layer. DETAILED DESCRIPTION
[0057] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.
[0058] Those skilled in the art will appreciate that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".
[0059] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.
[0060] The research and development ideas of this application include: in the technology of related ferroelectric memory, when manufacturing ferroelectric field effect transistors, the oxygen introduced will cause the surface of the channel region to oxidize, generating an interface layer. The interface layer generates a strong electric field, which will aggravate the injection of charges from the channel region into the ferroelectric layer, resulting in the formation of defective morphology of the ferroelectric layer, thereby affecting the memory performance, especially the fatigue characteristics.
[0061] When manufacturing a ferroelectric capacitor structure, the oxygen introduced will cause the surface of the first electrode to oxidize, resulting in an interface layer. This interface layer will induce lattice dislocation in the subsequently grown ferroelectric layer, increase ferroelectric layer defects, and generate a depolarization field, thereby affecting the fatigue and retention characteristics of the ferroelectric capacitor structure.
[0062] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above technical problems with specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.
[0063] The present application embodiment provides a semiconductor structure 1. The structural schematic diagram of the semiconductor structure 1 is as follows: Figure 1 As shown, it includes a substrate 11, a first isolation layer 12, a ferroelectric layer 13 and an electrode layer 14.
[0064] The first isolation layer 12 is disposed on one side of the substrate 11 .
[0065] The ferroelectric layer 13 is disposed on a side of the first isolation layer 12 away from the substrate 11 .
[0066] The electrode layer 14 is disposed on a side of the ferroelectric layer 13 away from the first isolation layer 12 .
[0067] In the related art, during the process of manufacturing the ferroelectric layer 13 , the oxygen source introduced may easily cause the surface of the substrate 11 to be oxidized to form an interface layer, and the interface layer may cause the performance of the semiconductor structure 1 to degrade.
[0068] In the embodiment of the present application, a first isolation layer 12 is provided between the ferroelectric layer 13 and the substrate 11, which can block the gaseous oxygen source introduced during the growth of the ferroelectric layer 13 from reaching the substrate 11, and prevent the substrate 11 from being oxidized on the side facing the ferroelectric layer 13 to form an interface layer, thereby improving the fatigue characteristics and retention characteristics of the ferroelectric memory. The gaseous oxygen source includes at least one of oxygen, ozone and water vapor.
[0069] It should be noted that the interior of the substrate 11 may include a channel region 211, or one side of the substrate 11 may include a first electrode 32. When the ferroelectric layer 13 grows, a certain amount of oxygen needs to be introduced. The introduced oxygen will cause the surface of the channel region 211 or the surface of the first electrode 32 to be oxidized to form an interface layer.
[0070] Optionally, the material of the first isolation layer 12 includes graphene.
[0071] In the present embodiment, because the material of the first isolation layer 12 includes graphene, the graphene has a stable structure, ultra-high density and isolation function, is not easily oxidized, has a zero band gap, and has a very high electron mobility. It can further block the gaseous oxygen source introduced during the growth of the ferroelectric layer 13 from reaching the substrate 11, and prevent the substrate 11 from oxidizing on the side facing the ferroelectric layer 13 to produce an interface layer, thereby improving the fatigue characteristics and retention characteristics of the ferroelectric memory.
[0072] It should be noted that the graphene can be a single layer, and the physical thickness of the graphene is ultra-thin, at the sub-nanometer level, so the thickness of the first isolation layer 12 is very thin and does not affect the integration of the semiconductor structure.
[0073] Optionally, refer to Figure 2 and Figure 3 , the semiconductor structure 1 includes a ferroelectric field effect transistor 2 .
[0074] The substrate 11 includes a first substrate 21 ; the first isolation layer 12 is disposed on a side of the ferroelectric layer 13 close to a channel region 211 of the first substrate 21 .
[0075] The electrode layer 14 includes a gate electrode layer 22 . The gate electrode layer 22 is disposed on a side of the ferroelectric layer 13 away from the first isolation layer 12 .
[0076] In this embodiment, the first substrate 21 includes a channel region 211, a first source and drain region 212, and a second source and drain region 213. Along a direction parallel to the first substrate 21, the channel region 211 is disposed between the first source and drain region 212 and the second source and drain region 213. The first source and drain region 212 may be a source, and the second source and drain region 213 may be a drain, or the first source and drain region 212 may be a drain, and the second source and drain region 213 may be a source, and the specific definition may be set according to actual needs.
[0077] In the present application, a first isolation layer 12 is arranged between the channel region 211 and the ferroelectric layer 13, and the material of the first isolation layer 12 includes graphene. Since graphene has a stable structure and is not easily oxidized, and has ultra-high density and isolation function, it can completely block the formation of an interface layer between the ferroelectric layer 13 and the channel region 211, thereby helping to improve the performance of the ferroelectric memory.
[0078] Specifically, the material of the channel region 211 may be silicon or silicon germanium.
[0079] Optionally, the material of the gate electrode layer 22 includes at least one of titanium nitride, ruthenium, tungsten, platinum, and tantalum nitride.
[0080] Alternatively, if Figure 3 As shown, the ferroelectric field effect transistor 2 further includes a second isolation layer 23 disposed between the ferroelectric layer 13 and the gate electrode layer 22 , and the material of the second isolation layer 23 includes graphene.
[0081] It should be noted that the material of the gate electrode layer 22 is usually an oxygen-philic material. In the related technology, during the annealing process of manufacturing the ferroelectric layer 13 or during the subsequent use of devices such as the ferroelectric field effect transistor 2, the oxygen atoms in the ferroelectric layer 13 will diffuse to the interface between the ferroelectric layer 13 and the gate electrode layer 22, and may even diffuse into the interior of the gate electrode layer 22, causing an increase in oxygen vacancies in the ferroelectric layer 13 and a decrease in the residual polarization value, thereby deteriorating the fatigue characteristics and retention characteristics.
[0082] In the embodiment of the present application, a second isolation layer 23 is provided between the ferroelectric layer 13 and the gate electrode layer 22, and the material of the second isolation layer 23 includes graphene. Since graphene has a stable structure, is not easily oxidized, has a zero band gap, and has a high electron mobility, the second isolation layer 23 will not affect the electrical properties of the ferroelectric memory; at the same time, the second isolation layer 23 has an ultra-high density and isolation function, and can completely block the oxygen atoms in the ferroelectric layer 13 from diffusing to the interface between the ferroelectric layer 13 and the gate electrode layer 22, or can block the oxygen atoms in the ferroelectric layer 13 from diffusing to the inside of the gate electrode layer 22, which is conducive to suppressing or eliminating the generation of oxygen vacancies in the ferroelectric layer 13, thereby improving the fatigue resistance and retention characteristics of the ferroelectric memory.
[0083] Optionally, the material of the ferroelectric layer 13 includes hafnium oxide containing a doping element, and the doping element includes at least one of zirconium, silicon, yttrium, aluminum, and lanthanum.
[0084] In this embodiment, doped hafnium oxide is used as the material of the ferroelectric layer 13, so that the ferroelectric field effect transistor 2 is miniaturized. Moreover, the ferroelectric field effect transistor 2 is compatible with the traditional CMOS process, has a high operating speed and low power consumption.
[0085] Optionally, the content of oxygen atoms in the ferroelectric layer 13 is constant.
[0086] In this embodiment, reference Figure 3 Because the second isolation layer 23 is arranged between the ferroelectric layer 13 and the gate electrode layer 22, the second isolation layer 23 has ultra-high density and isolation function, which can prevent the oxygen atoms in the ferroelectric layer 13 from diffusing to the interface between the ferroelectric layer 13 and the gate electrode layer 22, or can prevent the oxygen atoms in the ferroelectric layer 13 from diffusing into the interior of the gate electrode layer 22, which is beneficial to inhibit or eliminate the generation of oxygen vacancies in the ferroelectric layer 13. The content of oxygen atoms in the ferroelectric layer 13 is constant, so as to improve the fatigue characteristics and retention characteristics of the ferroelectric memory.
[0087] Optionally, refer to Figure 2 and Figure 3 , the orthographic projection of the first isolation layer 12 on the first substrate 21 coincides with the channel region 211 of the first substrate 21 .
[0088] In this embodiment, because the material of the first isolation layer 12 includes graphene, which is a conductive material, the orthographic projection of the first isolation layer 12 on the first substrate 21 coincides with the channel region 211 of the first substrate 21, thereby preventing the first isolation layer 12 from short-circuiting with the first source and drain or the second source and drain.
[0089] Alternatively, if Figure 4 and Figure 5 As shown, the semiconductor structure 1 includes a ferroelectric capacitor structure 3 .
[0090] The substrate 11 includes a second substrate 31 .
[0091] The ferroelectric capacitor structure 3 includes a first electrode 32 , and the electrode layer 14 includes a second electrode 33 . The first electrode 32 , the first isolation layer 12 , the ferroelectric layer 13 , and the second electrode 33 are sequentially arranged on one side of the second substrate 31 .
[0092] In this embodiment, the first electrode 32 and the second electrode 33 of the ferroelectric capacitor structure 3 are generally symmetrical structures. The first isolation layer 12 is arranged between the ferroelectric layer 13 and the first electrode 32. In the related art, in the process of manufacturing the ferroelectric layer, the surface of the first electrode is easily oxidized to produce an interface layer, and the interface layer is easy to reduce the performance of the semiconductor structure. In the present application, a first isolation layer 12 including graphene is arranged between the first electrode 32 and the ferroelectric layer 13. Because the graphene structure is stable, it can suppress or eliminate the generation of the interface layer, thereby improving the performance of the semiconductor structure 1.
[0093] It should be noted that, when the semiconductor structure 1 includes the ferroelectric capacitor structure 3 , the semiconductor structure 1 also includes a switch transistor, and the switch transistor and the ferroelectric capacitor structure 3 constitute a ferroelectric memory (FeRAM).
[0094] Alternatively, if Figure 5 As shown, the ferroelectric capacitor structure 3 further includes a third isolation layer 34 , which is disposed between the ferroelectric layer 13 and the second electrode 33 , and the material of the third isolation layer 34 includes graphene.
[0095] In the related art, during the annealing process of manufacturing the ferroelectric layer 13 or in subsequent use, the oxygen atoms in the ferroelectric layer 13 will diffuse to the interface between the ferroelectric layer 13 and the second electrode 33; the oxygen atoms in the ferroelectric layer 13 will diffuse to the interior of the second electrode 33, causing the oxygen vacancies in the ferroelectric layer 13 to increase and the residual polarization value to decrease, thereby deteriorating the fatigue characteristics and retention characteristics.
[0096] In the embodiment of the present application, a third isolation layer 34 is provided between the ferroelectric layer 13 and the second electrode 33, and the material of the third isolation layer 34 includes graphene. Since graphene has a stable structure, is not easily oxidized, has a zero band gap, and has a high electron mobility, the third isolation layer 34 will not affect the electrical properties of the ferroelectric memory; at the same time, the third isolation layer 34 has a high density and isolation function, and can prevent the oxygen atoms in the ferroelectric layer 13 from diffusing to the interface between the ferroelectric layer 13 and the second electrode 33, or can prevent the oxygen atoms in the ferroelectric layer 13 from diffusing to the inside of the second electrode 33, which is conducive to suppressing or eliminating the generation of oxygen vacancies in the ferroelectric layer 13, thereby improving the fatigue resistance and retention characteristics of the ferroelectric memory.
[0097] Optionally, the conductive material of the first electrode 32 and the conductive material of the second electrode 33 are both selected from at least one of titanium, ruthenium, tungsten, platinum, tantalum, and molybdenum.
[0098] Based on the same inventive concept, an embodiment of the present application provides a ferroelectric memory, including the semiconductor structure 1 provided in the above embodiment.
[0099] In this embodiment, the ferroelectric memory includes the semiconductor structure 1 provided in the above embodiment, and its beneficial effects also include the beneficial effects of the semiconductor structure 1 provided in the above embodiment, which will not be described in detail here.
[0100] Based on the same inventive concept, an embodiment of the present application provides an electronic device, including the ferroelectric memory provided by the above embodiment.
[0101] In this embodiment, since the electronic device adopts any one of the ferroelectric memories provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.
[0102] Optionally, the electronic device may include a smart phone, a computer, a tablet computer, artificial intelligence, a wearable device or a smart mobile terminal.
[0103] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any ferroelectric memory provided in the above-mentioned embodiments of the present application in different devices according to actual application requirements, so as to obtain the electronic device provided in the embodiments of the present application.
[0104] Based on the same inventive concept, an embodiment of the present application provides a method for manufacturing a semiconductor structure 1, the method comprising: sequentially manufacturing a first isolation layer 12, a ferroelectric layer 13 and an electrode layer 14 on one side of a substrate 11, wherein the material of the first isolation layer comprises graphene.
[0105] In this embodiment, a first isolation layer 12 is arranged between the substrate 11 and the ferroelectric layer 13, and the material of the first isolation layer 12 includes graphene. Since graphene has a stable structure and is not easily oxidized, and has ultra-high density and isolation function, it can completely block the formation of an interface layer between the ferroelectric layer 13 and the channel region 211, which is beneficial to improving the performance of the ferroelectric memory.
[0106] Optionally, in the above manufacturing method, the first isolation layer 12, the ferroelectric layer 13 and the electrode layer 14 are sequentially manufactured on one side of the substrate 11, including the following steps S101 to S102. The flow chart of the method is as follows: Figure 6 shown.
[0107] S101 : an initial first isolation layer 41 , an initial ferroelectric layer 42 and an initial gate electrode layer 43 are sequentially manufactured on one side of a first substrate 21 where a channel region 211 is located. The substrate 11 includes the first substrate 21 .
[0108] In this embodiment, the initial ferroelectric layer 42 is deposited, and its material is usually hafnium oxide including doped elements. The hafnium oxide doped with elements is used as the material of the ferroelectric layer 13, so that the ferroelectric field effect transistor 2 has miniaturization. Moreover, the ferroelectric field effect transistor 2 is compatible with the traditional CMOS process, and has a fast working speed and low power consumption. Fig. 9 It is a cross-sectional schematic diagram obtained after an initial first isolation layer 41 , an initial ferroelectric layer 42 and an initial gate electrode layer 43 are sequentially manufactured on the side of the first substrate 21 where the channel region 211 is located.
[0109] Optionally, in step S101, manufacturing an initial first isolation layer 41 on a side of the first substrate 21 where the channel region 211 is located includes:
[0110] The initial first isolation layer 41 is obtained on the side of the first substrate 21 where the channel region 211 is located based on an epitaxial process; or the initial first isolation layer 41 is transferred to the side of the first substrate 21 where the channel region 211 is located based on a transfer process.
[0111] In this embodiment, the initial first isolation layer 41 can be manufactured in two ways, one of which is to grow the initial first isolation layer 41 directly on the surface of the channel region 211 of the first substrate 21 through a vapor deposition process; the other way is to grow the initial first isolation layer 41 on another substrate, and then transfer the initial first isolation layer 41 to the side where the channel region 211 of the first substrate 21 is located through a transfer process. It is sufficient to ensure that the first isolation layer 12 is manufactured before the ferroelectric layer 13 is manufactured.
[0112] Specifically, the first isolation layer 12 may be a single layer, and its thickness may be less than 1 nanometer.
[0113] S102: Patterning the initial first isolation layer 41, the initial ferroelectric layer 42 and the initial gate electrode layer 43 to obtain a stacked first isolation layer 12, a ferroelectric layer 13 and a gate electrode layer 22, so that the orthographic projections of the first isolation layer 12, the ferroelectric layer 13 and the gate electrode layer 22 on the first substrate 21 coincide with the channel region 211 of the first substrate 21, wherein the electrode layer 14 includes the gate electrode layer 22.
[0114] Optionally, Fig. 9 The initial first isolation layer 41, the initial ferroelectric layer 42 and the initial gate electrode layer 43 are patterned to obtain Figure 2The stacked first isolation layer 12 , ferroelectric layer 13 and gate electrode layer 22 are shown such that their orthographic projections on the first substrate 21 coincide with the channel region 211 of the first substrate 21 .
[0115] In this embodiment, the orthographic projection of the first isolation layer 12 on the first substrate 21 overlaps with the channel region 211 of the first substrate 21 , which can avoid signal interference between the first isolation layer 12 and the first source and drain or the second source and drain.
[0116] Optionally, in the above step S101, before the initial first isolation layer 41, the initial ferroelectric layer 42 and the initial gate electrode layer 43 are sequentially manufactured on the side of the channel region 211 of the first substrate 21, it also includes: manufacturing a first source and drain region 212, a second source and drain region 213 and the channel region 211 in the first substrate 21, so that the channel region 211 is arranged between the first source and drain region 212 and the second source and drain region 213 along a direction parallel to the substrate 11.
[0117] In this embodiment, Figure 7 is a cross-sectional schematic diagram of a provided first substrate 21; Figure 8 It is a schematic cross-sectional view obtained after manufacturing the first source and drain region 212 , the second source and drain region 213 , and the channel region 211 in the first substrate 21 .
[0118] In this embodiment, the first source and drain regions 212 and the second source and drain regions 213 may be p-type doped or n-type doped.
[0119] Optionally, in the above step S101, an initial first isolation layer 41, an initial ferroelectric layer 42 and an initial gate electrode layer 43 are sequentially manufactured on the side of the first substrate 21 where the channel region 211 is located, including:
[0120] An initial second isolation layer 44 is fabricated on a side of the initial ferroelectric layer 42 that is remote from the initial first isolation layer 41 .
[0121] In this embodiment, an initial first isolation layer 41, an initial ferroelectric layer 42, an initial second isolation layer 44 and an initial gate electrode layer 43 are sequentially manufactured on the side where the channel region 211 of the first substrate 21 is located. The material of the initial second isolation layer 44 includes graphene. Since graphene has a stable structure, is not easily oxidized, has a zero band gap, and has a high electron mobility, the second isolation layer 23 will not affect the electrical properties of the ferroelectric memory. Fig.10 It is a cross-sectional schematic diagram obtained after an initial first isolation layer 41 , an initial ferroelectric layer 42 , an initial second isolation layer 44 and an initial gate electrode layer 43 are sequentially manufactured on the side of the first substrate 21 where the channel region 211 is located.
[0122] Optionally, in the above step S102, the initial first isolation layer 41, the initial ferroelectric layer 42 and the initial gate electrode layer 43 are patterned to obtain a stacked first isolation layer 12, ferroelectric layer 13 and gate electrode layer 22, including: patterning the initial second isolation layer 44 so that the orthographic projection of the second isolation layer 23 on the first substrate 21 coincides with the channel region 211 of the first substrate 21.
[0123] Specifically, the initial first isolation layer 41, the initial ferroelectric layer 42, the initial second isolation layer 44 and the initial gate electrode layer 43 are patterned to obtain a stacked first isolation layer 12, a ferroelectric layer 13, a second isolation layer 23 and a gate electrode layer 22. In addition, the second isolation layer 23 can also be made by the same method as the first isolation layer 12, which will not be described in detail here.
[0124] In this embodiment, a second isolation layer 23 is provided between the ferroelectric layer 13 and the gate electrode layer 22, and the material of the second isolation layer 23 includes graphene. The second isolation layer 23 has a high density and isolation function, and can prevent oxygen atoms in the ferroelectric layer 13 from diffusing to the interface between the ferroelectric layer 13 and the gate electrode layer 22, or can prevent oxygen atoms in the ferroelectric layer 13 from diffusing to the inside of the gate electrode layer 22, which is beneficial to suppress or eliminate the generation of oxygen vacancies in the ferroelectric layer 13, thereby improving the fatigue resistance and retention characteristics of the ferroelectric memory.
[0125] Optionally, in the manufacturing method of the semiconductor structure, a first isolation layer 12, a ferroelectric layer 13 and an electrode layer 14 are manufactured in sequence on one side of a substrate 11, wherein the material of the first isolation layer includes graphene, including: a first electrode 32, a first isolation layer 12, a ferroelectric layer 13 and a second electrode 33 are manufactured in sequence on one side of a second substrate 31, the substrate 11 includes a second substrate 31, and the electrode layer 14 includes a second electrode 33.
[0126] In the related art, during the process of manufacturing the ferroelectric layer 13 , the surface of the first electrode 32 is easily oxidized to generate an interface layer, which is likely to reduce the performance of the semiconductor structure 1 .
[0127] In the embodiment of the present application, a first isolation layer 12 including graphene is provided between the first electrode 32 and the ferroelectric layer 13. Since the graphene structure is stable, the generation of the interface layer can be suppressed or eliminated, thereby improving the performance of the semiconductor structure 1.
[0128] Optionally, in the above manufacturing method, the first electrode 32, the first isolation layer 12, the ferroelectric layer 13 and the second electrode 33 are sequentially manufactured on one side of the second substrate 31, including:
[0129] A first electrode 32 is fabricated on one side of the second substrate 31 .
[0130] The first isolation layer 12 is manufactured on a side of the first electrode 32 away from the second substrate 31 .
[0131] A ferroelectric layer 13 , a third isolation layer 34 , and a second electrode 33 are sequentially manufactured on a side of the first isolation layer 12 away from the second substrate 31 , and the third isolation layer 34 includes graphene.
[0132] In this embodiment, a third isolation layer 34 is arranged between the ferroelectric layer 13 and the second electrode 33. The third isolation layer 34 has a high density and isolation function, and can block the oxygen atoms in the ferroelectric layer 13 from diffusing to the interface between the ferroelectric layer 13 and the second electrode 33, or can block the oxygen atoms in the ferroelectric layer 13 from diffusing into the interior of the second electrode 33, which is beneficial to suppress or eliminate the generation of oxygen vacancies in the ferroelectric layer 13, thereby improving the anti-fatigue characteristics and retention characteristics of the ferroelectric memory. Fig.11 It is a schematic cross-sectional view obtained after manufacturing the first electrode 32 on one side of the second substrate 31 . Fig.12 It is a schematic cross-sectional view obtained after the first isolation layer 12 is manufactured on the side of the first electrode 32 away from the second substrate 31 .
[0133] Optionally, in the above manufacturing method, the first isolation layer 12 is manufactured on one side of the second substrate 31, including: obtaining the first isolation layer 12 based on an epitaxial process on the side of the first electrode 32 away from the second substrate 31; or transferring the first isolation layer 12 to the side of the first electrode 32 away from the second substrate 31 based on a transfer process.
[0134] In this embodiment, the first isolation layer 12 can be manufactured in two ways, one of which is to grow the first isolation layer 12 directly on the surface of the first electrode 32 by a vapor deposition process; the other is to grow the first isolation layer 12 on another substrate and then transfer the first isolation layer 12 to the surface of the first electrode 32 by a transfer process. In addition, the third isolation layer 34 can also be manufactured by the same method as the first isolation layer 12, which will not be described in detail here.
[0135] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:
[0136] 1. In the embodiment of the present application, a first isolation layer is provided between the channel region and the ferroelectric layer, and the material of the first isolation layer includes graphene. Since graphene has a stable structure and is not easily oxidized, and has ultra-high density and isolation function, it can prevent the formation of an interface layer between the ferroelectric layer and the channel region, thereby facilitating the improvement of the performance of the ferroelectric memory.
[0137] 2. In the embodiment of the present application, a second isolation layer is provided between the ferroelectric layer and the gate electrode layer, and the material of the second isolation layer includes graphene. Since graphene has a stable structure, is not easily oxidized, has a zero band gap, and has a high electron mobility, the second isolation layer will not affect the electrical properties of the ferroelectric memory; at the same time, the second isolation layer has a high density and isolation function, and can prevent the oxygen atoms in the ferroelectric layer from diffusing to the interface between the ferroelectric layer and the gate electrode layer, or can prevent the oxygen atoms in the ferroelectric layer from diffusing to the inside of the gate electrode layer, which is conducive to suppressing or eliminating the generation of oxygen vacancies in the ferroelectric layer, thereby improving the fatigue resistance and retention characteristics of the ferroelectric memory.
[0138] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.
[0139] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the exemplary directions or positional relationships shown in the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.
[0140] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.
[0141] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0142] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.
[0143] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence according to the indication of the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless there is a clear description herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders according to demand. Moreover, some or all of the steps in each flow chart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time, and the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiments of the present application do not limit this.
[0144] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.
Claims
1. A semiconductor structure, characterized in that: include: substrate; A first isolation layer, disposed on one side of the substrate; A ferroelectric layer, disposed on a side of the first isolation layer away from the substrate; The electrode layer is arranged on a side of the ferroelectric layer away from the first isolation layer.
2. The semiconductor structure according to claim 1, characterized in that: The material of the first isolation layer includes graphene.
3. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure includes a ferroelectric field effect transistor; The substrate comprises a first substrate; the first isolation layer is arranged on a side of the ferroelectric layer close to a channel region of the first substrate; The electrode layer includes a gate electrode layer, and the gate electrode layer is arranged on a side of the ferroelectric layer away from the first isolation layer.
4. The semiconductor structure according to claim 3, characterized in that: The ferroelectric field effect transistor further includes a second isolation layer disposed between the ferroelectric layer and the gate electrode layer, wherein a material of the second isolation layer includes graphene.
5. The semiconductor structure according to claim 3, characterized in that: An orthographic projection of the first isolation layer on the first substrate coincides with a channel region of the first substrate.
6. The semiconductor structure according to claim 1, characterized in that The semiconductor structure includes a ferroelectric capacitor structure; The substrate includes a second substrate; The ferroelectric capacitor structure includes a first electrode, and the electrode layer includes a second electrode; the first electrode, the first isolation layer, the ferroelectric layer and the second electrode are sequentially arranged on one side of the second substrate.
7. The semiconductor structure according to claim 5, characterized in that: The ferroelectric capacitor structure further includes a third isolation layer, which is disposed between the ferroelectric layer and the second electrode, and a material of the third isolation layer includes graphene.
8. A ferroelectric memory, characterized in that: The semiconductor structure comprises any one of claims 1 to 7.
9. An electronic device, characterized in that: Comprising the ferroelectric memory as claimed in claim 8.
10. A method for manufacturing a semiconductor structure, characterized in that: include: A first isolation layer, a ferroelectric layer and an electrode layer are sequentially manufactured on one side of a substrate, wherein the material of the first isolation layer comprises graphene.
11. The manufacturing method according to claim 10, characterized in that: A first isolation layer, a ferroelectric layer and an electrode layer are sequentially manufactured on one side of the substrate, including: An initial first isolation layer, an initial ferroelectric layer and an initial gate electrode layer are sequentially manufactured on one side of the first substrate where the channel region is located, wherein the substrate comprises a first substrate; The initial first isolation layer, the initial ferroelectric layer and the initial gate electrode layer are patterned to obtain a stacked first isolation layer, the ferroelectric layer and the gate electrode layer, so that the orthographic projections of the first isolation layer, the ferroelectric layer and the gate electrode layer on the first substrate coincide with the channel region of the first substrate, wherein the electrode layer includes a gate electrode layer.
12. The manufacturing method according to claim 11, wherein an initial first isolation layer, an initial ferroelectric layer and an initial gate electrode layer are sequentially manufactured on a side of the first substrate where the channel region is located, comprising: Fabricate an initial second isolation layer on a side of the initial ferroelectric layer away from the initial first isolation layer; And, patterning the initial first isolation layer, the initial ferroelectric layer and the initial gate electrode layer to obtain the stacked first isolation layer, the ferroelectric layer and the gate electrode layer, comprising: The initial second isolation layer is patterned to obtain a second isolation layer, so that an orthographic projection of the second isolation layer on the first substrate coincides with a channel region of the first substrate.
13. The manufacturing method according to claim 11, characterized in that: Manufacturing an initial first isolation layer on a side of the first substrate where the channel region is located, comprising: The initial first isolation layer is obtained on the side of the first substrate where the channel region is located based on an epitaxial process; or the initial first isolation layer is transferred to the side of the first substrate where the channel region is located based on a transfer process.
14. The manufacturing method according to claim 10, characterized in that: A first isolation layer, a ferroelectric layer and an electrode layer are sequentially manufactured on one side of the substrate, including: A first electrode, a first isolation layer, a ferroelectric layer and a second electrode are sequentially manufactured on one side of a second substrate, wherein the substrate includes the second substrate, and the electrode layer includes the second electrode.