Method and system for checking effectiveness of voltage identification of layout line and electronic equipment thereof

Abstract

The invention discloses a method and a system for checking the effectiveness of a voltage identifier of a layout line and electronic equipment thereof, and belongs to the technical field of layout data processing. Comprising the steps of obtaining line voltage of a circuit, including a line name and a voltage value; obtaining a layout line voltage identifier which comprises a line name and a voltage value; and comparing whether the layout line voltage identifier is consistent with the line voltage of the circuit, and generating a voltage identifier validity report of the layout line. The correctness and effectiveness of the layout line voltage identification value are verified through the line voltage value under the actual working condition of the circuit, the situation that the line voltage is unreasonable due to the fact that the identification layer or the voltage value is manually and mistakenly used is avoided, and therefore the interval requirement rule checking result caused by the line voltage difference is prevented from being influenced; and the accuracy and the reliability of the layout line voltage validity check are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of layout data processing, and in particular to a method, system and electronic equipment for checking the validity of voltage markings of layout lines. Background Art

[0002] In integrated circuit (IC) design, DRC (Design Rule Check) verification plays a vital role in chip design. It mainly analyzes and verifies the physical design in many aspects through rule checking. DRC Rule, which defines a series of standards and restrictions that design objects (such as line width, spacing, etc.) should meet to ensure that the design meets the expected electrical performance, reliability, manufacturability and testability requirements. It is an important step to ensure design reliability and manufacturability. The voltage rule check in DRC verification is to prevent problems such as voltage conflicts and short circuits. If the spacing between areas with different voltage differences is too small, it may cause voltage interference and even cause a short circuit. Therefore, in order to ensure the safe operation of the circuit, DRC sets the corresponding minimum spacing requirements according to the size of the voltage difference.

[0003] like Figure 1 As shown in the figure, DRC provides a dedicated voltage identification CAD layer to determine the line voltage value, such as the voltage mark layer and the text layer. Use these layer marks to mark the appropriate voltage value on the line in the layout, and DRC calculates the voltage difference between adjacent lines according to the following formula: Delta V = MAX (Net1 Voltage High - Net2Voltage Low, Net2 Voltage High - Net1 Voltage Low). Then run the DRC rules to check whether the voltage difference meets the corresponding spacing requirements.

[0004] Although DRC rules can identify the voltage value of the line according to the mark layer or text layer, DRC rules cannot check whether the voltage value of the line is valid and consistent with the actual working conditions of the design. If the text layer or mark layer is used incorrectly, or the voltage value is set unreasonably, it will affect the result of the voltage difference spacing check. Wrong or invalid voltage value identification may appear in DRC clean, thus covering up the real error. Summary of the invention

[0005] In order to solve the problems existing in the above background technology, the present invention adopts the following technical solutions: The present application provides a method for checking the validity of voltage markings of layout lines, comprising the steps of: Get the line voltage of the circuit, including line name and voltage value; Get the layout line voltage identification, including line name and voltage value; Compare the line voltage identification on the layout and the line voltage of the circuit to see if they are consistent, and generate a report on the validity of the voltage identification of the layout line.

[0006] As a preferred solution of the present application, the step of obtaining the voltage identification of the circuit line specifically includes: Create a circuit; Set up test incentives; Run the simulation and obtain the simulation results; Save the line names and voltage values ​​in the circuit from the simulation results.

[0007] As a preferred solution of the present application, the test stimulus is set to create a test stimulus according to the actual working condition of the circuit, including designing the reference voltage of all lines in the circuit; the simulation result is exported in a text file or a spreadsheet.

[0008] As a preferred solution of the present application, the step of obtaining the voltage mark of the layout line specifically includes: Create a layout; Define the line voltage identification layer; select the voltage identification layer to cover the corresponding physical layer; Extract line names and voltage values ​​in the layout and generate voltage reports for the lines in the layout.

[0009] As a preferred solution of the present application, generating a voltage report of a line in the layout includes extracting a line in the layout and identifying a line voltage to generate a voltage report of the line in the layout according to a DRC rule, specifically including: Layout parsing: parse the layout file to obtain the physical layout, connection relationship and attribute information in the layout; Circuit identification: DRC tools identify circuits in the layout, including their geometric features, connection relationships, and other attributes; Voltage marker extraction: The DRC tool extracts voltage marker information from the layout.

[0010] As a preferred solution of the present application, after the voltage identification is extracted, the following steps are further included: Voltage value association: The extracted voltage identification information is associated with the corresponding voltage value; Data Integration: The extracted line names and voltage values ​​are integrated into a format that can be used for report generation or subsequent analysis.

[0011] As a preferred solution of the present application, comparing whether the voltage identification of the lines of the layout and the circuit are consistent, and generating a voltage identification validity report of the layout lines specifically includes the following steps: S301, converting LVS intermediate result data through EDA tools to obtain the corresponding relationship between the layout and the circuit line name; S302, running the script to compare the voltage values ​​of the same line in the circuit and the layout, and generating a difference report; S303. According to the differentiation report, determine the consistency of the circuit and the layout.

[0012] As a preferred solution of the present application, in step S303, if the layout and the circuit are inconsistent, the following steps are performed: In the voltage mark validity report generated for the layout line, fill in the voltage mark as invalid; Analyze discrepancies in reporting to determine causes and impacts of inconsistencies; Modify the voltage mark corresponding to the layout.

[0013] As a preferred solution of the present application, if the layout and the circuit are inconsistent, it also includes iterative steps S301-S303 until the voltage identification of all lines in the layout is consistent with the circuit.

[0014] The present application also provides a system for checking the validity of voltage markings of layout lines, which is applied to the method for checking the validity of voltage markings of layout lines as described above; the system comprises: A data acquisition module configured to acquire line voltage information data of the circuit and the layout, wherein the line voltage information data includes line names and voltage values; A data processing module is configured to compare and analyze the line names and voltage values ​​of the circuits and layouts collected by the data collection module; The data optimization module is configured to optimize the inconsistent data after comparison in the data processing module, specifically to modify the voltage mark corresponding to the layout until the voltage marks of all lines in the layout are consistent with the circuit.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention verifies the correctness and validity of the layout line voltage identification value through the line voltage value under the actual working condition of the circuit, thereby avoiding the situation where the line voltage is unreasonable due to the erroneous use of the identification layer or voltage value, thereby avoiding affecting the spacing requirement rule inspection result caused by the line voltage difference.

[0016] The present invention ensures that the voltage mark of the line in the layout is consistent with the actual voltage in the circuit by means of circuit simulation and layout extraction, which helps to find and solve the problem of inconsistency between the layout and the circuit during the design process, thereby ensuring the accuracy and reliability of the design.

[0017] The present invention also modifies the voltage marks of the lines in the inconsistent layout according to the difference report, and iterates the circuit and layout. Figure 1 The consistency check process is continued until the voltage identification of all lines in the layout is consistent with the circuit. This not only solves the problem of inconsistency between the layout and the circuit, but also improves the accuracy and reliability of the layout line voltage validity check. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of a voltage identification layer of a layout in the background technology of the present invention; Figure 2 A schematic flow chart of a method for checking the validity of voltage markings of layout lines provided in the first embodiment of the present invention; Figure 3 This is a flow chart of step S1 of the first embodiment of the present invention; Figure 4 This is a flow chart of step S2 of the first embodiment of the present invention; Figure 5 This is a flow chart of step S3 of the first embodiment of the present invention; Figure 6 A schematic diagram of the structure of a system for checking the validity of voltage markings of layout lines provided in the second embodiment of the present invention; Figure 7 A schematic diagram of the structure of an electronic device provided in Embodiment 3 of the present invention; DETAILED DESCRIPTION The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. It should be noted that relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0020] The present invention provides a method, system and electronic device for checking the validity of the voltage identification of the layout line. The correctness and validity of the voltage identification value of the layout line is verified by the line voltage value under the actual working condition of the circuit, so as to avoid the situation where the line voltage is unreasonable due to the erroneous use of the identification layer or voltage value, thereby avoiding the spacing requirement rule inspection result caused by the line voltage difference. Through circuit simulation and layout extraction, it is ensured that the voltage identification of the line in the layout is consistent with the actual voltage in the circuit. This helps to discover and solve the problem of inconsistency between the layout and the circuit during the design process, so as to ensure the accuracy and reliability of the design. The voltage identification of the inconsistent layout line is also modified according to the differentiation report, and the circuit and layout are iterated. Figure 1 The consistency check process is repeated until the voltage identification of all lines in the layout is consistent with the circuit. This not only solves the problem of inconsistency between the layout and the circuit, but also improves the accuracy and reliability of the layout line voltage validity check. The technical solution of the present invention is described in detail below: Embodiment 1 See also Figure 2 The present invention provides a method for checking the validity of voltage marking of a layout line, comprising the steps of: S1. Obtain the line voltage of the circuit, including the line name and voltage value, wherein the line name refers to the name of the line in the circuit, and the voltage value refers to the voltage value of the corresponding line in the circuit.

[0021] like Figure 3 As shown, step S1, obtaining the line voltage of the circuit, including the line name and the voltage value, specifically includes the following steps: S101, creating a circuit: according to the actual layout to be checked, creating a circuit corresponding to the layout in a circuit design tool. In an embodiment of the present invention, the circuit design tool adopts a commonly used circuit design tool in the art, such as an EDA tool, a Synopsys design tool, and an Altium Designer, etc., which is not limited here.

[0022] S102, setting test stimulus; creating a test stimulus according to the actual working condition of the circuit. In this embodiment, setting the test stimulus includes designing reference voltages for all lines in the circuit.

[0023] Set reference voltage: According to the reference voltage of all lines in the circuit, these reference voltages can be power supply voltage, amplitude of input signal, etc.

[0024] Set test stimulus: According to the reference voltage of all lines in the circuit, set a suitable test stimulus. Setting test stimulus means providing one or more sets of specific input signals to the input ports or other key nodes of the circuit in circuit simulation to simulate the response of the circuit under actual working conditions. These input signals can be voltage pulses, constant voltage, current injection or other forms of signals to stimulate the circuit and observe its response. By setting test stimulus, you can evaluate the performance of the circuit under different working conditions, verify the correctness of the design, analyze the stability and robustness of the circuit, and identify potential problems and room for improvement.

[0025] In actual engineering, setting test stimulus is usually achieved through simulation tools, in which the type, parameters and timing of test stimulus can be specified, and then the simulation can be run and the response of the circuit can be analyzed. In this way, the performance and reliability of the circuit can be verified through simulation before the actual circuit is manufactured, thus saving time and cost.

[0026] S103, running simulation to obtain simulation results; In an embodiment of the present invention, the simulation may use a SPICE simulator or other simulation tools, and then load the created circuit model and the set test stimulus into the SPICE simulator or other simulation tools, and then run the simulation to obtain the voltage response of the output line.

[0027] S104, saving the line names and voltage values ​​in the circuit from the simulation results, and generating high and low voltage related files of the lines in the circuit.

[0028] Saving the line names and voltage values ​​in the circuit includes exporting the simulation results from the simulation tool after the simulation is completed. The simulation results can usually be exported as a text file or spreadsheet. The content of the simulation result file includes the name of the output line and the corresponding voltage value. Then extract the line name and its corresponding voltage value in the simulation result file to generate the high and low voltage related files of the circuit line.

[0029] S2. Obtain the voltage identification of the layout line, including the line name and the voltage value, wherein the line name refers to the name of the line in the layout, and the voltage value refers to the voltage value of the corresponding line in the layout.

[0030] like Figure 4 As shown, step S2, obtaining the voltage identification of the layout line, including the line name and the voltage value, specifically includes the following steps: S201. Create a layout; create the layout to be checked in the DRC tool, including the definition of lines and other physical layers.

[0031] S202, define a line voltage identification layer: in the DRC tool, define a line voltage identification layer to identify the voltage information of the line in the layout. Defining the line voltage identification layer can be completed through the graphical interface of the DRC tool or a script.

[0032] Select the appropriate voltage mark layer (mark layer / text layer) to cover the corresponding physical layer. Select the appropriate voltage mark layer. Usually, you can use "mark layer" or "text layer" to mark the voltage information of the line. These mark layers can be covered on the corresponding physical layer to display the voltage information of the line in the layout.

[0033] S203, extracting line names and voltage values ​​in the layout, and generating a voltage report for the lines in the layout; extracting the lines in the layout and identifying the line voltages according to DRC rules to generate a voltage report for the lines in the layout.

[0034] The embodiment of the present invention uses a tool or script provided by a DRC tool to extract line names and voltage values ​​in a layout. Extracting lines in a layout and identifying line voltages according to DRC rules to generate a voltage report for lines in a layout includes: Layout parsing: Parse the layout file to obtain the physical layout, connection relationship and attribute information in the layout.

[0035] Circuit Identification: DRC tools identify circuits in the layout, including their geometric features, connection relationships, and other attributes. Circuits in the layout may involve analysis of the layers, geometry, and components in the layout to identify the location and characteristics of the circuits.

[0036] Voltage Marker Extraction: Once the circuit is identified, the DRC tool extracts the voltage marker information from the layout. The voltage marker information includes analysis of the marker layer, extraction of text content, and identification of other relevant attributes.

[0037] Voltage value association: The extracted voltage identification information is associated with the corresponding voltage value. This includes analyzing the power, ground, and other voltage pins in the layout to determine the voltage value associated with each line.

[0038] Data Integration: The extracted line names and voltage values ​​are integrated into a format that can be used for report generation or subsequent analysis.

[0039] S3, Circuit and Board Figure 1 The LVS check compares the voltage markings of the lines in the layout and circuit to see if they are consistent, and generates a report on the validity of the voltage markings of the layout lines.

[0040] like Figure 5As shown, in step S3, comparing the voltage identification of the lines of the layout and the circuit to see if they are consistent, and generating a voltage identification validity report of the layout lines, specifically includes the following steps: S301. Convert the LVS intermediate result data through the EDA tool to obtain the correspondence between the layout and the circuit line name; specifically: use the tool or script provided by the EDA tool to convert the LVS intermediate result data into a format that can be analyzed, including extracting the line name, voltage identifier and layout information in the LVS intermediate result, comparing and analyzing the layout and circuit line name, and obtaining a correspondence table between the layout and the circuit line name.

[0041] S302, running the script to compare the voltage values ​​of the same line in the circuit and the layout, and generating a difference report.

[0042] Specifically include: According to the correspondence table between the layout and circuit line names, find the same line in the circuit and the layout.

[0043] The circuit simulation result and the voltage value of the same line in the layout extraction are compared through a script or program. The comparison process includes matching, sorting and comparing the two sets of voltage value data to determine whether there is a difference in the voltage value.

[0044] Generate a difference report. If there is a voltage difference between the same line in the circuit and the layout, the line and its voltage value are marked and a difference report is generated. The difference report includes the inconsistent line name, voltage value, and other related information.

[0045] S303, judging the consistency of the circuit and the layout according to the differentiation report; If the voltage of the same line in the circuit and the layout is inconsistent, it means that the layout and the circuit are inconsistent. At this time, the following processing is performed: In the voltage mark validity report generated for the layout line, fill in the voltage mark as invalid.

[0046] Analyze the difference reports to determine the causes and effects of the inconsistency. Analyzing the causes and effects of the inconsistency enables more accurate subsequent adjustments and modifications.

[0047] Modify the voltage identifiers corresponding to the layout. According to the information in the difference report, modify the inconsistent voltage identifiers corresponding to the layout. You can modify it by editing the layout file or using the tools provided by the EDA tool.

[0048] Iterate the process of steps S301-S303 until the voltage identification of all lines in the layout is consistent with the circuit. The process of iterating steps S301-S303 includes repeating the above-mentioned comparison, analysis and modification process until the voltage identification of all lines in the layout is consistent with the circuit. The iterative process can be completed by repeatedly running the script, generating a report, and making corresponding modifications and adjustments.

[0049] In this embodiment, the correctness and validity of the layout line voltage identification value is verified by the line voltage value under actual circuit working conditions, so as to avoid the situation where the line voltage is unreasonable due to the erroneous use of the identification layer or voltage value, thereby avoiding affecting the spacing requirement rule check result caused by the line voltage difference.

[0050] In this embodiment, the voltage mark of the line in the layout is ensured to be consistent with the actual voltage in the circuit by means of circuit simulation and layout extraction, which helps to find and solve the problem of inconsistency between the layout and the circuit during the design process, thereby ensuring the accuracy and reliability of the design.

[0051] In this embodiment, the voltage mark of the line in the inconsistent layout is modified according to the difference report, and the circuit and layout are iterated. Figure 1 The consistency check process is continued until the voltage identification of all lines in the layout is consistent with the circuit. This not only solves the problem of inconsistency between the layout and the circuit, but also improves the accuracy and reliability of the layout line voltage validity check.

[0052] Embodiment 2 like Figure 6 As shown, the present invention provides a system for checking the validity of voltage markings of layout lines, which is applied to a method for checking the validity of voltage markings of layout lines as in Embodiment 1, and the system includes: A data acquisition module configured to acquire line voltage information data of the circuit and the layout, wherein the line voltage information data includes line names and voltage values; A data processing module is configured to compare and analyze the line names and voltage values ​​of the circuits and layouts collected by the data collection module; The data optimization module is configured to optimize the inconsistent data after comparison in the data processing module, specifically to modify the voltage mark corresponding to the layout until the voltage marks of all lines in the layout are consistent with the circuit.

[0053] Embodiment 3 like Figure 7 As shown, the present invention also provides an electronic device 2, including a processor 21 and a memory 22, the memory 22 is used to store computer program code, the computer program code includes computer instructions, when the processor 21 executes the computer instructions, the electronic device executes a CDM ESD risk analysis method for an internal circuit of a SoC of the above embodiment.

[0054] The electronic device 2 also includes an input device 24 and an output device 23. The processor 21, the memory 22, the input device 24 and the output device 23 are coupled via a connector, and the connector includes various interfaces, transmission lines or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0055] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0056] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), which is used for related instructions and data.

[0057] The input device 24 is used to input data and / or signals, and the output device 23 is used to output data and / or signals. The output device 23 and the input device 24 can be independent devices or an integrated device.

[0058] In the several embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, the indirect coupling or communication connection of the modules can be electrical, mechanical or other forms.

[0059] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0060] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0061] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, read-only memory), random access memory (RAM, random access memory), disk or optical disk and other media that can store program code.

[0062] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for checking the validity of voltage marking of a layout line, characterized by: Includes steps: Get the line voltage of the circuit, including line name and voltage value; Get the layout line voltage identification, including line name and voltage value; Compare the line voltage identification on the layout and the line voltage of the circuit to see if they are consistent, and generate a report on the validity of the voltage identification of the layout line.

2. A method for checking the validity of voltage markings of layout lines according to claim 1, characterized in that: The obtaining of the voltage identification of the circuit line specifically includes: Create a circuit; Set up test incentives; Run the simulation and obtain the simulation results; Save the line names and voltage values ​​in the circuit from the simulation results.

3. A method for checking the validity of voltage markings of layout lines according to claim 2, characterized in that: The setting of the test stimulus is to create the test stimulus according to the actual working condition of the circuit, including designing the reference voltage of all lines in the circuit; the simulation result export format is a text file or a spreadsheet.

4. A method for checking the validity of voltage markings of layout lines according to claim 1, characterized in that: The obtaining of the voltage mark of the layout line specifically includes: Create a layout; Define the line voltage identification layer; select the voltage identification layer to cover the corresponding physical layer; Extract line names and voltage values ​​in the layout and generate voltage reports for the lines in the layout.

5. A method for checking the validity of voltage markings of layout lines according to claim 4, characterized in that: Generating a voltage report for a line in the layout includes extracting a line in the layout according to a DRC rule and identifying a line voltage to generate a voltage report for the line in the layout, specifically including: Layout parsing: parse the layout file to obtain the physical layout, connection relationship and attribute information in the layout; Circuit identification: DRC tools identify circuits in the layout, including their geometric features, connection relationships, and other attributes; Voltage marker extraction: The DRC tool extracts voltage marker information from the layout.

6. A method for checking the validity of voltage markings of layout lines according to claim 5, characterized in that: After the voltage mark is extracted, the method further includes: Voltage value association: The extracted voltage identification information is associated with the corresponding voltage value; Data Integration: Extracted line names and voltage values ​​are integrated into a format that can be used for report generation or subsequent analysis.

7. A method for checking the validity of voltage markings of layout lines according to claim 1, characterized in that: Compare the voltage marks of the lines in the layout and circuit to see if they are consistent, and generate a report on the validity of the voltage marks of the layout lines. The specific steps include: S301, converting LVS intermediate result data through EDA tools to obtain the corresponding relationship between the layout and the circuit line name; S302, running the script to compare the voltage values ​​of the same line in the circuit and the layout, and generating a difference report; S303. Determine the consistency of the circuit and the layout according to the differentiation report.

8. A method for checking the validity of voltage markings of layout lines according to claim 7, characterized in that: In step S303, if the layout and the circuit are inconsistent, the following steps are performed: In the voltage mark validity report generated for the layout line, fill in the voltage mark as invalid; Analyze discrepancies in reporting to determine causes and impacts of inconsistencies; Modify the voltage mark corresponding to the layout.

9. A method for checking the validity of voltage markings of layout lines according to claim 8, characterized in that: If the layout and the circuit are inconsistent, it also includes iterative steps S301-S303 until the voltage identifiers of all lines in the layout are consistent with the circuit.

10. A system for checking the validity of voltage markings of layout lines, characterized in that: The system is applied to a method for checking the validity of voltage markings of layout lines as described in any one of claims 1 to 9; the system comprises: A data acquisition module configured to acquire line voltage information data of the circuit and the layout, wherein the line voltage information data includes line names and voltage values; A data processing module is configured to compare and analyze the line names and voltage values ​​of the circuits and layouts collected by the data collection module; The data optimization module is configured to optimize the inconsistent data after comparison in the data processing module, specifically to modify the voltage mark corresponding to the layout until the voltage marks of all lines in the layout are consistent with the circuit.

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