Display panel, driving method thereof, and display device

Abstract

The application provides a display panel and a driving method thereof and a display device, and relates to the technical field of display, and is used for improving the brightness consistency of the display panel. A first scanning driving unit is electrically connected with a first scanning control end of a first pixel driving circuit and a second pixel driving circuit respectively; a working period of the pixel driving circuit comprises a data writing period; within the display time of one frame of picture, the data writing period of the first pixel driving circuit is located before the data writing period of the second pixel driving circuit; and when the first pixel driving circuit and the second pixel driving circuit receive the same data voltage, the potential V N11 of a first node in the first pixel driving circuit is greater than the potential V N12 of a first node in the second pixel driving circuit after the respective data writing periods.

Description

[0001] This application is a divisional application of application number 202210757542.8, filed on June 29, 2022, entitled "Display Panel and Driving Method Thereof, Display Device". [Technical Field]

[0002] This invention relates to the field of display technology, and in particular to a display panel and its driving method, and a display device. [Background Technology]

[0003] Organic light-emitting diode (OLED) display panels have gradually become the mainstream display technology for mobile phones, televisions, computers and other monitors due to their characteristics such as self-illumination, fast response, wide color gamut, wide viewing angle and high brightness.

[0004] OLED display panels consist of multiple sub-pixels located in the display area and driving circuitry located in the non-display area to illuminate the sub-pixels. Currently, display panels suffer from issues such as excessively large non-display areas and poor brightness uniformity across the display area. [Summary of the Invention]

[0005] In view of this, embodiments of the present invention provide a display panel and its driving method and display device, for reducing the width of the non-display area of ​​the display panel and improving the brightness uniformity of the display panel.

[0006] On one hand, embodiments of the present invention provide a display panel, characterized in that it includes:

[0007] Multiple pixel groups, each pixel group comprising B pixel rows, where B ≥ 2 and B is an integer; each pixel row comprising multiple pixel driving circuits, each pixel driving circuit comprising a driving transistor, a data writing control terminal, and a first scan control terminal; the control electrode of the driving transistor is electrically connected to a first node, and the first electrode of the driving transistor is electrically connected to a second node;

[0008] The first scan driving unit is electrically connected to multiple first scan control terminals in the same pixel group;

[0009] The working cycle of the pixel driving circuit includes a data writing period. During the data writing period, the data writing control terminal receives a valid level, and the first scan driving unit provides a valid level to the first scan control terminal.

[0010] The plurality of pixel driving circuits in the same pixel group include a first pixel driving circuit and a second pixel driving circuit. During the display time of one frame, the data writing period of the first pixel driving circuit is before the data writing period of the second pixel driving circuit. Furthermore, when the first pixel driving circuit and the second pixel driving circuit receive the same data voltage, after the data writing period, the potential of the first node in the first pixel driving circuit is V. N11 The potential of the first node in the second pixel driving circuit is V. N12 V N11 >V N12 .

[0011] On the other hand, embodiments of the present invention provide a display panel, including:

[0012] Multiple pixel groups, each pixel group comprising B pixel rows, where B ≥ 2 and B is an integer; each pixel row comprising multiple pixel driving circuits, each pixel driving circuit comprising a driving transistor, a data writing control terminal, and a first scan control terminal; the control electrode of the driving transistor is electrically connected to a first node, and the first electrode of the driving transistor is electrically connected to a second node;

[0013] The first scan driving unit is electrically connected to multiple first scan control terminals in the same pixel group;

[0014] The working cycle of the pixel driving circuit includes a data writing period. During the data writing period, the data writing control terminal receives a valid voltage level, and the first scanning driving unit provides a valid voltage level. The plurality of pixel driving circuits in the same pixel group include a first pixel driving circuit and a second pixel driving circuit. Within the display time of one frame, the data writing period of the first pixel driving circuit precedes the data writing period of the second pixel driving circuit. Furthermore, when the first pixel driving circuit and the second pixel driving circuit receive the same data voltage, after the data writing period, the leakage current velocity of the first node in the first pixel driving circuit is v. N11 The leakage current velocity of the first node in the second pixel driving circuit is v. N12 v N11 <v N12 .

[0015] In another aspect, embodiments of the present invention provide a driving method for a display panel, the display panel comprising:

[0016] Multiple pixel groups, each pixel group comprising B pixel rows, where B ≥ 2 and B is an integer; each pixel row comprising multiple pixel driving circuits, each pixel driving circuit comprising a driving transistor, a data writing control terminal, and a first scan control terminal; the control electrode of the driving transistor is electrically connected to a first node, and the first electrode of the driving transistor is electrically connected to a second node;

[0017] The first scan driving unit is electrically connected to multiple first scan control terminals in the same pixel group;

[0018] The working cycle of the pixel driving circuit includes a data writing period. During the data writing period, the data writing control terminal receives a valid level, and the first scanning driving unit provides a valid level. The plurality of pixel driving circuits in the same pixel group include a first pixel driving circuit and a second pixel driving circuit.

[0019] The driving method includes:

[0020] Within the display time of one frame, the data writing period of the first pixel driving circuit is positioned before the data writing period of the second pixel driving circuit; and, when the first pixel driving circuit and the second pixel driving circuit receive the same data voltage, after the data writing period, the potential of the first node in the first pixel driving circuit is V. N11 The potential of the first node in the second pixel driving circuit is V. N12 V N11 >V N12 .

[0021] In another aspect, embodiments of the present invention provide a driving method for a display panel, the display panel comprising:

[0022] Multiple pixel groups, each pixel group comprising B pixel rows, where B ≥ 2 and B is an integer; each pixel row comprising multiple pixel driving circuits, each pixel driving circuit comprising a driving transistor, a data writing control terminal, and a first scan control terminal; the control electrode of the driving transistor is electrically connected to a first node, and the first electrode of the driving transistor is electrically connected to a second node;

[0023] The first scan driving unit is electrically connected to multiple first scan control terminals in the same pixel group;

[0024] The working cycle of the pixel driving circuit includes a data writing period. During the data writing period, the data writing control terminal receives a valid level, and the first scanning driving unit provides a valid level. The plurality of pixel driving circuits in the same pixel group include a first pixel driving circuit and a second pixel driving circuit.

[0025] The driving method includes:

[0026] Within the display time of one frame, the data writing period of the first pixel driving circuit is positioned before the data writing period of the second pixel driving circuit; and, when the first pixel driving circuit and the second pixel driving circuit receive the same data voltage, after the data writing period, the leakage current velocity of the first node in the first pixel driving circuit is v. N11 The leakage current velocity of the first node in the second pixel driving circuit is v. N12 v N11 <v N12 .

[0027] In another aspect, embodiments of the present invention provide a display device including the aforementioned display panel.

[0028] The display panel and its driving method and display device provided in the embodiments of the present invention can reduce the number of first scanning driving units required by the display panel by electrically connecting the first scanning driving unit to multiple first scanning control terminals in the same pixel group, thereby reducing the space occupied by the first scanning driving circuit in the non-display area and improving the screen ratio of the display panel.

[0029] Furthermore, when the first pixel driving circuit and the second pixel driving circuit receive the same data voltage, after the respective data writing period of the first pixel driving circuit and the second pixel driving circuit, that is, when their respective data writing transistors are turned off, the embodiment of the present invention enables V... N11 >V N12 It can compensate for or even eliminate the difference in leakage time between the first node of the first pixel driving circuit and the first node of the second pixel driving circuit. After entering the light emission stage, it can make the potential of the first node of the first pixel driving circuit and the first node of the second pixel driving circuit tend to be consistent, which is beneficial to improve the brightness consistency of the light emission elements driven by the two. [Attached Image Description]

[0030] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of a portion of a display panel provided in an embodiment of the present invention;

[0032] Figure 2 A schematic diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0033] Figure 3 A timing diagram of a first pixel driving circuit and a second pixel driving circuit provided in an embodiment of the present invention;

[0034] Figure 4 A schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0035] Figure 5 for Figure 4 Corresponding sequence diagram;

[0036] Figure 6 A schematic diagram of a second scanning circuit provided in an embodiment of the present invention;

[0037] Figure 7 A circuit diagram of a second scanning driving unit provided in an embodiment of the present invention;

[0038] Figure 8 for Figure 6 A corresponding sequence diagram;

[0039] Figure 9 This is a connection diagram of another second scan driving circuit provided in an embodiment of the present invention;

[0040] Figure 10 for Figure 9 Corresponding sequence diagram;

[0041] Figure 11 This is a connection diagram of another second scanning drive circuit provided in an embodiment of the present invention;

[0042] Figure 12 for Figure 11 A corresponding sequence diagram;

[0043] Figure 13 for Figure 6 Another corresponding timing diagram;

[0044] Figure 14 This is a connection diagram of another second scanning drive circuit provided in an embodiment of the present invention;

[0045] Figure 15 A schematic diagram illustrating the connection relationship between a first pixel driving circuit and a second pixel driving circuit, provided in an embodiment of the present invention;

[0046] Figure 16 A schematic diagram of a portion of another display panel provided in an embodiment of the present invention;

[0047] Figure 17 A circuit diagram of a light-emitting driving unit provided in an embodiment of the present invention;

[0048] Figure 18 This is a connection diagram of a light-emitting driving circuit provided in an embodiment of the present invention;

[0049] Figure 19 This is a schematic diagram of a driving method for a display panel provided in an embodiment of the present invention;

[0050] Figure 20 A schematic diagram of another display panel driving method provided in an embodiment of the present invention.

[0051] Figure 21 This is a schematic diagram of a display device provided in an embodiment of the present invention.

Detailed Implementation Methods

[0052] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0053] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0054] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0055] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0056] It should be understood that although the terms "first," "second," etc., may be used to describe pixel driving circuits in the embodiments of the present invention, these pixel driving circuits should not be limited to these terms. These terms are only used to distinguish pixel driving circuits located in different pixel rows from one another. For example, without departing from the scope of the embodiments of the present invention, a first pixel driving circuit may also be referred to as a second pixel driving circuit, and similarly, a second pixel driving circuit may also be referred to as a first pixel driving circuit.

[0057] This invention provides a display panel, such as... Figure 1 As shown, Figure 1This is a schematic diagram of a portion of a display panel according to an embodiment of the present invention. The display panel includes a display area AA and a non-display area NA. The display area AA includes a plurality of pixel groups 1 arranged along a first direction h1. Each pixel group 1 includes B pixel rows 10 arranged along the first direction h1, where B ≥ 2 and B is an integer. Each pixel row 10 includes a plurality of pixel driving circuits 100 arranged along a second direction h2. Figure 1 As shown in the diagram, B=2, that is, a pixel group 1 includes two pixel rows 10, one pixel row 10 includes a first pixel driving circuit 101, and the other pixel row 10 includes a second pixel driving circuit 102.

[0058] like Figure 2 As shown, Figure 2This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention. The pixel driving circuit 100 includes a driving transistor M0, a data writing transistor M11, a threshold compensation transistor M12, a first node reset transistor M13, a light-emitting element reset transistor M14, a second light-emitting control transistor M15, a first light-emitting control transistor M16, and a storage capacitor Cst. The control electrode of the driving transistor M0 is electrically connected to the first node N11, the first electrode of the driving transistor M0 is electrically connected to the second node N12, and the second electrode of the driving transistor M0 is electrically connected to the third node N13. The control electrode of the data writing transistor M11 is electrically connected to the data writing control terminal S1, the first electrode of the data writing transistor M11 is electrically connected to the data voltage terminal Vdata, and the second electrode of the data writing transistor M11 is electrically connected to the second node N12. The control electrode of the threshold compensation transistor M12 is electrically connected to the first scan control terminal S21, the first electrode of the threshold compensation transistor M12 is electrically connected to the third node N13, and the second electrode of the threshold compensation transistor M12 is electrically connected to the first node N11. The control electrode of the first node reset transistor M13 is electrically connected to the second scan control terminal S22. The first electrode of the first node reset transistor M13 is electrically connected to the first reset terminal Ref1, and the second electrode of the first node reset transistor M13 is electrically connected to the first node N11. The control electrode of the light-emitting element reset transistor M14 is electrically connected to the data write control terminal S1. The first electrode of the light-emitting element reset transistor M14 is electrically connected to the second reset terminal Ref2, and the second electrode of the light-emitting element reset transistor M14 is electrically connected to the fourth node N14. The control electrode of the first light-emitting control transistor M16 is electrically connected to the light-emitting control terminal E. The first electrode of the first light-emitting control transistor M16 is electrically connected to the third node N13, and the second electrode of the first light-emitting control transistor M16 is electrically connected to the fourth node N14. The control electrode of the second light-emitting control transistor M15 is electrically connected to the light-emitting control terminal E. The first electrode of the second light-emitting control transistor M15 is electrically connected to the first power supply voltage terminal PVDD, and the second electrode of the second light-emitting control transistor M15 is electrically connected to the second node N12. The first plate of the storage capacitor Cst is electrically connected to the first node N11, and the second plate is electrically connected to the first power supply voltage terminal PVDD. One electrode of the light-emitting element 200 is electrically connected to the fourth node N14, and the other electrode is electrically connected to the second power supply voltage terminal PVEE.

[0059] For example, the first node reset transistor M13 and threshold compensation transistor M12 can be oxide transistors, such as indium gallium zinc oxide (IGZO) transistors, to give them a smaller off-state leakage current and improve the potential stability of the first node N11. Specifically, when the display panel is displayed in low-frequency mode, the potential of the first node N11 needs to be maintained for a longer period. Using indium gallium zinc oxide transistors for the first node reset transistor M13 and threshold compensation transistor M12, which are electrically connected to the first node N11, can ensure the brightness uniformity of the low-frequency display.

[0060] When displaying on this display panel, combined with Figure 2 and Figure 3 As shown, Figure 3 The present invention provides a timing diagram of a first pixel driving circuit and a second pixel driving circuit. The working process of the first pixel driving circuit 101 and the second pixel driving circuit 102 both include a first reset period TR1, a data writing period, and a light emission period TE. Figure 3 In this context, TW_101 represents the data writing period of the first pixel driving circuit 101, and TW_102 represents the data writing period of the second pixel driving circuit 102.

[0061] During the first reset period TR1, the second scan control terminal S22 controls the first node reset transistor M13 of the first pixel driving circuit 101 and the second pixel driving circuit 102 to be turned on, and the first reset terminal Ref1 resets the first node N11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 through the first node reset transistor M13.

[0062] During the data writing period TW_101 of the first pixel driving circuit 101, the data writing control terminal S1 of the first pixel driving circuit 101 controls the data writing transistor M11 of the first pixel driving circuit 101 to turn on, and the data voltage terminal Vdata of the first pixel driving circuit 101 provides the data voltage V data The data is written to the second node N12 of the first pixel driving circuit 101 by the data writing transistor M11. The driving transistor M0 of the first pixel driving circuit 101 is turned on. During this stage, the first scan control terminal S21 of the first pixel driving circuit 101 controls the threshold compensation transistor M12 of the first pixel driving circuit 101 to turn on. In this process, the potential of the first node N11 of the first pixel driving circuit 101 changes continuously until the potential V of the first node N11 of the first pixel driving circuit 101 reaches a certain value. N11 Change to V N11 =Vdata -|V th1 |,V th1 The threshold voltage of the driving transistor M0 of the first pixel driving circuit 101.

[0063] During the data writing period TW_102 of the second pixel driving circuit 102, the data writing control terminal S1 of the second pixel driving circuit 102 controls the data writing transistor M11 of the second pixel driving circuit 102 to be turned on, and the data voltage terminal Vdata of the second pixel driving circuit 102 provides the data voltage V data The data is written to the second node N12 of the second pixel driving circuit 102 via the data writing transistor M11. The driving transistor M0 of the second pixel driving circuit 102 is turned on. During this stage, the first scan control terminal S21 of the second pixel driving circuit 102 controls the threshold compensation transistor M12 of the second pixel driving circuit 102 to turn on. During this process, the potential of the first node N11 of the second pixel driving circuit 102 continuously changes until the potential V of the first node N11 of the second pixel driving circuit 102 reaches a certain value. N11 Change to V N11 =V data -|V th2 |,V th2 The threshold voltage of the driving transistor M0 of the second pixel driving circuit 102.

[0064] During the light-emitting period TE, the second light-emitting control transistor M15, the first light-emitting control transistor M16, and the driving transistor M0 of the first pixel driving circuit 101 and the second pixel driving circuit 102 are turned on, while the first node reset transistor M13, the data writing transistor M11, and the threshold compensation transistor M12 are all turned off. The current path between the first power supply voltage terminal PVDD and the second power supply voltage terminal PVEE is turned on, and the light-emitting element 200, which is electrically connected to the first pixel driving circuit 101 and the second pixel driving circuit 102, is lit.

[0065] like Figure 1 As shown, the display panel also includes a first scanning drive circuit 21, a second scanning drive circuit 22, and a light-emitting drive circuit 23.

[0066] The first scan drive circuit 21 includes multiple cascaded first scan drive units 210, and the first scan drive units 210 are electrically connected to the first scan control terminals S21 of multiple pixel rows 10 belonging to the same pixel group 1.

[0067] The second scan driving circuit 22 includes multiple cascaded second scan driving unit groups 20, each group comprising B cascaded second scan driving units 220. Multiple cascaded second scan driving unit groups 20 mean that the output terminal of the last stage second scan driving unit 220 in the previous group is electrically connected to the input terminal of the first stage second scan driving unit 220 in the current group. Each second scan driving unit group 20 corresponds to a pixel group 1, and the B cascaded second scan driving units 220 in the same group are electrically connected to B pixel rows 10 in the same pixel group 1. The second scan driving units 220 are electrically connected to the data write control terminal S1 of the pixel driving circuit 100. When the display panel is operating, each stage of the second scan driving unit 220 outputs a valid level signal sequentially, causing each pixel row 10 to sequentially perform data write operations.

[0068] Taking multiple pixel driving circuits 100 in the same pixel group 1, including the first pixel driving circuit 101 and the second pixel driving circuit 102 located in different pixel rows, as an example, within the display time of one frame, such as Figure 3 As shown, the effective level of the first scan control terminal S21 of the first pixel driving circuit 101 and the second pixel driving circuit 102 covers the data writing period TW_101 of the first pixel driving circuit 101 and the data writing period TW_102 of the second pixel driving circuit 102. The data writing period TW_101 of the first pixel driving circuit 101 is located before the data writing period TW_101 of the second pixel driving circuit 102. When the first pixel driving circuit 101 and the second pixel driving circuit 102 receive the same data voltage, after the data writing period TW_101 of the first pixel driving circuit 101, the potential of the first node N11 in the first pixel driving circuit 101 is V. N11 After the data writing period TW_102 of the second pixel driving circuit 102, the potential of the first node N11 in the second pixel driving circuit 102 is V. N12 In this embodiment of the invention, V N11 >V N12 .

[0069] The display panel provided in this embodiment of the invention can reduce the number of first scan driving units 210 required by the display panel by electrically connecting the first scan driving unit 210 to multiple first scan control terminals S21 in the same pixel group 1, thereby reducing the space occupied by the first scan driving circuit 21 in the non-display area NA, which is beneficial to improving the screen ratio of the display panel.

[0070] When the second pixel driving circuit 102 performs a data write operation, that is, during the data write period TW_102 of the corresponding second pixel driving circuit 102, the threshold compensation transistor M12 of the first pixel driving circuit 101 remains in the on state. Since the fourth node N14 and the second reset terminal Ref2 are electrically connected through the light-emitting element reset transistor M14, the second reset terminal Ref2 provides a low-level reset signal. Therefore, during this period, the first node N11 of the first pixel driving circuit 101 will leak current to the fourth node N14 through the third node N13 and the first light-emitting control transistor M16 until the threshold compensation transistor M12 of the first pixel driving circuit 101 is turned off. The time between the data write transistor M11 of the pixel driving circuit 100 being turned off and the threshold compensation transistor M12 being turned off is defined as the leakage time of the first node N1. As mentioned above, the effective level of the first scan control terminal S21 of the first pixel driving circuit 101 and the second pixel driving circuit 102 covers the data writing period TW_101 and the data writing period TW_102. The data writing period TW_101 of the first pixel driving circuit 101 is located before the data writing period TW_101 of the second pixel driving circuit 102. Therefore, the leakage time of the first node N11 in the first pixel driving circuit 101 is greater than the leakage time of the first node N11 in the second pixel driving circuit 102.

[0071] When the first pixel driving circuit 101 and the second pixel driving circuit 102 receive the same data voltage, after the respective data writing period of the first pixel driving circuit 101 and the second pixel driving circuit 102, that is, when their respective data writing transistors M11 are turned off, the embodiment of the present invention enables V... N11 >V N12 This can compensate for or even eliminate the difference in leakage time between the first node N11 of the first pixel driving circuit 101 and the first node N11 of the second pixel driving circuit 102. After entering the light-emitting stage, the potential of the first node N11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 can be made to be consistent, which is beneficial to improving the brightness consistency of the light-emitting elements 200 driven by the two.

[0072] For example, such as Figure 3 As shown, the operation of the first pixel driving circuit 101 and the second pixel driving circuit 102 also includes a second reset period TR2. During the second reset period TR2, combined with... Figure 2As shown, the threshold compensation transistor M12 and the first node reset transistor M13 of the first pixel driving circuit 101 and the second pixel driving circuit 102 are both turned on. The first reset terminal Ref1 can reset the third node N13 through the threshold compensation transistor M12 and the first node reset transistor M13, so as to adjust the bias state of the driving transistor M0 of the first pixel driving circuit 101 and the second pixel driving circuit 102.

[0073] For example, such as Figure 1 As shown, the second scan control terminal S22 in the pixel driving circuit 100 can be electrically connected to the previous first scan driving unit 210. That is, in addition to being electrically connected to the first scan control terminal S21 of the multiple pixel driving circuits 100 in the corresponding pixel group 1, the first scan driving unit 210 can also be electrically connected to the second scan control terminal S22 of the multiple pixel driving circuits 100 in the next pixel group 1.

[0074] For example, such as Figure 4 and Figure 5 As shown, Figure 4 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention. Figure 5 for Figure 4 According to the corresponding timing diagram, the pixel driving circuit 100 also includes an adjustment transistor M11*. The control electrode of the adjustment transistor M11* is electrically connected to the adjustment control terminal S1*, the first electrode of the adjustment transistor M11* is electrically connected to the adjustment terminal DVH, and the second electrode of the adjustment transistor M11* is electrically connected to the second node N12. Figure 5 The other structures besides the regulating transistor M11* can be arranged according to Figure 2 The corresponding structures in the pixel driving circuit 100 shown are configured, and the embodiments of the present invention will not be described in detail here.

[0075] Combination Figure 5 As shown, the operation of the pixel driving circuit 100 also includes a first bias adjustment stage TD1 and a second bias adjustment stage TD2. The first bias adjustment stage TD1 is located before the first reset period TR1, and the second bias adjustment stage TD2 is located after the corresponding data writing period of the pixel driving circuit 100. During the first bias adjustment stage TD1 and the second bias adjustment stage TD2, the pixel driving circuit 100 is in a non-light-emitting state. During the first bias adjustment stage TD1 and the second bias adjustment stage TD2, the adjustment terminal DVH writes a bias adjustment signal to the second node N12 through the adjustment transistor M11*, respectively, to adjust the bias state of the driving transistor M0 in this stage.

[0076] Optionally, in this embodiment of the invention, during the display time of one frame, the conduction time of the data writing transistor M11 in the first pixel driving circuit 101 is shorter than the conduction time of the data writing transistor M11 in the second pixel driving circuit 102. This setting allows the threshold compensation time of the first pixel driving circuit 101 to be shorter than the threshold compensation time of the second pixel driving circuit 102, thus preventing incomplete threshold compensation in the first pixel driving circuit 101. Since the potential of the first node N11 satisfies V after threshold compensation by the pixel driving circuit... N11 =V data -|V th |。V th When the data write transistor M11 of the corresponding pixel driving circuit is turned off, the threshold voltage of the driving transistor written to the first node N11 of the pixel driving circuit is used. Therefore, by adopting the method provided in the embodiment of the present invention, after each data write transistor M11 is turned off, the potential of the first node N11 in the first pixel driving circuit 101 can be made higher than the potential of the first node N11 in the second pixel driving circuit 102, thereby compensating for the difference in leakage current time between the two.

[0077] like Figure 6 , Figure 7 and Figure 8 As shown, Figure 6 This is a schematic diagram of a second scanning circuit provided in an embodiment of the present invention. Figure 7 This is a circuit diagram of a second scanning driving unit provided in an embodiment of the present invention. Figure 8 for Figure 6According to one corresponding timing diagram, the second scan driving unit 220 includes a first output transistor M21, a second output transistor M22, a third transistor M23, a fourth transistor M24, a fifth transistor M25, a sixth transistor M26, a seventh transistor M27, an eighth transistor M28, a first capacitor C21, and a second capacitor C22. The first terminal of the first output transistor M21 is electrically connected to the first clock terminal CK1, and the second terminal of the first output transistor M21 is electrically connected to the output terminal OUT1 of the second scan driving unit 220. The control terminal of the first output transistor M21 is electrically connected to the first node N21. The first terminal of the second output transistor M22 is electrically connected to the second level terminal VGH1, and the second terminal of the second output transistor M22 is electrically connected to the output terminal OUT1 of the second scan driving unit 220. The control terminal of the second output transistor M22 is electrically connected to the second node N22. The control terminals of the fifth transistor M25 and the fourth transistor M24 are both electrically connected to the second clock terminal XCK1. The first terminal of the fifth transistor M25 is electrically connected to the input terminal IN1. The second terminal of the fifth transistor M25 is electrically connected to the control terminal of the seventh transistor M27, the first terminal of the sixth transistor M26, and the first terminal of the third transistor M23. The first terminal of the seventh transistor M27 is electrically connected to the second clock terminal XCK1. The second terminal of the seventh transistor M27 is electrically connected to the control terminal of the eighth transistor M28. The control terminal of the sixth transistor M26 is electrically connected to the first clock terminal CK1. The second terminal of the sixth transistor M26 is electrically connected to the first terminal of the eighth transistor M28. The second terminal of the eighth transistor M28 is electrically connected to the second level terminal VGH1. The first terminal of the fourth transistor M24 is electrically connected to the first level terminal VGL1. The second terminal of the fourth transistor M24 is electrically connected to the control terminal of the second output transistor M22. The control terminal of the third transistor M23 is electrically connected to the first level terminal VGL1. The second terminal of the third transistor M23 is electrically connected to the control terminal of the first output transistor M21. In the second scan drive circuit, the output terminal OUT1 of each stage of the second scan drive unit is electrically connected to the control electrode of the data writing transistor M11 of the corresponding pixel drive circuit 100.

[0078] When the first output transistor M21 of the second scan driving unit 220 is turned on, the signal of the first clock terminal CK1 is output to the output terminal OUT1. The signal received by the first clock terminal CK1 is a pulse signal with an effective level that enables the data write transistor M11 in the pixel driving circuit 100 to turn on. For example, when the data write transistor M11 is a P-type transistor, the effective level is a low-level signal VGL. When the data write transistor M11 is an N-type transistor, the effective level is a high-level signal VGH.

[0079] In this embodiment of the invention, the display panel further includes Class B clock signal lines, which are electrically connected to the first clock terminal CK1 of the Class B second scan driving unit 220 in the same second scan driving unit group 20. Each type of clock signal line is used to transmit periodic pulse signals. The pulse signals include an effective level that controls the data writing transistor M11 of the pixel driving circuit 100 to turn on. In this embodiment of the invention, the effective levels of any two Class B clock signal lines are staggered. Furthermore, the pulse widths of the effective levels transmitted by the Class B clock signal lines are different. According to the order in which the Class B clock signal lines output effective levels, the pulse widths of the effective levels output by the Class B clock signal lines increase sequentially.

[0080] For example, the B cascaded second scan driving units 220 in the same second scan driving unit group 20 include at least an m-th level second scan driving unit 220_m and an n-th level second scan driving unit 220_n. The output terminal of the m-th level second scan driving unit 220_m is electrically connected to the data write control terminal S1 of the first pixel driving circuit 101, and the output terminal of the n-th level second scan driving unit 220_n is electrically connected to the data write control terminal S1 of the second pixel driving circuit 102. Correspondingly, the B-type clock signal lines included in the display panel include at least a m-th level clock signal line and an n-th level clock signal line. The m-th level clock signal line is electrically connected to the first clock terminal CK1 of the m-th level second scan driving unit 220_m, and the n-th level clock signal line is electrically connected to the first clock terminal CK1 of the n-th level second scan driving unit 220_n. The m-th level second scan driving unit 220_m outputs an effective level first, and the n-th level second scan driving unit 220_n outputs an effective level later, so that within the display time of one frame, the first pixel driving circuit 101 writes data first, and the second pixel driving circuit 102 writes data later. In this embodiment of the invention, the pulse width of the effective level of the m-th type clock signal line is less than the pulse width of the effective level of the n-th type clock signal line. Where m and n are both integers, and 1≤m<n≤B. For example, when B=2, m=1, n=2; when B=3, m=1, n=2; or, m=1, n=3; or, m=2, n=3.

[0081] Taking B=2 as an example, such as Figure 6As shown, two cascaded second scan drive unit groups 20 are used as an example. These two cascaded second scan drive unit groups 20 correspond to the first and second second scan drive unit groups 20 of the display panel, respectively. The input terminal IN1 of the first-stage second scan drive unit 220_1 in the first scan drive unit group 20 is electrically connected to the scan frame start signal line LS1. The output terminal OUT1 of the second-stage second scan drive unit 220_2 in the first second scan drive unit group 20 is connected to the input terminal IN1 of the first-stage second scan drive unit (corresponding to the third-stage second scan drive unit 220_3 of the display panel) in the second second scan drive unit group 20.

[0082] Taking the two-stage second scan drive unit in the first scan drive unit group 20 as an example, the first clock terminal CK1 of the first-stage second scan drive unit 220_1 is electrically connected to the first type of clock signal line LC11; the first clock terminal CK1 of the second-stage second scan drive unit 220_2 is electrically connected to the second type of clock signal line LC12. Combined with... Figure 8 As shown, the pulse width e1 of the effective level transmitted by the first type of clock signal line LC11 is smaller than the pulse width f1 of the effective level transmitted by the second type of clock signal line LC12.

[0083] In this embodiment of the invention, by connecting different second scan driving units 220 in the same second scan driving unit group 20 to different types of clock signal lines, and by increasing the pulse width of the effective level transmitted by each type of clock signal line in the order of the effective level output by each type of clock signal line, the conduction time of the data writing transistor M11 in different pixel rows 10 in the same pixel group 1 can be different, thereby balancing the difference in leakage current time of the first node N11 of different pixel driving circuits 100 in the same pixel group 1.

[0084] In specific implementation, the pulse width difference of the effective level transmitted by various clock signal lines can be adjusted according to the leakage current of the first node N11 of different pixel driving circuits in the same pixel group. This embodiment of the invention does not limit this.

[0085] For example, the first type of clock signal line in the aforementioned type B clock signal lines, in addition to being electrically connected to the first clock terminal CK1 of the first-level second scan drive unit 220 in the second scan drive unit group 20, can also be electrically connected to the second clock terminal XCK1 of the second-level B-stage second scan drive unit 220 in the same second scan drive unit group 20. For the i-th type of clock signal line in the aforementioned type B clock signal lines, where i is an integer and 2≤i≤B, in addition to being electrically connected to the first clock terminal CK1 of the i-th-stage second scan drive unit 220 in the second scan drive unit group 20, it can also be electrically connected to the second clock terminal XCK1 of the (i-1)-th-stage second scan drive unit 220 in the same second scan drive unit group 20. This configuration, while ensuring the normal operation of the second scan drive circuit 22, helps to reduce the number of required signal lines.

[0086] Taking B=2 as an example, such as Figure 6 As shown, the first type of clock signal line LC11 is electrically connected to the first clock terminal CK1 of the first-stage second scan drive unit 220_1, and also to the second clock terminal XCK1 of the second-stage second scan drive unit 220_2 in the same second scan drive unit group 20. The second type of clock signal line LC12 is electrically connected to the first clock terminal CK1 of the second-stage second scan drive unit 220_2, and also to the second clock terminal XCK1 of the first-stage second scan drive unit 220_1 in the same second scan drive unit group 20.

[0087] Taking B=3 as an example, such as Figure 9 and Figure 10 As shown, Figure 9 This is a connection diagram of another second scan driving circuit provided in an embodiment of the present invention. Figure 10 for Figure 9 The corresponding timing diagram, illustrated by two second scan drive unit groups 20, shows that the display panel includes three types of clock signal lines. Figure 9 and Figure 10These are labeled LC11, LC12, and LC13, respectively. The pulse width e2 of the effective level transmitted by the first type of clock signal line LC11 is smaller than the pulse width f2 of the effective level transmitted by the second type of clock signal line LC12. The pulse width f2 of the effective level transmitted by the second type of clock signal line LC12 is smaller than the pulse width f3 of the effective level transmitted by the third type of clock signal line LC13. For the first second scan drive unit group 20, the first type of clock signal line LC11 is electrically connected to the first clock terminal CK1 of the first-stage second scan drive unit 220_1 and also electrically connected to the second clock terminal XCK1 of the third-stage second scan drive unit 220_3. The second type of clock signal line LC12 is electrically connected to the first clock terminal CK1 of the second-stage second scan drive unit 220_2 and also electrically connected to the second clock terminal XCK1 of the first-stage second scan drive unit 220_1. In addition to being electrically connected to the first clock terminal CK1 of the third-level second scan drive unit 220_3, the third-class clock signal line LC13 is also electrically connected to the second clock terminal XCK1 of the second-level second scan drive unit 220_2.

[0088] For example, the first clock terminal CK1 of the corresponding level of the second scan drive unit 220 in different second scan drive unit groups 20 is connected to the same clock signal line. Figure 6 For example, the first type of clock signal line LC11 is electrically connected to the first clock terminal CK1 of the first level second scan drive unit 220_1 in the first second scan drive unit group 20, and also electrically connected to the first clock terminal CK1 of the first level second scan drive unit 220 (i.e., the fourth level second scan drive unit 220_4 of the display panel) in the second second scan drive unit group 20.

[0089] Optionally, in this embodiment of the invention, a Class B first clock signal line and a Class B second clock signal line may be respectively provided in the display panel. The Class B first clock signal line is electrically connected to the first clock terminal CK1 of each stage of the second scan driving unit 220 in the same second scan driving unit group 20; the Class B second clock signal line is electrically connected to the second clock terminal XCK1 of each stage of the second scan driving unit 220 in the same second scan driving unit group 20. According to the order of the effective levels transmitted by the Class B first clock signal line, the pulse width of the effective levels transmitted by the Class B first clock signal line gradually narrows, and correspondingly, the pulse width of the effective levels transmitted by the Class B second clock signal line also gradually narrows.

[0090] For example, the frequency of the signal transmitted on the second clock signal line is the same as the frequency of the signal transmitted on the first clock signal line. Alternatively, the frequencies of the signals transmitted on the first and second clock signal lines may be less than [the frequency of the first clock signal line]. Figure 8 and Figure 10The frequency of the signal transmitted by the clock signal line shown.

[0091] Taking B=2 as an example, for instance, as follows: Figure 11 and Figure 12 As shown, Figure 11 This is a connection diagram of another second scanning drive circuit provided in an embodiment of the present invention. Figure 12 for Figure 11 A corresponding sequence diagram, in Figure 11 The diagram illustrates two cascaded second scan drive unit groups 20 in the display panel. Figure 11 As shown, the display panel includes a first type of first clock signal line LC111, a second type of first clock signal line LC112, a first type of second clock signal line LX11, and a second type of second clock signal line LX12. The first type of first clock signal line LC111 is electrically connected to the first clock terminal CK1 of the first-stage second scan drive unit 220_1, and the second type of first clock signal line LC112 is electrically connected to the first clock terminal CK1 of the second-stage second scan drive unit 220_2. The first type of second clock signal line LX11 is electrically connected to the second clock terminal XCK1 of the first-stage second scan drive unit 220_1, and the second type of second clock signal line LX12 is electrically connected to the second clock terminal XCK1 of the second-stage second scan drive unit 220_2. The pulse width e3 of the effective level transmitted by the first type of first clock signal line LC111 is smaller than the pulse width f3 of the effective level transmitted by the second type of first clock signal line LC112. The pulse width of the effective level transmitted by the first clock signal line LC111 (Type 1) and the pulse width of the effective level transmitted by the second clock signal line LX11 (Type 1) are both e3. The pulse width of the effective level transmitted by the first clock signal line LC112 (Type 2) and the pulse width of the effective level transmitted by the second clock signal line LX12 (Type 2) are both f3. The effective level transmitted by the first clock signal line LC112 (Type 2) lies between the effective level transmitted by the first clock signal line LC111 and the effective level transmitted by the second clock signal line LX11 (Type 1). The effective level transmitted by the second clock signal line LX12 (Type 2) lies between the effective level transmitted by the first clock signal line LC111 and the effective level transmitted by the second clock signal line LX11 (Type 1). By adopting this configuration, while ensuring the normal operation of the second scanning drive circuit 220, the frequency of the signals transmitted by various first clock signal lines and various second clock signal lines can be kept low, which is beneficial to reducing the power consumption of the display panel.

[0092] For example, in an embodiment of the present invention, various first clock signal lines are alternately connected to the first clock terminal CK1 and the second clock terminal XCK1 of the corresponding level of the second scan driving unit 220 in two adjacent second scan driving unit groups 20. For example... Figure 11 As shown, for the first type of first clock signal line LC111, it is electrically connected to the first clock terminal CK1 of the first level second scan drive unit 220_1 in the first second scan drive unit group 20 and the second clock terminal XCK1 of the first level second scan drive unit 220 in the second second scan drive unit group 20, that is, the third level second scan drive unit 220_3 of the display panel.

[0093] Similarly, various second clock signal lines are alternately connected to the second clock terminal XCK1 and the first clock terminal CK1 of the corresponding level of the second scan drive unit 220 in two adjacent second scan drive unit groups 20. For example... Figure 11 As shown, for the first type of second clock signal line LX11, it is electrically connected to the second clock terminal XCK1 of the first level second scan drive unit 220_1 in the first second scan drive unit group 20 and the first clock terminal CK1 of the first level second scan drive unit 220 in the second second scan drive unit group 20, that is, the third level second scan drive unit 220_3 of the display panel.

[0094] Combination Figure 7 As shown, the width-to-length ratio of the channel of the first output transistor M21 of the second scan driving unit 220 electrically connected to the first pixel driving circuit 101 is W11 / L11, and the width-to-length ratio of the channel of the first output transistor M21 of the second scan driving unit 220 electrically connected to the second pixel driving circuit 102 is W21 / L21. In this embodiment of the invention, W11 / L11 < W21 / L21. This configuration allows the output delay of the second scan driving unit 220 electrically connected to the first pixel driving circuit 101 to be greater than that of the second scan driving unit 220 electrically connected to the second pixel driving circuit 102. Consequently, the time for the effective level received by the data write control terminal S1 of the first pixel driving circuit 101 is shorter than the time for the effective level received by the data write control terminal S1 of the second pixel driving circuit 102. This compensates for the difference in subsequent leakage time between the first node N11 of the first pixel driving circuit 101 and the first node N11 of the second pixel driving circuit 102.

[0095] Optionally, in this embodiment of the invention, the on-state current of the data writing transistor M11 in the first pixel driving circuit 101 can be made smaller than the on-state current of the data writing transistor M11 in the second pixel driving circuit 102, so that the threshold compensation degree of the first pixel driving circuit 101 is weaker than that of the second pixel driving circuit 102, so that the potential of the first node N11 of the first pixel driving circuit 101 is higher than that of the first node N11 of the second pixel driving circuit 102 after the corresponding data writing transistor M11 is turned off.

[0096] For example, the data writing transistor M11 includes a P-type transistor or an N-type transistor.

[0097] When the data writing transistors M11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 are both configured to include P-type transistors, the P-type transistors are turned on at a low level. In this embodiment of the invention, the effective level output by the second scan driving unit 220 electrically connected to the first pixel driving circuit 101 is greater than the effective level output by the second scan driving unit 220 electrically connected to the second pixel driving circuit 102, so that the on-state current of the data writing transistor M11 in the first pixel driving circuit 101 is less than the on-state current of the data writing transistor M11 in the second pixel driving circuit 102.

[0098] When the data writing transistors M11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 are both configured to include N-type transistors, the N-type transistors are turned on at a high level. In this embodiment of the invention, the effective level output by the second scan driving unit 220 electrically connected to the first pixel driving circuit 101 is less than the effective level output by the second scan driving unit 220 electrically connected to the second pixel driving circuit 102. This configuration ensures that the on-state current of the data writing transistor M11 in the first pixel driving circuit 101 is less than the on-state current of the data writing transistor M11 in the second pixel driving circuit 102.

[0099] For example, when the data writing transistor M11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 is configured to include a P-type transistor, this embodiment of the invention can make the effective level Vm transmitted by the m-th type clock signal line electrically connected to the first clock terminal CK1 of the m-th level second scan driving unit 220_m greater than the effective level Vn transmitted by the n-th type clock signal line electrically connected to the first clock terminal CK1 of the n-th level second scan driving unit 220_n. As mentioned above, the effective level output by the second scan driving unit 220 is the effective level of the signal received by its first clock terminal CK1. By making Vm > Vn, this embodiment of the invention can make the on-state current of the data writing transistor M11 in the first pixel driving circuit 101 less than the on-state current of the data writing transistor M11 in the second pixel driving circuit 102. Taking B = 2 as an example, combined with Figure 6 and Figure 13 As shown, Figure 13 for Figure 6 In another corresponding timing diagram, the effective level V1 transmitted by the first type of clock signal line LC11 is greater than the effective level V2 transmitted by the second type of clock signal line LC12.

[0100] It should be noted that while differentiating the effective level of various clock signal lines, the pulse width of the effective level of various clock signal lines can also be adjusted in the aforementioned manner.

[0101] Optionally, when the data writing transistor M11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 is configured to include an N-type transistor, the embodiment of the present invention can make the effective level Vm transmitted by the m-th type clock signal line electrically connected to the first clock terminal CK1 of the m-th level second scan driving unit 220_m less than the effective level Vn transmitted by the n-th type clock signal line electrically connected to the first clock terminal CK1 of the n-th level second scan driving unit 220_n, so that the on-state current of the data writing transistor M11 in the first pixel driving circuit 101 is less than the on-state current of the data writing transistor M11 in the second pixel driving circuit 102.

[0102] The display panel also includes Class B first-level signal lines. The Class B first-level signal lines are electrically connected to the first-level terminal VGL1 of the Class B second scan drive unit in the same second scan drive unit group 20.

[0103] When the data write transistors M11 of each pixel driving circuit in the same pixel group 1 are all P-type transistors, the potential of the signal transmitted by the Class B first level signal line gradually decreases according to the output order of the effective levels of the second scanning driving units in the same second scanning driving unit group 20.

[0104] When the data write transistors M11 of each pixel driving circuit in the same pixel group 1 are all N-type transistors, the potential of the signal transmitted by the Class B first level signal line gradually increases according to the output order of the effective level of each level of the second scanning driving unit in the same second scanning driving unit group 20.

[0105] Taking the example that the first level signal line of class B includes at least the first level signal line of class m and the first level signal line of class n, and the first level signal line of class m is electrically connected to the first level terminal VGL1 of the second scanning drive unit of class m; and the first level signal line of class n is electrically connected to the first level terminal VGL1 of the second scanning drive unit of class n, in this embodiment of the invention, when the data writing transistor M11 of each pixel drive circuit in the same pixel group 1 is a P-type transistor, the level transmitted by the first level signal line of class m is greater than the level transmitted by the first level signal line of class n.

[0106] Taking B=2 as an example, such as Figure 14 As shown, Figure 14 This is a connection diagram of another second scanning drive circuit provided in an embodiment of the present invention, wherein two second scanning drive unit groups 20 in the display panel are used as examples. For the two second scanning drive units 220 in the same second scanning drive unit group 20, the first level terminal VGL1 of the first-stage second scanning drive unit 220_1 is electrically connected to the first type of first level signal line LL11; the first level terminal VGL1 of the second-stage second scanning drive unit 220_2 is electrically connected to the second type of first level signal line LL12. The level transmitted by the first type of first level signal line LL11 is greater than the level transmitted by the second type of first level signal line LL12.

[0107] For the second scan driving unit 220, combined with Figure 7 As shown, when the potential of the second clock terminal XCK1 is low, the fifth transistor M25 and the fourth transistor M24 are turned on. When the signal input to the input terminal IN1 is also low, the control electrode of the seventh transistor M27 is written low by the input terminal IN through the fifth transistor M25, thereby turning on the seventh transistor M27, and the low level of the second clock terminal XCK1 is written to the control electrode of the eighth transistor M28. At the same time, the control electrode of the eighth transistor M28 is also written low by the first level terminal VGL1 through the fourth transistor M24. By differentiating the potentials connected to the first level terminals VGL1 of each level of the second scan driving unit 220 in the same second scan driving unit group 20, the potentials connected to the first level terminals VGL1 of each level of the second scan driving unit 220 can be matched with the potentials connected to the second clock terminal XCK1 of the corresponding second scan driving unit 220, which helps to avoid the path formed by the second clock terminal XCK1, the seventh transistor M27 and the first level terminal VGL1 (e.g. Figure 7 (As shown by the dashed arrow) A short circuit can ensure the display effect of the display panel.

[0108] This invention also provides a display panel, combined with Figure 1 and Figure 2 As shown, the display panel includes multiple pixel groups 1, each pixel group 1 comprising B pixel rows 10, where B ≥ 2 and B is a positive integer. Each pixel row 10 includes multiple pixel driving circuits 100, each pixel driving circuit 100 including a driving transistor M0, a data write control terminal S1, and a first scan control terminal S21. The control electrode of the driving transistor M0 is electrically connected to a first node N11, and the first electrode of the driving transistor M0 is electrically connected to a second node N12. The first scan driving circuit 21 includes multiple cascaded first scan driving units 210, each first scan driving unit 210 being electrically connected to multiple first scan control terminals S21 within the same pixel group 1.

[0109] The working cycle of the pixel driving circuit 100 includes a data writing period. During the data writing period, the data writing control terminal S1 and the first scan control terminal S21 receive valid levels. Multiple pixel driving circuits 100 in the same pixel group 1 include a first pixel driving circuit 101 and a second pixel driving circuit 102. Within the display time of one frame, such as... Figure 3 As shown, the data writing period TW_101 of the first pixel driving circuit 101 is located before the data writing period TW_102 of the second pixel driving circuit 102; and, in this embodiment of the invention, when the first pixel driving circuit 101 and the second pixel driving circuit 102 receive the same data voltage, after the data writing period TW_101 of the first pixel driving circuit 101, the leakage current velocity of the first node N11 in the first pixel driving circuit 101 is v. N11 After the data writing period TW_102 of the second pixel driving circuit 102, the leakage current rate of the first node N11 in the second pixel driving circuit 102 is v. N12 v N11 <v N12 .

[0110] The display panel provided in this embodiment of the invention can reduce the number of first scan driving units 210 required by the display panel by electrically connecting the first scan driving unit 210 to multiple first scan control terminals S21 in the same pixel group 1, thereby reducing the space occupied by the first scan driving circuit 21 in the non-display area NA, which is beneficial to improving the screen ratio of the display panel.

[0111] When the first pixel driving circuit 101 and the second pixel driving circuit 102 receive the same data voltage, after the respective data writing period of the first pixel driving circuit 101 and the second pixel driving circuit 102, that is, when their respective data writing transistors M11 are turned off, the embodiment of the present invention sets v N11 <v N12 This can compensate for or even eliminate the difference in leakage time between the first node N11 of the first pixel driving circuit 101 and the first node N11 of the second pixel driving circuit 102. After entering the light-emitting stage, the potential of the first node N11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 can be made to be consistent, which is beneficial to improving the brightness consistency of the light-emitting elements 200 driven by the two.

[0112] For example, the aspect ratio of the channel of the first light-emitting control transistor M16 in the first pixel driving circuit 101 is W12 / L12, and the aspect ratio of the channel of the first light-emitting control transistor M16 in the second pixel driving circuit 102 is W22 / L22, where W12 / L12 < W22 / L22. With this configuration, during the leakage of the potential of the first node N11 of the first pixel driving circuit 101 to the fourth node N14 through the threshold compensation transistor M12, the third node N13, and the first light-emitting control transistor M16, since the aspect ratio W12 / L12 of the channel of the first light-emitting control transistor M16 in the first pixel driving circuit 101 is smaller than the aspect ratio W22 / L22 of the channel of the first light-emitting control transistor M16 in the second pixel driving circuit 102, the leakage current velocity v of the first node N11 in the first pixel driving circuit 101 can be reduced. N11 The leakage velocity v is less than that of the first node N11 in the second pixel driving circuit 102. N12 .

[0113] Optionally, the first light-emitting control transistor M16 in the first pixel driving circuit 101 and the second pixel driving circuit 102 includes multiple sub-transistors connected in series, such as... Figure 15 As shown, Figure 15This is a schematic diagram illustrating the connection relationship between a first pixel driving circuit and a second pixel driving circuit provided in an embodiment of the present invention. In the first pixel driving circuit 101, the first light-emitting control transistor M16 includes three sub-transistors connected in series: M161, M162, and M163. Sub-transistors M161 and M162 are electrically connected to the fifth node N15, and sub-transistors M162 and M163 are electrically connected to the sixth node N16. In the second pixel driving circuit 102, the first light-emitting control transistor M16 is configured to include two sub-transistors connected in series: M164 and M165. Sub-transistors M164 and M165 are electrically connected to the seventh node N17. The arrangement of multiple sub-transistors connected in series slows down the leakage current from the third node N13 to the fourth node N14. Taking the first pixel driving circuit 101 as an example, the voltage difference between the third node N13 and the fifth node N15 will be less than... Figure 2 The pressure difference between the third node N13 and the fourth node N14 shown is therefore based on Figure 15 With this setting, the leakage current velocity between the third node N13 and the fourth node N14 will be slower.

[0114] In this embodiment of the invention, the number of sub-transistors included in the first light-emitting control transistor M16 in the first pixel driving circuit 101 is greater than the number of sub-transistors included in the first light-emitting control transistor M16 in the second pixel driving circuit 102. This configuration allows the leakage current velocity of the first node N11 in the first pixel driving circuit 101 to be less than the leakage current velocity of the first node N11 in the second pixel driving circuit 102.

[0115] When setting up the light-emitting driving circuit, for example, such as Figure 1 As shown, a light-emitting driving unit 230 can be electrically connected to the light-emitting control terminals E of the B pixel driving circuits in the aforementioned pixel group 1.

[0116] Alternatively, in embodiments of the present invention, the light-emitting driving unit 230 may be electrically connected to the pixel row 10 in a one-to-one correspondence. For example, as shown... Figure 16 As shown, Figure 16This is a schematic diagram of a light-emitting driving circuit according to an embodiment of the present invention. The light-emitting driving circuit 23 includes multiple cascaded light-emitting driving unit groups 30, and each light-emitting driving unit group 30 includes B cascaded light-emitting driving units 230. Multiple cascaded light-emitting driving unit groups 30 mean that the output terminal of the last stage light-emitting driving unit 230 in the previous light-emitting driving unit group 30 is electrically connected to the input terminal of the first stage light-emitting driving unit 230 in the current light-emitting driving unit group 30. The multiple cascaded light-emitting driving units 230 in the same light-emitting driving unit group 30 are respectively electrically connected to the light-emitting control terminals E of the pixel driving circuits in different pixel rows 10 of the same pixel group 1.

[0117] like Figure 17 As shown, Figure 17 The present invention provides a circuit diagram of a light-emitting driving unit 230, which includes a first transistor M31, a second transistor M32, a third transistor M33, a fourth transistor M34, a fifth transistor M35, a sixth transistor M36, a seventh transistor M37, an eighth transistor M38, a ninth transistor M39, a tenth transistor M30, a first capacitor C31, a second capacitor C32, and a third capacitor C33.

[0118] The control electrode of the first transistor M31 is electrically connected to the first clock terminal CK2, the first terminal of the first transistor M31 is electrically connected to the input terminal IN2, and the second terminal of the first transistor M31 is electrically connected to the first node N31. Under the control of the signal provided by the first clock terminal CK2, the first transistor M31 controls the electrical connection between the input terminal IN2 and the first node N31, thereby adjusting the potential of the first node N31. The control electrode of the second transistor M32 is electrically connected to the second clock terminal XCK2, the first terminal of the second transistor M32 is electrically connected to the first node N31, and the second terminal of the second transistor M32 is electrically connected to the first terminal of the third transistor M33. The control electrode of the third transistor M33 is electrically connected to the third node N33, and the second terminal of the third transistor M33 is electrically connected to the input terminal IN2. Under the control of the signals provided by the second clock terminal XCK2 and the third node N33, the second transistor M32 and the third transistor M33 control the electrical connection between the input terminal IN2 and the first node N31, thereby adjusting the potential of the first node N31. The control electrode of the fourth transistor M34 is electrically connected to the first node N31, the first terminal of the fourth transistor M34 is electrically connected to the first clock terminal CK2, and the second terminal of the fourth transistor M34 is electrically connected to the third node N33. Under the control of the first node N31, the fourth transistor M34 controls the electrical connection between the first clock terminal CK2 and the third node N33, so as to adjust the potential of the third node N33 through the signal of the first clock terminal CK2. The control electrode of the fifth transistor M35 is electrically connected to the first clock terminal CK2, the first terminal of the fifth transistor M35 is electrically connected to the first level terminal VGL2, and the second terminal of the fifth transistor M35 is electrically connected to the third node N33. Under the control of the signal provided by the first clock terminal CK2, the fifth transistor M35 controls the electrical connection between the first level terminal VGL2 and the third node N33, so as to adjust the potential of the third node N33 through the signal of the first level terminal VGL2. The gate electrode of the sixth transistor M36 is electrically connected to the third node N33, the first terminal of the sixth transistor M36 is electrically connected to the second clock terminal XCK2, and the second terminal of the sixth transistor M36 is electrically connected to the fourth node N34. Under the control of the third node N33, the sixth transistor M36 controls the electrical connection between the second clock terminal XCK2 and the fourth node N34, so as to adjust the potential of the fourth node N34 through the signal provided by the second clock terminal XCK2. The gate electrode of the seventh transistor M37 is electrically connected to the second clock terminal XCK2, the first terminal of the seventh transistor M37 is electrically connected to the fourth node N34, and the second terminal of the seventh transistor M37 is electrically connected to the second node N32. Under the control of the signal provided by the second clock terminal XCK2, the seventh transistor M37 controls the electrical connection between the fourth node N34 and the second node N32, so as to adjust the potential of the second node N32 through the signal provided by the fourth node N34.The control electrode of the eighth transistor M38 is electrically connected to the first node N31, the first terminal of the eighth transistor M38 is electrically connected to the second level terminal VGH2, and the second terminal of the eighth transistor M38 is electrically connected to the second node N32. Under the control of the first node N31, the eighth transistor M38 controls the electrical connection between the second level terminal VGH2 and the second node N32, so as to adjust the potential of the second node N32 through the signal of the second level terminal VGH2. The control electrode of the ninth transistor M39 is electrically connected to the first node N31, the first terminal of the ninth transistor M39 is electrically connected to the first level terminal VGL2, and the second terminal of the ninth transistor M39 is electrically connected to the output terminal OUT2. Under the control of the first node N31, the ninth transistor M39 controls the electrical connection between the first level terminal VGL2 and the output terminal OUT2, so as to adjust the output signal of the output terminal OUT2 through the first level terminal VGL2. The control electrode of the tenth transistor M30 is electrically connected to the second node N32, the first terminal of the tenth transistor M30 is electrically connected to the second level terminal VGH2, and the second terminal of the tenth transistor M30 is electrically connected to the output terminal OUT2. Under the control of the second node N32, the tenth transistor M30 controls the electrical connection between the second level terminal VGH2 and the output terminal OUT2, so as to adjust the output signal of the output terminal OUT2 through the second level terminal VGH2.

[0119] The first terminal of the first capacitor C21 is electrically connected to the first node N21, and the second terminal of the first capacitor C21 is electrically connected to the second clock terminal XCK2. The first terminal of the second capacitor C22 is electrically connected to the third node N23, and the second terminal of the second capacitor C22 is electrically connected to the fourth node N24. The first terminal of the third capacitor C23 is electrically connected to the second level terminal VGH2, and the second terminal of the third capacitor C23 is electrically connected to the second node N22.

[0120] The first level terminal VGL2 is used to transmit a signal that turns on the first light-emitting control transistor M16 in the pixel driving circuit 100. The second level terminal VGH2 is used to transmit a signal that turns off the first light-emitting control transistor M16 in the pixel driving circuit 100. For example, when the first light-emitting control transistor M16 is a P-type transistor, the first level terminal VGL2 receives a low-level signal VGL, and the second level terminal VGH2 receives a high-level signal VGH.

[0121] In this embodiment of the invention, the display panel further includes Class B second-level signal lines. These Class B second-level signal lines are electrically connected to the second-level terminal VGH2 of the Class B light-emitting driving unit 230 in the same light-emitting driving unit group 30. Exemplarily, each type of second-level signal line is used to transmit a constant signal. This constant signal includes a signal capable of controlling the first light-emitting control transistor M16 of the corresponding pixel driving circuit 100 to turn off. The voltage levels transmitted by these Class B second-level signal lines are different from each other. According to the data writing order of the corresponding connected pixel driving circuits, the voltage levels transmitted by the aforementioned Class B second-level signal lines gradually decrease.

[0122] Taking a Class B light-emitting driving unit 230 within the same light-emitting driving unit group 30, which includes at least a p-th class light-emitting driving unit 30_p and a q-th class light-emitting driving unit 30_q, as an example; where p and q are both integers, 1 ≤ p < q ≤ B. The Class B second-level signal lines include a p-th class second-level signal line and a q-th class second-level signal line. The p-th class second-level signal line is electrically connected to the second-level terminal VGH2 of the p-th class light-emitting driving unit 30_p, and the q-th class second-level signal line is electrically connected to the second-level terminal VGH2 of the q-th class light-emitting driving unit 30_q. The voltage of the p-th class second-level signal line is greater than the voltage of the q-th class second-level signal line.

[0123] Taking B=2 as an example, such as Figure 18 As shown, Figure 18 This is a schematic diagram of a light-emitting driving circuit provided in an embodiment of the present invention. Two light-emitting driving unit groups 30 in a display panel are used as examples. The input terminal IN2 of the first-stage light-emitting driving unit 230_1 in the first light-emitting driving unit group 30 is electrically connected to the light-emitting frame start signal line LS2. The first type of second-level signal line LH21 is electrically connected to the second-level terminal VGH2 of the first-stage light-emitting driving unit 230_1. The second type of second-level signal line LH22 is electrically connected to the second-level terminal VGH2 of the second-stage light-emitting driving unit 2. The voltage of the signal provided by the first type of second-level signal line LH21 is greater than the voltage of the signal provided by the second type of second-level signal line LH22.

[0124] In this embodiment of the invention, a parasitic capacitance exists between the light-emitting control signal line connecting the light-emitting driving unit 230 and the pixel driving circuit and the first node N11 in the pixel driving circuit. When the signal in the light-emitting control signal line connected to the pixel driving circuit 100 changes from an enabled level (e.g., high level) to an enabled level (e.g., low level), causing the corresponding light-emitting element to start emitting light, the signal transition on the corresponding light-emitting control signal line will affect the potential of the first node N11 in the corresponding pixel driving circuit through coupling, causing the potential of the first node N11 to decrease. This embodiment of the invention connects different light-emitting driving units 230 in the same light-emitting driving unit group 30 to different types of second-level signal lines, and decreases the voltage of the signals transmitted by each type of second-level signal line according to the data writing order of the corresponding electrically connected pixel driving circuits. Within a pixel group, the first nodes in the pixel driving circuits of different pixel rows can be coupled to different degrees by the light-emitting control signal when entering the light-emitting stage, thereby balancing the differences in leakage current time of the first nodes of each pixel driving circuit.

[0125] This invention also provides a method for driving a display panel. The display panel has been described in detail above and will not be repeated here. Combined with... Figure 3 and Figure 19 As shown, Figure 19 This is a schematic diagram of a driving method for a display panel provided in an embodiment of the present invention. The driving method includes:

[0126] Within the display time of one frame, the data writing period TW_101 of the first pixel driving circuit 101 is located before the data writing period TW_102 of the second pixel driving circuit 102; and, when the first pixel driving circuit 101 and the second pixel driving circuit 102 receive the same data voltage, after the data writing period TW_101 of the first pixel driving circuit 101, the potential of the first node N11 in the first pixel driving circuit 101 is V. N11 After the data writing period TW_102 of the second pixel driving circuit 102, the potential of the first node N11 in the second pixel driving circuit 102 is V. N12 V N11 >V N12 .

[0127] The display panel driving method provided in this embodiment of the invention, when the first pixel driving circuit 101 and the second pixel driving circuit 102 receive the same data voltage, after the respective data writing period of the first pixel driving circuit 101 and the second pixel driving circuit 102, that is, when their respective data writing transistors M11 are turned off, the present invention embodiment enables V... N11 >V N12This can compensate for or even eliminate the difference in leakage time between the first node N11 of the first pixel driving circuit 101 and the first node N11 of the second pixel driving circuit 102. After entering the light-emitting stage, the potential of the first node N11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 can be made to be consistent, which is beneficial to improving the brightness consistency of the light-emitting elements 200 driven by the two.

[0128] For example, in combination Figure 2 As shown, the above control V N11 >V N12 The methods include:

[0129] The conduction time of the data writing transistor M11 in the first pixel driving circuit 101 is less than the conduction time of the data writing transistor M11 in the second pixel driving circuit 102.

[0130] Optional, combined Figure 1 As shown, the display panel also includes a second scan driving circuit 22, which includes multiple cascaded second scan driving unit groups 20. Each second scan driving unit group 20 includes B cascaded second scan driving units 220. The B second scan driving units 220 in the same second scan driving unit group 20 include at least an m-th level second scan driving unit and an n-th level second scan driving unit, where m and n are integers and 1 ≤ m < n ≤ B. The output terminal of the m-th level second scan driving unit is electrically connected to the data writing control terminal S1 of the first pixel driving circuit 101, and the output terminal of the n-th level second scan driving unit is electrically connected to the data writing control terminal S1 of the second pixel driving circuit 102.

[0131] Combination Figure 6 and Figure 7 As shown, the second scan driving unit 220 includes a clock terminal; the display panel also includes a Class B clock signal line, which includes at least a Class m clock signal line and a Class n clock signal line. The Class m clock signal line is electrically connected to the clock terminal of the Class m second scan driving unit; the Class n clock signal line is electrically connected to the clock terminal of the Class n second scan driving unit.

[0132] The method for controlling the on-time of the data writing transistor M11 in the first pixel driving circuit 101 to be less than the on-time of the data writing transistor M11 in the second pixel driving circuit 102 includes:

[0133] The duration of the effective level transmitted by the m-th clock signal line is less than the duration of the effective level transmitted by the n-th clock signal line.

[0134] Optionally, the above control V N11 >V N12 The methods include:

[0135] The on-state current of the data writing transistor M11 in the first pixel driving circuit 101 is controlled to be less than the on-state current of the data writing transistor M11 in the second pixel driving circuit 102.

[0136] For example, the data writing transistor M11 in the first pixel driving circuit 101 and the second pixel driving circuit 102 includes a P-type transistor; the method for controlling the on-state current of the data writing transistor M11 in the first pixel driving circuit 101 to be less than the on-state current of the data writing transistor M11 in the second pixel driving circuit 102 includes:

[0137] The effective level output by the second scan driving unit 220, which is electrically connected to the first pixel driving circuit 101, is greater than the effective level output by the second scan driving unit 220, which is electrically connected to the second pixel driving circuit 102.

[0138] Alternatively, in this embodiment of the invention, both the data writing transistors M11 in the first pixel driving circuit 101 and the second pixel driving circuit 102 may be configured to include N-type transistors; the method for controlling the on-state current of the data writing transistor M11 in the first pixel driving circuit 101 to be less than the on-state current of the data writing transistor M11 in the second pixel driving circuit 102 includes:

[0139] The effective level output by the second scan drive unit 220, which is electrically connected to the first pixel drive circuit 101, is lower than the effective level output by the second scan drive unit 220, which is electrically connected to the second pixel drive circuit 102.

[0140] The B cascaded second scan driving units 220 in the same second scan driving unit group 20 mentioned above include an m-th level second scan driving unit 220 and an n-th level second scan driving unit 220. The output terminal of the m-th level second scan driving unit 220 is electrically connected to the data write control terminal S1 of the first pixel driving circuit 101, and the output terminal of the n-th level second scan driving unit 220 is electrically connected to the data write control terminal S1 of the second pixel driving circuit 102. The second scan driving unit 220 includes a clock terminal CK1. The display panel also includes an m-th type clock signal line and an n-th type clock signal line. The m-th type clock signal line is electrically connected to the clock terminal CK1 of the m-th level second scan driving unit 220, and the n-th type clock signal line is electrically connected to the clock terminal CK1 of the n-th level second scan driving unit 220.

[0141] For example, in embodiments of the present invention, the data writing transistors M1 in the first pixel driving circuit 101 and the second pixel driving circuit 102 can both be configured to include P-type transistors; the method described above for controlling the effective level output by the second scan driving unit 220 electrically connected to the first pixel driving circuit 101 to be greater than the effective level output by the second scan driving unit 220 electrically connected to the second pixel driving circuit 102 includes: controlling the effective level transmitted by the m-th type clock signal line to be greater than the effective level transmitted by the n-th type clock signal line.

[0142] For example, in this embodiment of the invention, the data writing transistors M11 in the first pixel driving circuit 101 and the second pixel driving circuit 102 may both be configured to include N-type transistors; the method for controlling the effective level output by the second scan driving unit 220 electrically connected to the first pixel driving circuit 101 to be less than the effective level output by the second scan driving unit 220 electrically connected to the second pixel driving circuit 102 includes: controlling the effective level transmitted by the m-th type clock signal line to be less than the effective level transmitted by the n-th type clock signal line.

[0143] This invention also provides a method for driving a display panel, such as... Figure 20 As shown, Figure 20 This is a schematic diagram of another driving method for a display panel provided in an embodiment of the present invention. The driving method includes:

[0144] Within the display time of one frame, the data writing period TW_101 of the first pixel driving circuit 101 is located before the data writing period TW_102 of the second pixel driving circuit 102; and, when the first pixel driving circuit 101 and the second pixel driving circuit 102 receive the same data voltage, after the data writing period TW_101 of the first pixel driving circuit 101, the leakage current velocity of the first node in the first pixel driving circuit 101 is v. N11 After the data writing period TW_102 of the second pixel driving circuit 102, the leakage current rate of the first node in the second pixel driving circuit 102 is v. N12 v N11 <v N12 .

[0145] The display panel driving method provided in this embodiment of the invention, when the first pixel driving circuit 101 and the second pixel driving circuit 102 receive the same data voltage, after the respective data writing period of the first pixel driving circuit 101 and the second pixel driving circuit 102, that is, when their respective data writing transistors M11 are turned off, the embodiment of the invention enables v N11 <v N12This can compensate for or even eliminate the difference in leakage time between the first node N11 of the first pixel driving circuit 101 and the first node N11 of the second pixel driving circuit 102. After entering the light-emitting stage, the potential of the first node N11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 can be made to be consistent, which is beneficial to improving the brightness consistency of the light-emitting elements 200 driven by the two.

[0146] Combination Figure 16 As shown, the display panel also includes a light-emitting driving circuit 23, which includes multiple cascaded light-emitting driving unit groups 30, and each light-emitting driving unit group 30 includes B cascaded light-emitting driving units 230. Combined with... Figure 17 As shown, the light-emitting driving unit 230 includes a second-level terminal VGH2; the display panel also includes Class B second-level signal lines. The Class B second-level signal lines are electrically connected to the second-level terminals VGH2 of the Class B light-emitting driving units 230 in the same light-emitting driving unit group 30. The levels transmitted by these Class B second-level signal lines are different from each other. According to the data writing order of the corresponding connected pixel driving circuits, the voltage of the levels transmitted by the aforementioned Class M second-level signal lines gradually decreases. Taking the Class B light-emitting driving unit 230 in the same light-emitting driving unit group 30 as an example, which includes at least a p-th level light-emitting driving unit and a q-th level light-emitting driving unit, the output terminal of the p-th level light-emitting driving unit is electrically connected to the light-emitting control terminal of the first pixel driving circuit, and the output terminal of the q-th level light-emitting driving unit is electrically connected to the light-emitting control terminal of the second pixel driving circuit; p and q are both integers, and 1 ≤ p < q ≤ B. Accordingly, the Class B second-level signal line includes at least a Class p second-level signal line and a Class q second-level signal line. The Class p second-level signal line is electrically connected to the second-level terminal of the Class p light-emitting driving unit; the Class q second-level signal line is electrically connected to the second-level terminal of the Class q light-emitting driving unit.

[0147] For example, the above control v N11 <v N12 The method includes controlling the voltage of the second-level signal line of the p-th class to be greater than the voltage of the second-level signal line of the q-th class.

[0148] This invention also provides a display device, such as... Figure 21 As shown, Figure 21 This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device includes the display panel 1000 described above. The specific structure of the display panel 1000 has been described in detail in the above embodiments and will not be repeated here. Figure 21 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader or television.

[0149] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that, include: Multiple pixel groups, each pixel group comprising B pixel rows, where B ≥ 2 and B is an integer; each pixel row comprising multiple pixel driving circuits, each pixel driving circuit comprising a driving transistor, a data writing control terminal, and a first scan control terminal; the control electrode of the driving transistor is electrically connected to a first node, and the first electrode of the driving transistor is electrically connected to a second node; The first scan driving unit is electrically connected to multiple first scan control terminals in the same pixel group; The working cycle of the pixel driving circuit includes a data writing period. During the data writing period, the data writing control terminal receives a valid level, and the first scan driving unit provides a valid level to the first scan control terminal. The plurality of pixel driving circuits in the same pixel group include a first pixel driving circuit and a second pixel driving circuit located in different pixel rows. During the display time of a frame, the data writing period of the first pixel driving circuit is before the data writing period of the second pixel driving circuit. The display panel further includes a second scan driving circuit, which includes multiple cascaded second scan driving unit groups, each of which includes B cascaded second scan driving units; the second scan driving unit is electrically connected to the data writing control terminal of the pixel driving circuit. The B second scanning driving units in the same second scanning driving unit group include at least an m-th level second scanning driving unit and an n-th level second scanning driving unit. The output terminal of the m-th level second scanning driving unit is electrically connected to the data writing control terminal of the first pixel driving circuit, and the output terminal of the n-th level second scanning driving unit is electrically connected to the data writing control terminal of the second pixel driving circuit. Both m and n are integers, and 1 ≤ m < n ≤ B; the second scan driving unit includes a clock terminal; the display panel also includes a type B clock signal line, and each different second scan driving unit in the same second scan driving unit group is connected to a different type of clock signal line; the type B clock signal line includes at least a type m clock signal line and a type n clock signal line, the type m clock signal line is electrically connected to the clock terminal of the type m second scan driving unit; the type n clock signal line is electrically connected to the clock terminal of the type n second scan driving unit; The pixel driving circuit also includes a data writing transistor. The data writing transistor includes a P-type transistor; the effective level transmitted by the m-th type clock signal line is greater than the effective level transmitted by the n-th type clock signal line; the effective level output by the second scan driving unit electrically connected to the first pixel driving circuit is greater than the effective level output by the second scan driving unit electrically connected to the second pixel driving circuit; or, The data writing transistor includes an N-type transistor; The effective level transmitted by the m-th type clock signal line is less than the effective level transmitted by the n-th type clock signal line; the effective level output by the second scan driving unit electrically connected to the first pixel driving circuit is less than the effective level output by the second scan driving unit electrically connected to the second pixel driving circuit.

2. The display panel according to claim 1, characterized in that, The control electrode of the data writing transistor is electrically connected to the data writing control terminal, the first electrode of the data writing transistor is electrically connected to the data voltage terminal, and the second electrode of the data writing transistor is electrically connected to the second node. During the display time of one frame, the on-time of the data writing transistor in the first pixel driving circuit is shorter than the on-time of the data writing transistor in the second pixel driving circuit.

3. The display panel according to claim 2, characterized in that, The display panel further includes a second scanning driving circuit, which includes multiple cascaded second scanning driving unit groups. Each second scanning driving unit group includes B cascaded second scanning driving units. The B second scanning driving units in the same second scanning driving unit group include at least an m-th level second scanning driving unit and an n-th level second scanning driving unit, where m and n are integers and 1 ≤ m < n ≤ B. The output terminal of the m-th level second scanning driving unit is electrically connected to the data writing control terminal of the first pixel driving circuit, and the output terminal of the n-th level second scanning driving unit is electrically connected to the data writing control terminal of the second pixel driving circuit. The second scan driving unit includes a clock terminal; the display panel further includes a Class B clock signal line, which includes at least a Class m clock signal line and a Class n clock signal line, and the Class m clock signal line is electrically connected to the clock terminal of the m-th level second scan driving unit; The nth type of clock signal line is electrically connected to the clock terminal of the nth level second scan drive unit; The pulse width of the effective level transmitted by the m-th type clock signal line is smaller than the pulse width of the effective level transmitted by the n-th type clock signal line.

4. The display panel according to claim 2, characterized in that, The display panel further includes a second scan driving circuit, which includes multiple cascaded second scan driving units; the second scan driving units are electrically connected to the data writing control terminal of the pixel driving circuit. The second scan driving unit includes a first output transistor, which is used to electrically connect the clock terminal and the output terminal of the second scan driving unit; The width-to-length ratio of the channel of the first output transistor of the second scan driving unit electrically connected to the first pixel driving circuit is W11 / L11, and the width-to-length ratio of the channel of the first output transistor of the second scan driving unit electrically connected to the second pixel driving circuit is W21 / L21, where W11 / L11 < W21 / L21.

5. The display panel according to claim 1, characterized in that, The on-state current of the data writing transistor in the first pixel driving circuit is less than the on-state current of the data writing transistor in the second pixel driving circuit.

6. The display panel according to claim 1, characterized in that, The second scanning driving unit further includes a first level terminal; the display panel further includes a Class B first level signal line, which includes at least a Class m first level signal line and a Class n first level signal line, and the Class m first level signal line is electrically connected to the first level terminal of the m-th level second scanning driving unit; The first level signal line of the nth type is electrically connected to the first level terminal of the second scan driving unit of the nth level; The data writing transistor includes a P-type transistor; the level transmitted by the m-th type first level signal line is greater than the level transmitted by the n-th type first level signal line; or, The data writing transistor includes an N-type transistor; The voltage level transmitted by the m-th type first level signal line is lower than the voltage level transmitted by the n-th type first level signal line.

7. A display panel, characterized in that, include: Multiple pixel groups, each pixel group comprising B pixel rows, where B ≥ 2 and B is an integer; each pixel row comprising multiple pixel driving circuits, each pixel driving circuit comprising a driving transistor, a data writing control terminal, and a first scan control terminal; the control electrode of the driving transistor is electrically connected to a first node, and the first electrode of the driving transistor is electrically connected to a second node; The first scan driving unit is electrically connected to multiple first scan control terminals in the same pixel group; The working cycle of the pixel driving circuit includes a data writing period. During the data writing period, the data writing control terminal receives a valid voltage level, and the first scan driving unit provides a valid voltage level. The plurality of pixel driving circuits in the same pixel group include a first pixel driving circuit and a second pixel driving circuit located in different pixel rows. Within the display time of one frame, the data writing period of the first pixel driving circuit precedes the data writing period of the second pixel driving circuit. Furthermore, when the first pixel driving circuit and the second pixel driving circuit receive the same data voltage, after the data writing period, when the data writing transistor in the first pixel driving circuit is turned off, the leakage current rate of the first node in the first pixel driving circuit is... v N11 When the data write transistor in the second pixel driving circuit is turned off, the leakage current rate of the first node in the second pixel driving circuit is v N12 , v N11 < v N12 .

8. The display panel according to claim 7, characterized in that, The pixel driving circuit further includes a light-emitting control transistor, the control electrode of which is electrically connected to the light-emitting control terminal, the first electrode of which is electrically connected to the second electrode of the driving transistor, and the second electrode of which is electrically connected to the light-emitting element. The width-to-length ratio of the channel of the light-emitting control transistor in the first pixel driving circuit is W12 / L12, and the width-to-length ratio of the channel of the light-emitting control transistor in the second pixel driving circuit is W22 / L22, where W12 / L12 < W22 / L22.

9. The display panel according to claim 7, characterized in that, The pixel driving circuit further includes a first light-emitting control transistor, the control electrode of the first light-emitting control transistor is electrically connected to the light-emitting control terminal, the first electrode of the first light-emitting control transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the light-emitting control transistor is electrically connected to the light-emitting element. The first light-emitting control transistor includes a plurality of sub-transistors connected in series, and the number of the sub-transistors in the first pixel driving circuit is greater than the number of the sub-transistors in the second pixel driving circuit.

10. The display panel according to claim 7, characterized in that, The display panel further includes a light-emitting driving circuit, which includes multiple cascaded light-emitting driving unit groups, each group comprising B cascaded light-emitting driving units; the B light-emitting driving units in the same group include at least a p-th level light-emitting driving unit and a q-th level light-emitting driving unit, the output terminal of the p-th level light-emitting driving unit being electrically connected to the light-emitting control terminal of the first pixel driving circuit, and the output terminal of the q-th level light-emitting driving unit being electrically connected to the light-emitting control terminal of the second pixel driving circuit; p and q are both integers, and 1 ≤ p < q ≤ B; The light-emitting driving unit includes a second level terminal; the display panel further includes a Class B second level signal line, which includes at least a Class p second level signal line and a Class q second level signal line, and the Class p second level signal line is electrically connected to the second level terminal of the Class p light-emitting driving unit. The second level signal line of the qth class is electrically connected to the second level terminal of the qth level light-emitting driving unit; The voltage of the second-level signal line of the p-th class is greater than the voltage of the second-level signal line of the q-th class.

11. A driving method for a display panel, characterized in that, The display panel includes: Multiple pixel groups, each pixel group comprising B pixel rows, where B ≥ 2 and B is an integer; each pixel row comprising multiple pixel driving circuits, each pixel driving circuit comprising a driving transistor, a data writing control terminal, and a first scan control terminal; the control electrode of the driving transistor is electrically connected to a first node, and the first electrode of the driving transistor is electrically connected to a second node; The first scan driving unit is electrically connected to multiple first scan control terminals in the same pixel group; The working cycle of the pixel driving circuit includes a data writing period. During the data writing period, the data writing control terminal receives a valid level, and the first scanning driving unit provides a valid level. The multiple pixel driving circuits in the same pixel group include a first pixel driving circuit and a second pixel driving circuit located in different pixel rows. The driving method includes: Within the display time of one frame, the data writing period of the first pixel driving circuit is located before the data writing period of the second pixel driving circuit; The B second scan driving units in the same second scan driving unit group include at least an m-th level second scan driving unit and an n-th level second scan driving unit. The output terminal of the m-th level second scan driving unit is electrically connected to the data write control terminal of the first pixel driving circuit, and the output terminal of the n-th level second scan driving unit is electrically connected to the data write control terminal of the second pixel driving circuit. m and n are both integers, and 1 ≤ m < n ≤ B. The second scan driving unit includes a clock terminal. The display panel also includes a type B clock signal line. Each different second scan driving unit in the same second scan driving unit group is connected to a different type of clock signal line. The type B clock signal line includes at least a type m clock signal line and a type n clock signal line. The type m clock signal line is electrically connected to the clock terminal of the m-th level second scan driving unit, and the type n clock signal line is electrically connected to the clock terminal of the n-th level second scan driving unit. The pixel driving circuit also includes a data writing transistor; The data writing transistor includes a P-type transistor; the effective level transmitted by the m-th type clock signal line is greater than the effective level transmitted by the n-th type clock signal line; or, The data writing transistor includes an N-type transistor; the effective level transmitted by the m-th type clock signal line is less than the effective level transmitted by the n-th type clock signal line; The control electrode of the data writing transistor is electrically connected to the data writing control terminal, the first electrode of the data writing transistor is electrically connected to the data voltage terminal, and the second electrode of the data writing transistor is electrically connected to the second node. Control V N11 >V N12 The methods include: The on-time of the data writing transistor in the first pixel driving circuit is controlled to be less than the on-time of the data writing transistor in the second pixel driving circuit; A method for controlling the on-time of the data write transistor in the first pixel driving circuit to be less than the on-time of the data write transistor in the second pixel driving circuit includes: The duration of the effective level transmitted by the m-th type clock signal line is controlled to be less than the duration of the effective level transmitted by the n-th type clock signal line.

12. The driving method according to claim 11, characterized in that, Control V N11 >V N12 The methods include: The on-state current of the data writing transistor in the first pixel driving circuit is controlled to be less than the on-state current of the data writing transistor in the second pixel driving circuit.

13. The driving method according to claim 12, characterized in that, The display panel further includes a second scanning drive circuit, which includes multiple cascaded second scanning drive unit groups, and the second scanning drive unit group includes B cascaded second scanning drive units. The data writing transistor includes a P-type transistor; a method for controlling the on-state current of the data writing transistor in the first pixel driving circuit to be less than the on-state current of the data writing transistor in the second pixel driving circuit includes: The effective level output by the second scan driving unit electrically connected to the first pixel driving circuit is greater than the effective level output by the second scan driving unit electrically connected to the second pixel driving circuit. Alternatively, the data writing transistor includes an N-type transistor; the method for controlling the on-state current of the data writing transistor in the first pixel driving circuit to be less than the on-state current of the data writing transistor in the second pixel driving circuit includes: The effective level output by the second scan driving unit, which is electrically connected to the first pixel driving circuit, is lower than the effective level output by the second scan driving unit, which is electrically connected to the second pixel driving circuit.

14. A driving method for a display panel, characterized in that, The display panel includes: Multiple pixel groups, each pixel group comprising B pixel rows, where B ≥ 2 and B is an integer; each pixel row comprising multiple pixel driving circuits, each pixel driving circuit comprising a driving transistor, a data writing control terminal, and a first scan control terminal; the control electrode of the driving transistor is electrically connected to a first node, and the first electrode of the driving transistor is electrically connected to a second node; The first scan driving unit is electrically connected to multiple first scan control terminals in the same pixel group; The working cycle of the pixel driving circuit includes a data writing period. During the data writing period, the data writing control terminal receives a valid level, and the first scanning driving unit provides a valid level. The multiple pixel driving circuits in the same pixel group include a first pixel driving circuit and a second pixel driving circuit located in different rows. The driving method includes: Within the display time of one frame, the data writing period of the first pixel driving circuit is positioned before the data writing period of the second pixel driving circuit; and, when the first pixel driving circuit and the second pixel driving circuit receive the same data voltage, after the data writing period, when the data writing transistor in the first pixel driving circuit is turned off, the leakage current rate of the first node in the first pixel driving circuit is... v N11 When the data write transistor in the second pixel driving circuit is turned off, the leakage current rate of the first node in the second pixel driving circuit is v N12 , v N11 < v N12 ; The display panel further includes a light-emitting driving circuit, which includes multiple cascaded light-emitting driving unit groups, each group comprising B cascaded light-emitting driving units. Each group of B light-emitting driving units includes at least a p-th level light-emitting driving unit and a q-th level light-emitting driving unit. The output terminal of the p-th level light-emitting driving unit is electrically connected to the light-emitting control terminal of the first pixel driving circuit, and the output terminal of the q-th level light-emitting driving unit is electrically connected to the data writing control terminal of the light-emitting control terminal of the second pixel driving circuit. p and q are both integers, and 1 ≤ p < q ≤ B. The light-emitting driving unit includes a second level terminal; the display panel further includes a Class B second level signal line, which includes at least a Class p second level signal line and a Class q second level signal line, wherein the Class p second level signal line is electrically connected to the second level terminal of the Class p light-emitting driving unit; and the Class q second level signal line is electrically connected to the second level terminal of the Class q light-emitting driving unit. control v N11 < v N12 The methods include: The voltage of the p-th type second level signal line is controlled to be greater than the voltage of the q-th type second level signal line.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 1-10.

Images