Metal-oxide-metal capacitor and method of forming same

Abstract

The invention provides a metal-oxide-metal capacitor and a forming method thereof, and the method comprises the steps: providing a substrate, forming a first dielectric layer on the substrate, and forming a plurality of first concave chambers in the first dielectric layer; forming a first metal layer, wherein the first concave chamber is filled with the first metal layer; forming a second dielectric layer, wherein the second dielectric layer covers the first metal layer and the first dielectric layer; forming a second concave chamber and a through hole which are communicated in the second dielectric layer, wherein the through hole exposes part of the first metal layer; a second metal layer is formed, the second concave chamber and the through hole are filled with the second metal layer, and the second metal layer is electrically connected with the first metal layer; the stress of the first dielectric layer and the stress of the second dielectric layer are both smaller than 50 MPa. The low-stress dielectric layer formed by the method is used as a metal interlayer film, the breakdown performance of a voltage slope dielectric of a subsequent channel is greatly improved, a device can be qualified for an application scene with a high-voltage requirement, and the application range of a product is expanded.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a metal-oxide-metal capacitor and a forming method thereof. Background Art

[0002] Voltage ramp dielectric breakdown is an important dielectric layer reliability indicator. Generally, there are two indicators: front-end gate oxide voltage ramp dielectric breakdown and back-end capacitor dielectric layer voltage ramp dielectric breakdown.

[0003] In the back-end device design, the metal-oxide-metal capacitor structure is used to store charge through the dielectric layer between the metal layers to achieve the capacitor function; at the same time, the capacitor performance is optimized through different levels of metal. Compared with the metal-insulator-metal capacitor structure, it can not only save the production cost of a metal capacitor lithography layer, but also the metal-oxide-metal capacitor structure has a high process integration and is more suitable for applications that require high capacity and high voltage. Therefore, it is widely used when the device has high capacity or high voltage requirements.

[0004] In a metal-oxide-metal capacitor, metal is formed in a dielectric layer, and metal strips in the same layer are isolated from each other by the dielectric layer. After the dielectric layer grows into a film, the stress is relatively large. The large stress in the dielectric layer results in a low voltage ramp dielectric breakdown of the metal-oxide-metal capacitor, and the voltage ramp dielectric breakdown performance is poor, which has great limitations on the high-voltage application scenarios of the device and is in urgent need of improvement. Summary of the invention

[0005] The purpose of the present invention is to provide a metal-oxide-metal capacitor and a method for forming the same. The low-stress dielectric layer formed serves as a metal interlayer film, which greatly improves the voltage ramp dielectric breakdown performance of the subsequent process, so that the device can be used in application scenarios with high voltage requirements and expand the product application range.

[0006] The present invention provides a method for forming a metal-oxide-metal capacitor, comprising:

[0007] Providing a substrate, forming a first dielectric layer on the substrate, and forming a plurality of first recessed chambers in the first dielectric layer;

[0008] forming a first metal layer, wherein the first metal layer fills the first recess;

[0009] forming a second dielectric layer, wherein the second dielectric layer covers the first metal layer and the first dielectric layer; forming a second concave chamber and a through hole in communication in the second dielectric layer, wherein the through hole exposes a portion of the first metal layer;

[0010] forming a second metal layer, wherein the second metal layer fills the second recess and the through hole and is electrically connected to the first metal layer;

[0011] The stress of the first dielectric layer and the second dielectric layer are both less than 50 MPa.

[0012] Furthermore, the first dielectric layer and / or the second dielectric layer is formed by a plasma enhanced chemical vapor deposition process.

[0013] Furthermore, the reaction gases used in the plasma enhanced chemical vapor deposition include silane, ammonia and nitrogen.

[0014] Furthermore, the first dielectric layer and / or the second dielectric layer are formed by chemical vapor deposition or spin coating process.

[0015] Furthermore, forming the first dielectric layer specifically includes:

[0016] A first dielectric layer is deposited on the substrate, and a surface of the first dielectric layer is planarized by chemical mechanical polishing.

[0017] Furthermore, the dielectric constant of the first dielectric layer and / or the second dielectric layer is 6-7.

[0018] The present invention also provides a metal-oxide-metal capacitor, comprising:

[0019] A substrate, on which a first dielectric layer is formed, wherein a plurality of first recessed chambers are formed;

[0020] a first metal layer, the first metal layer filling the first recess;

[0021] a second dielectric layer, the second dielectric layer covering the first metal layer and the first dielectric layer; a second concave chamber and a through hole connected to each other are formed in the second dielectric layer, and the through hole exposes a portion of the first metal layer;

[0022] a second metal layer, the second metal layer filling the second recess and the through hole and being electrically connected to the first metal layer;

[0023] The stress of the first dielectric layer and the second dielectric layer are both less than 50 MPa.

[0024] Furthermore, the metal-oxide-metal capacitor includes: multiple metal layers; parallel finger electrodes are formed on each metal layer, and multiple metal layers are vertically stacked to form a three-dimensional structure; the finger electrodes on each metal layer are electrically connected through the plugs in the through holes.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] The present invention provides a metal-oxide-metal capacitor and a method for forming the same, the method comprising: providing a substrate, forming a first dielectric layer on the substrate, and forming a plurality of first recesses in the first dielectric layer; forming a first metal layer, the first metal layer filling the first recesses; forming a second dielectric layer, the second dielectric layer covering the first metal layer and the first dielectric layer; forming a connected second recess and a through hole in the second dielectric layer, the through hole exposing a portion of the first metal layer; forming a second metal layer, the second metal layer filling the second recess and the through hole, and being electrically connected to the first metal layer; the stress of the first dielectric layer and the second dielectric layer is less than 50MPa. The low-stress dielectric layer formed by the present invention is used as a metal interlayer film, which greatly improves the voltage ramp dielectric breakdown performance of the subsequent process, so that the device can be competent for application scenarios with high voltage requirements and expand the application range of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 The figure is a schematic flow chart of a method for forming a metal-oxide-metal capacitor according to an embodiment of the present invention.

[0028] Figure 2 FIG. 4 is a schematic diagram of a cross-sectional structure of a metal-oxide-metal capacitor according to an embodiment of the present invention.

[0029] The reference numerals are as follows:

[0030] 100 - substrate; 101 - first dielectric layer; 102 - first metal layer; 103 - second dielectric layer; 104 - second metal layer; a - plug. DETAILED DESCRIPTION

[0031] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0032] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.

[0033] The embodiment of the present invention provides a method for forming a metal-oxide-metal capacitor, such as Figure 1 As shown, including:

[0034] Step S1, providing a substrate, forming a first dielectric layer on the substrate, and forming a plurality of first concave chambers in the first dielectric layer;

[0035] Step S2, forming a first metal layer, wherein the first metal layer fills the first concave chamber;

[0036] Step S3, forming a second dielectric layer, the second dielectric layer covering the first metal layer and the first dielectric layer; forming a second concave chamber and a through hole in communication in the second dielectric layer, the through hole exposing a portion of the first metal layer;

[0037] Step S4, forming a second metal layer, the second metal layer fills the second recessed chamber and the through hole, and is electrically connected to the first metal layer;

[0038] In step S5, the stress of the first dielectric layer and the second dielectric layer are both less than 50 MPa.

[0039] The steps of the method for forming a metal-oxide-metal capacitor according to an embodiment of the present invention are described in detail below with reference to the accompanying drawings.

[0040] like Figure 2 As shown, a substrate 100 is provided. The substrate 100 may be made of a semiconductor material, such as silicon, germanium, or a compound semiconductor material, such as gallium arsenide. The substrate 100 may also be a silicon-on-insulator substrate.

[0041] The first dielectric layer 101 is formed on the substrate 100, and a plurality of first recesses are formed in the first dielectric layer 101. The first dielectric layer 101 is formed by depositing the first dielectric layer 101 on the substrate and planarizing the surface of the first dielectric layer 101 by chemical mechanical polishing.

[0042] The first metal layer 102 is formed by forming a metal material on the first dielectric layer 101 by a metal deposition process and filling the first concave chamber. The metal material is, for example, copper or tungsten. Then, a planarization process is performed, such as chemical mechanical polishing, to remove the metal material on the first dielectric layer 101, and form the first metal layer 102 in the first concave chamber.

[0043] A second dielectric layer 103 is formed, and the second dielectric layer 103 covers the first metal layer 102 and the first dielectric layer 101; and a plurality of second recessed chambers are formed in the second dielectric layer 103 by an etching process. Before or after the second recessed chambers are formed, a plurality of through holes connected to the second recessed chambers may be formed in the second dielectric layer 103 by another etching process, so that a portion of the first metal layer 102 is exposed through the second recessed chambers and the through holes.

[0044] The second metal layer 104 is formed by forming a metal material, such as copper or tungsten, on the second dielectric layer 103 by a metal deposition process, and filling the second recess and the through hole. Then, a planarization process is performed to control the depth of chemical mechanical polishing, remove the metal material on the second dielectric layer 103, and form a plug in the through hole to electrically connect the first metal layer 102 and the second metal layer 104.

[0045] In one example, the first dielectric layer 101 and / or the second dielectric layer 103 can be formed by a plasma enhanced chemical vapor deposition process. The reaction gases used in plasma enhanced chemical vapor deposition include silane, ammonia and nitrogen. The stress of the first dielectric layer 101 and the second dielectric layer 103 after film formation is less than 50MPa. The measured results of multiple wafer samples show that the dielectric layer with low stress conditions after the process is improved, and the dielectric breakdown performance of the back-end voltage ramp after process integration is greatly improved by about 20V, and the performance of the device is significantly improved in high-voltage application scenarios.

[0046] In another example, the first dielectric layer 101 and / or the second dielectric layer 103 may be formed by chemical vapor deposition or spin coating. The stress of the first dielectric layer 101 and the second dielectric layer 103 after film formation is less than 50 MPa.

[0047] Figure 2 Only two metal layers are shown, namely the first metal layer 102 and the second metal layer 104. In the metal-oxide-metal capacitor, multiple metal layers can be provided as required, and parallel finger electrodes are formed on each metal layer, and then multiple metal layers are vertically stacked to form a three-dimensional structure, and the finger electrodes on each metal layer are electrically connected through plugs between layers. The dielectric constant of the first dielectric layer and / or the second dielectric layer is 6 to 7.

[0048] The present invention also provides a metal-oxide-metal capacitor, such as Figure 2 As shown, including:

[0049] A substrate 100, on which a first dielectric layer 101 is formed, wherein a plurality of first recessed chambers are formed;

[0050] A first metal layer 102, the first metal layer 102 fills the first concave chamber;

[0051] A second dielectric layer 103, the second dielectric layer 103 covers the first metal layer 102 and the first dielectric layer 101; a second concave chamber and a through hole are formed in the second dielectric layer 103, and a portion of the first metal layer 102 is exposed through the through hole;

[0052] A second metal layer 104, the second metal layer 104 fills the second recess and the through hole and is electrically connected to the first metal layer 102;

[0053] The stress of the first dielectric layer 101 and the second dielectric layer 103 are both less than 50 MPa.

[0054] Furthermore, the metal-oxide-metal capacitor includes: multiple metal layers; parallel finger electrodes are formed on each metal layer, and multiple metal layers are vertically stacked to form a three-dimensional structure; the finger electrodes on each metal layer are electrically connected through plugs in the through holes.

[0055] In summary, the present invention provides a metal-oxide-metal capacitor and a method for forming the same, the method comprising: providing a substrate, forming a first dielectric layer on the substrate, and forming a plurality of first recesses in the first dielectric layer; forming a first metal layer, the first metal layer filling the first recesses; forming a second dielectric layer, the second dielectric layer covering the first metal layer and the first dielectric layer; forming a connected second recess and a through hole in the second dielectric layer, the through hole exposing a portion of the first metal layer; forming a second metal layer, the second metal layer filling the second recess and the through hole, and being electrically connected to the first metal layer; the stress of the first dielectric layer and the second dielectric layer is less than 50MPa. The low-stress dielectric layer formed by the present invention acts as a metal interlayer film, which greatly improves the voltage ramp dielectric breakdown performance of the subsequent process, so that the device can be competent for application scenarios with high voltage requirements, and expands the application range of the product.

[0056] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0057] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for forming a metal-oxide-metal capacitor, characterized in that: include: Providing a substrate, forming a first dielectric layer on the substrate, and forming a plurality of first recessed chambers in the first dielectric layer; forming a first metal layer, wherein the first metal layer fills the first recess; forming a second dielectric layer, wherein the second dielectric layer covers the first metal layer and the first dielectric layer; forming a second concave chamber and a through hole in communication in the second dielectric layer, wherein the through hole exposes a portion of the first metal layer; forming a second metal layer, wherein the second metal layer fills the second recess and the through hole and is electrically connected to the first metal layer; The stress of the first dielectric layer and the second dielectric layer are both less than 50 MPa.

2. The method for forming a metal-oxide-metal capacitor according to claim 1, wherein: The first dielectric layer and / or the second dielectric layer are formed by a plasma enhanced chemical vapor deposition process.

3. The method for forming a metal-oxide-metal capacitor according to claim 2, wherein: The reaction gases used in the plasma enhanced chemical vapor deposition process include silane, ammonia and nitrogen.

4. The method for forming a metal-oxide-metal capacitor according to claim 1, wherein: The first dielectric layer and / or the second dielectric layer are formed by chemical vapor deposition or spin coating process.

5. The method for forming a metal-oxide-metal capacitor according to claim 1, wherein: Forming the first dielectric layer specifically includes: The first dielectric layer is deposited on the substrate, and the surface of the first dielectric layer is planarized by chemical mechanical polishing.

6. The method for forming a metal-oxide-metal capacitor according to claim 1, wherein: The dielectric constant of the first dielectric layer and / or the second dielectric layer is 6-7.

7. A metal-oxide-metal capacitor, characterized in that: include: A substrate, on which a first dielectric layer is formed, wherein a plurality of first recessed chambers are formed; a first metal layer, the first metal layer filling the first recess; a second dielectric layer, the second dielectric layer covering the first metal layer and the first dielectric layer; A second concave chamber and a through hole are formed in the second dielectric layer, and the through hole exposes a portion of the first metal layer; a second metal layer, the second metal layer filling the second recess and the through hole and being electrically connected to the first metal layer; The stress of the first dielectric layer and the second dielectric layer are both less than 50 MPa.

8. The metal-oxide-metal capacitor according to claim 7, wherein: The metal-oxide-metal capacitor comprises: multiple metal layers; parallel finger electrodes are formed on each metal layer, and multiple metal layers are vertically stacked to form a three-dimensional structure; the finger electrodes on each metal layer are electrically connected through the plugs in the through holes.

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