A data processing apparatus and method

Abstract

The application provides a data processing device and method, which is used for extracting more abundant computing and data flow features by multi-layer IR decomposition of original application code to obtain an initial computing graph, and performing graph transformation processing on the initial computing graph to obtain a target computing graph, so that the application corresponding to the original application code can run on different systems and realize performance portability, and compared with a mode of realizing transformation by manual selection of a user, the optimization effect and efficiency of the application optimization process are improved. In the device, an input module is used to acquire original application code; a multi-layer IR decomposition module is used to decompose the original application code into multi-layer IR and determine an initial computing graph according to the multi-layer IR; a transformation module is used to perform at least one time of graph transformation processing on the initial computing graph to obtain a target computing graph; a code generation module is used to generate target application code according to the target computing graph; and an output module is used to output the target application code to a target device.

Description

[0001] This application is a divisional application, the original application number is 202110285243.4, the original application date is March 17, 2021, and the entire contents of the original application are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of computers, and in particular to a data processing device and method. BACKGROUND

[0003] Data movement is one of the main factors leading to the power consumption and application overhead of current computing systems. How to optimize data movement and maintain performance portability has always been the focus and difficulty of computing system and application design. The data-centric (DC) method can effectively reduce system power consumption and improve application performance by focusing on data movement and computation to design systems and applications.

[0004] Currently, the academic and industrial communities have carried out some research work around the DC method. The design of DC systems has become an important development trend in the future. In a typical implementation method based on DC, the original application code is converted into an intermediate representation (IR), and a computation graph is constructed based on the IR. Then, the user manually selects the transformation of the computation graph, and further converts and outputs the optimized target application code.

[0005] However, in the above implementation method, on the one hand, the user needs to deeply study these graph transformation methods and master their characteristics and usage methods, which will consume a lot of manpower and time. On the other hand, the user needs to manually select the transformation method of the computation graph combined with application optimization experience, and the optimization efficiency is low.

[0006] Therefore, how to improve the optimization efficiency of application tuning and maintain performance portability is a technical problem to be solved. SUMMARY

[0007] The embodiments of the present application provide a data processing device and method for running the application corresponding to the original application code on different systems and realizing performance portability. Compared with the method of realizing transformation by user manual selection, the optimization effect and efficiency of the application tuning process are improved.

[0008] The first aspect of the embodiment of the present application provides a data processing apparatus, which is applied to an application tuning process of an original application code, so that an application corresponding to the original application code runs on different systems and realizes performance portability. In the apparatus, an input module first acquires the original application code, the original application code is input into a multi-layer IR decomposition module in the apparatus, the original application code is decomposed into multi-layer IR in the multi-layer IR decomposition module, and an initial computation graph is determined according to the multi-layer IR; then, a transformation module in the apparatus performs at least one graph transformation process on the initial computation graph, and a target computation graph obtained is input into a code generation module in the apparatus, and a target application code is generated according to the target computation graph in the code generation module; finally, an output module in the apparatus outputs the target application code to a target device, so that the application corresponding to the target application code runs on the target device.

[0009] Based on the above technical solution, the original application code is decomposed into multi-layer IR, richer computation and data flow features are extracted to obtain an initial computation graph, and at least one graph transformation process is performed on the initial computation graph to obtain a target computation graph. That is, the original application code is automatically optimized based on DC, and at the same time, the application corresponding to the original application code runs on different systems and realizes performance portability. Compared with the mode of realizing transformation by manual selection of a user, the optimization effect and efficiency of the application tuning process are improved.

[0010] In a possible implementation manner of the first aspect of the embodiment of the present application, the transformation module is specifically configured to: perform at least one graph transformation process on the initial computation graph to obtain a graph-transformed computation graph, the graph-transformed computation graph including an original parameter; and then perform parameter transformation processing on the original parameter in code corresponding to the graph-transformed computation graph to obtain the target computation graph.

[0011] Based on the above technical solution, the transformation module in the data processing apparatus can transform the initial computation graph to obtain the target computation graph through different granularities, that is, the graph-transformed computation graph is obtained by optimizing the computation graph as the optimization granularity, and then the target computation graph is obtained by optimizing the parameter included in the graph-transformed computation graph as the optimization granularity. The transformation module respectively starts from two tuning granularities to complete automatic optimization of the initial computation graph, which can fully improve the application performance and reduce system overhead.

[0012] In a possible implementation manner of the first aspect of the embodiment of the present application, the transformation module in the data processing apparatus is specifically configured to: based on hardware information of the target device, perform parameter transformation processing on the original parameter in code corresponding to the graph-transformed computation graph to obtain the target computation graph.

[0013] Based on the above technical solution, in the process of optimizing the parameters contained in the graph-transformed computation graph as the optimization granularity, the transformation module can specifically perform parameter transformation processing on the original parameters in the code corresponding to the graph-transformed computation graph based on the hardware information of the target device, to obtain the target computation graph. The original parameters are optimized based on the hardware information of the target device to obtain the target parameters. Since the hardware information of the target device can indicate the hardware running environment of the target device, the transformed computation graph constructed is matched with the hardware running environment of the target device, and the optimization effect is further improved.

[0014] In a possible implementation manner of the first aspect of the embodiment, the multi-layer IR decomposition module in the data processing apparatus includes a first layer IR decomposition module, a second layer IR decomposition module, and a third layer IR decomposition module. The first layer IR decomposition module is configured to determine a first IR according to the original application code, the first IR including a plurality of operators. The second layer IR decomposition module is configured to construct a second IR according to the first IR, the second IR including a structured mode corresponding to the plurality of operators. The third layer IR decomposition module is configured to determine a DC primitive corresponding to the structured mode according to the second IR, the DC primitive being used to construct the initial computation graph.

[0015] Based on the above technical solution, in the process of IR decomposition of the original application code to obtain the initial computation graph, the multi-layer IR decomposition module can specifically obtain the first IR including a plurality of operators through the first IR decomposition module, obtain the second IR including a structured mode corresponding to the plurality of operators through the second IR decomposition module, and obtain the DC primitive corresponding to the structured mode and used to construct the initial computation graph through the third IR decomposition module. Compared with the manner of extracting a single-layer IR in the original application code, the initial computation graph obtained by performing multi-layer IR decomposition on the original application code can extract more abundant computation and data flow features.

[0016] In a possible implementation manner of the first aspect of the embodiment, the second IR decomposition module in the data processing apparatus is specifically configured to construct the second IR according to the first IR and the hardware information of the target device.

[0017] Based on the above technical solution, in the process of IR decomposition of the first IR to construct the second IR including a structured mode corresponding to a plurality of operators, the second IR decomposition module can construct the second IR based on the hardware information of the target device. Since the hardware information of the target device can indicate the hardware running environment of the target device, the constructed second IR is matched with the hardware running environment of the target device, and the optimization effect is further improved.

[0018] In a possible implementation of the first aspect of the embodiment of the application, the transformation module in the data processing apparatus is specifically configured to: first, decompose the initial computation graph to obtain a plurality of subgraphs; and then, perform at least one graph transformation on the plurality of subgraphs according to the preset subgraph transformation library to obtain the target computation graph.

[0019] Based on the above technical solution, in the process of performing at least one graph transformation on the initial computation graph to obtain the target computation graph, the initial computation graph can be decomposed to obtain a plurality of subgraphs, and the initial computation graph can be iteratively optimized based on the subgraph as a fine-grained optimization granularity to obtain the target computation graph. Compared with the optimization manner taking the computation graph as an optimization granularity, the optimization effect can be further improved.

[0020] In a possible implementation of the first aspect of the embodiment of the application, the transformation module in the data processing apparatus is specifically configured to: perform at least one graph transformation on the plurality of subgraphs according to the preset subgraph transformation library and a first parameter, and obtain the target computation graph, the first parameter including at least one of a transformation number, a transformation time length, a data movement overhead, and a cache miss rate.

[0021] Based on the above technical solution, in the process of performing graph transformation on the subgraph, the transformation module can perform iterative optimization according to the first parameter, and different optimization requirements can be determined by the first parameter, that is, on-demand optimization is realized in the process of performing graph transformation on the subgraph by the transformation module, and the automation degree of the optimization process is further improved.

[0022] In a possible implementation of the first aspect of the embodiment of the application, the input module in the data processing apparatus is further configured to obtain subgraph transformation update information, and the apparatus further includes an update module configured to update the preset subgraph transformation library according to the subgraph transformation update information.

[0023] Based on the above technical solution, the preset subgraph transformation library used by the transformation module can be updated based on the subgraph transformation update information, that is, the subgraph transformation library can be updated according to the experience given by an expert or the configuration customized by a user.

[0024] In a possible implementation of the first aspect of the embodiment of the application, the original application code includes at least one of a mathematical equation operator, a geometric discrete abstraction, a typical data structure, and a DC primitive.

[0025] Based on the technical solution, the original application code can include the above-mentioned multiple implementations. In order to support a wide range of computing applications, facilitate user application programming, and improve coding efficiency, a DSL interface highly abstracted and close to mathematical expression is designed and provided by analyzing and summarizing mathematical operators and data structures commonly used in a wide range of computing fields. That is, the original application code includes at least one of the following: mathematical equation operators (for example: n-order differential equation, matrix operation, LU decomposition, convolution operation, etc.), geometric discrete abstraction, typical data structures (for example: vector, two-dimensional matrix, n-dimensional matrix, tree, linked list, etc.), and DC primitives. At the same time, the input module in the data processing device also supports user-defined extension of the domain-specific language (DSL) interface to improve the adaptability of the scheme.

[0026] In a possible implementation manner of the first aspect of the embodiment of the present application, the operator includes at least one of a mathematical equation-based operator decomposition, a geometric discrete abstraction, and a basic data type.

[0027] Based on the technical solution, the operator obtained by the first IR decomposition module performing IR decomposition on the original application code can include the above-mentioned multiple implementations, that is, the first IR decomposition module obtains relevant mathematical and data information of the application by scanning keywords and key information in the original application code, to determine the first IR containing the above-mentioned multiple implementation operators.

[0028] In a possible implementation manner of the first aspect of the embodiment of the present application, the structured mode includes at least one of a Stencil mode, a Reduce mode, and a Package mode.

[0029] Based on the technical solution, the second IR is further constructed by the second IR decomposition module from the first IR, and the structured mode contained in the second IR can include the above-mentioned multiple implementations, that is, the second IR decomposition module can construct multiple different structured modes from the first IR containing multiple operators.

[0030] In a possible implementation manner of the first aspect of the embodiment of the present application, the initial computing graph includes at least one of data, data flow direction, computing task, and loop mapping.

[0031] Based on the technical solution, the third IR decomposition module determines the DC primitive corresponding to the structured mode according to the second IR, wherein the initial computing graph constructed by the DC primitive can include data, data flow direction, computing task, loop mapping, and other data-centered primitive representations, so that the initial computing graph is adapted to the DC-based application optimization scheme.

[0032] The second aspect of the embodiments of the present application provides a data processing method. The method can be applied to the process of application tuning of original application code, so that the application corresponding to the original application code runs on different systems and realizes performance portability. In the method, first, the original application code is obtained; then, the original application code is decomposed into multi-layer IR, and an initial computation graph is determined according to the multi-layer IR; after at least one graph transformation process is performed on the initial computation graph, a target computation graph is obtained, and then the target application code is generated according to the target computation graph; finally, the target application code is output to a target device.

[0033] Based on the above technical solution, the original application code is decomposed into multi-layer IR, richer computation and data flow features are extracted to obtain an initial computation graph, and at least one graph transformation process is performed on the initial computation graph to obtain a target computation graph. That is, the original application code is automatically optimized based on DC, and at the same time, the application corresponding to the original application code runs on different systems and realizes performance portability. Compared with the mode of realizing transformation by manual selection of users, the optimization effect and efficiency of the application tuning process are improved.

[0034] In a possible implementation manner of the second aspect of the embodiments of the present application, the process of performing at least one graph transformation process on the initial computation graph to obtain a target computation graph can specifically include: performing at least one graph transformation process on the initial computation graph to obtain a graph-transformed computation graph, the graph-transformed computation graph including an original parameter; and performing parameter transformation processing on the original parameter in the code corresponding to the graph-transformed computation graph to obtain the target computation graph.

[0035] Based on the above technical solution, the initial computation graph is transformed into a target computation graph at different granularities, that is, the graph-transformed computation graph is obtained by optimizing the computation graph as the optimization granularity, and then the target computation graph is obtained by optimizing the parameters included in the graph-transformed computation graph as the optimization granularity. The automatic optimization of the initial computation graph is completed from two tuning granularities, which can fully improve the application performance and reduce the system overhead.

[0036] In a possible implementation manner of the second aspect of the embodiments of the present application, the process of performing parameter transformation processing on the original parameter in the code corresponding to the graph-transformed computation graph to obtain the target computation graph can specifically include: based on the hardware information of the target device, performing parameter transformation processing on the original parameter in the code corresponding to the graph-transformed computation graph to obtain the target computation graph.

[0037] Based on the technical solution, in the process of optimizing the parameters contained in the transformed computation graph, the original parameters can be transformed based on the hardware information of the target device to obtain the target computation graph. The original parameters are optimized based on the hardware information of the target device to obtain the target parameters. The hardware information of the target device can indicate the hardware running environment of the target device, so that the transformed computation graph is matched with the hardware running environment of the target device, and the optimization effect is further improved.

[0038] In a possible implementation manner of the second aspect of the embodiment, the original application code is decomposed into multiple layers of IR, including: determining a first IR according to the original application code, the first IR including multiple operators; then, constructing a second IR according to the first IR, the second IR including a structured mode corresponding to the multiple operators; further, determining a DC primitive corresponding to the structured mode according to the second IR, the DC primitive being used to construct the initial computation graph.

[0039] Based on the technical solution, in the process of decomposing the original application code into multiple layers of IR to obtain the initial computation graph, the first IR including multiple operators, the second IR including a structured mode corresponding to the multiple operators, and the DC primitive corresponding to the structured mode and used to construct the initial computation graph can be obtained. Compared with the way of extracting a single layer of IR from the original application code, the initial computation graph obtained by decomposing the original application code into multiple layers of IR can extract more abundant computation and data flow features.

[0040] In a possible implementation manner of the second aspect of the embodiment, the second IR is constructed according to the first IR, including: constructing the second IR according to the first IR and the hardware information of the target device.

[0041] Based on the technical solution, in the process of decomposing the first IR into multiple layers of IR to obtain the second IR including a structured mode corresponding to the multiple operators, the second IR can be constructed based on the hardware information of the target device. The hardware information of the target device can indicate the hardware running environment of the target device, so that the constructed second IR is matched with the hardware running environment of the target device, and the optimization effect is further improved.

[0042] In a possible implementation manner of the second aspect of the embodiment, the process of performing at least one graph transformation on the initial computation graph to obtain the target computation graph can include: decomposing the initial computation graph to obtain multiple subgraphs, then performing at least one graph transformation on the multiple subgraphs according to a preset subgraph transformation library to obtain the target computation graph.

[0043] Based on the above technical solutions, in the process of performing at least one graph transformation on the initial computation graph to obtain the target computation graph, the initial computation graph can be decomposed to obtain a plurality of subgraphs, and the initial computation graph can be iteratively optimized based on the subgraph as a fine-grained optimization granularity to obtain the target computation graph. Compared with the optimization mode based on the computation graph as the optimization granularity, the optimization effect can be further improved.

[0044] In a possible implementation manner of the second aspect of the embodiment of the application, the at least one graph transformation is performed on the plurality of subgraphs according to the preset subgraph transformation library to obtain the target computation graph, including: performing the at least one graph transformation on the plurality of subgraphs according to the preset subgraph transformation library and a first parameter to obtain the target computation graph, the first parameter including at least one of a transformation number, a transformation time length, a data movement overhead, and a cache miss rate.

[0045] Based on the above technical solutions, in the process of performing graph transformation on the subgraph, the optimization of multiple iterations can be performed through the first parameter, and different optimization requirements can be determined through the first parameter, that is, on-demand optimization is realized in the process of performing graph transformation on the subgraph in the transformation module, and the automation degree of the optimization process is further improved.

[0046] In a possible implementation manner of the second aspect of the embodiment of the application, the method further includes: obtaining subgraph transformation update information; and updating the preset subgraph transformation library according to the subgraph transformation update information.

[0047] Based on the above technical solutions, the preset subgraph transformation library used in the subgraph transformation process can be updated based on the subgraph transformation update information, that is, the subgraph transformation library can be updated according to the experience given by an expert or the configuration customized by a user.

[0048] In a possible implementation manner of the second aspect of the embodiment of the application, the original application code includes at least one of a mathematical equation operator, a geometric discrete abstraction, a typical data structure, and a DC primitive.

[0049] Based on the above technical solution, the original application code can include the above-mentioned multiple implementations. In order to support a wide range of computing applications, facilitate user application programming, and improve coding efficiency, a DSL interface highly abstracted and close to mathematical expression is designed and provided by analyzing and summarizing mathematical operators and data structures commonly used in a wide range of computing fields. That is, the original application code includes at least one of mathematical equation operators (for example: n-order differential equation, matrix operation, LU decomposition, convolution operation, etc.), geometric discrete abstraction, typical data structures (for example: vector, two-dimensional matrix, n-dimensional matrix, tree, linked list, etc.), and DC primitives. At the same time, the input module in the data processing device also supports user-defined extension of the domain-specific language (DSL) interface to improve the adaptability of the scheme.

[0050] In a possible implementation manner of the second aspect of the embodiment of the present application, the operator includes at least one of a mathematical equation-based operator decomposition, a geometric discrete abstraction, and a basic data type.

[0051] Based on the above technical solution, the operator obtained by IR decomposition of the original application code can include the above-mentioned multiple implementations, that is, by scanning the keywords and key information in the original application code to obtain relevant mathematical and data information of the application, the first IR containing the above-mentioned multiple implementation operators is determined.

[0052] In a possible implementation manner of the second aspect of the embodiment of the present application, the structured mode includes at least one of a Stencil mode, a Reduce mode, and a Package mode.

[0053] Based on the above technical solution, the first IR is further constructed to obtain the second IR, and the structured mode contained in the second IR can include the above-mentioned multiple implementations, that is, a plurality of different structured modes can be constructed by the first IR containing a plurality of operators.

[0054] In a possible implementation manner of the second aspect of the embodiment of the present application, the first DC computation graph includes at least one of data, data flow direction, computing task, and loop mapping.

[0055] Based on the above technical solution, the DC primitive corresponding to the structured mode can be determined according to the second IR, wherein the initial computation graph constructed by the DC primitive can include data, data flow direction, computing task, loop mapping, and other data-centered primitive representations, so that the initial computation graph is adapted to the DC-based application optimization scheme.

[0056] The third aspect of the embodiments of the present application provides a data processing apparatus, comprising a processor coupled with a memory, the memory being configured to store computer programs or instructions, and the processor being configured to execute the computer programs or instructions in the memory, so that the data processing apparatus implements the method of the second aspect or any possible implementation manner of the second aspect.

[0057] The fourth aspect of the embodiments of the present application provides a computer readable storage medium storing one or more computer execution instructions, when the computer execution instructions are executed by a processor, the processor executes the method of the second aspect or any possible implementation manner of the second aspect.

[0058] The fifth aspect of the embodiments of the present application provides a computer program product storing one or more computers, when the computer program product is executed by the processor, the processor executes the method of the second aspect or any possible implementation manner of the second aspect.

[0059] The sixth aspect of the embodiments of the present application provides a chip system, comprising at least one processor configured to support the data processing apparatus to implement the functions involved in the second aspect or any possible implementation manner of the second aspect.

[0060] In a possible design, the chip system can further comprise a memory configured to store necessary program instructions and data of the data processing apparatus. The chip system can be composed of a chip, or can comprise the chip and other discrete devices. Optionally, the chip system further comprises an interface circuit configured to provide program instructions and / or data for the at least one processor.

[0061] The technical effects brought by the second aspect to the sixth aspect or any possible implementation manner thereof can be referred to the technical effects brought by the first aspect or different possible implementation manners of the first aspect, which will not be described herein again.

[0062] From the above technical solution, it can be seen that the embodiments of the present application have the following advantages: in the data processing apparatus, the input module first acquires the original application code, which is the input of the multi-layer IR decomposition module in the apparatus, the original application code is decomposed into multi-layer IR in the multi-layer IR decomposition module, and the initial calculation graph is determined according to the multi-layer IR; then, the transformation module in the apparatus performs at least one graph transformation processing on the initial calculation graph, and the target calculation graph obtained is input to the code generation module in the apparatus, and the target application code is generated according to the target calculation graph in the code generation module; finally, the output module in the apparatus outputs the target application code to the target device, so that the application corresponding to the target application code runs on the target device. Among them, by decomposing the original application code into multi-layer IR, more rich calculation and data flow features are extracted to obtain the initial calculation graph, and at least one graph transformation processing is performed on the initial calculation graph to obtain the target calculation graph. That is, the original application code is automatically optimized based on DC, and at the same time, the application corresponding to the original application code runs on different systems and realizes performance portability. Compared with the way of realizing transformation by manual selection of users, the optimization effect and efficiency of the application tuning process are improved. BRIEF DESCRIPTION OF DRAWINGS

[0063] Figure 1 One schematic diagram of the data processing method provided by the embodiments of the present application;

[0064] Figure 2 One schematic diagram of the data processing apparatus provided by the embodiments of the present application;

[0065] Figure 3 Another schematic diagram of the data processing apparatus provided by the embodiments of the present application;

[0066] Figure 4 Another schematic diagram of the data processing method provided by the embodiments of the present application;

[0067] Figure 5 Another schematic diagram of the data processing method provided by the embodiments of the present application;

[0068] Figure 6 Another schematic diagram of the data processing method provided by the embodiments of the present application;

[0069] Figure 7 Another schematic diagram of the data processing method provided by the embodiments of the present application;

[0070] Figure 8 Another schematic diagram of the data processing method provided by the embodiments of the present application;

[0071] Figure 9 Another schematic diagram of the data processing apparatus provided by the embodiments of the present application;

[0072] Figure 10 Another schematic diagram of the data processing apparatus provided by the embodiments of the present application. DETAILED DESCRIPTION

[0073] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0074] First, some terms in the embodiments of the present application are explained to facilitate the understanding of those of ordinary skill in the art.

[0075] Application: a program or a set of programs developed for users.

[0076] Computation system: a computer system that executes an application.

[0077] Data-Centric (DC): a method that focuses on data transmission and computation.

[0078] Domain specific architecture (DSA): an architecture that focuses on a specific domain.

[0079] Intermediate representation (IR): a representation that is independent of a hardware system and can describe information of source code, and is between target program code and source code.

[0080] Domain specific language (DSL): a language that abstracts operations and concepts in a specific domain.

[0081] Data flow: data transmission between different computing tasks in an application.

[0082] Data-Centric Computation Graph: a multi-graph structure used to represent computing tasks and data flow processes of an application.

[0083] Graph Transformation: a process that changes the structure of a computation graph of an application while keeping the output of the application unchanged, for example, changing the nesting order of double for loops.

[0084] Data movement is one of the main factors leading to current computing system power consumption and application overhead, and how to optimize data movement and maintain performance portability has always been the focus and difficulty of computing system and application design. The data-centric (DC) method can effectively reduce system power consumption and improve application performance by focusing on data movement and computation to design systems and applications. At present, the academic and industrial circles have carried out certain research work around the DC method, and the DC system design has become an important development trend in the future. At present, the source language corresponding program can be optimized during the optimization process of the application to improve the running efficiency of the target language corresponding program.

[0085] In the implementation of the traditional application optimization method, the input DSL application code is first converted, that is, a single level of IR decomposition is directly obtained DC computation graph, and available subgraph transformation mode is searched, and whether there is available graph transformation is determined by artificial judgment:

[0086] If it exists, the available graph transformation mode is provided for user selection, the graph transformation mode is selected manually according to the user, and the computation graph is transformed by using the graph transformation mode;

[0087] If it does not exist, the current computation graph is converted into target code and the target code is output.

[0088] In this implementation method, on the one hand, the user needs to deeply study these graph transformation modes and master their characteristics and use methods, which will consume a lot of manpower and time; on the other hand, the user needs to manually select the transformation mode of the computation graph combined with the application optimization experience, and the optimization efficiency is low.

[0089] Therefore, how to realize the optimization efficiency of the application optimization process and maintain the performance portability is a technical problem to be solved. The core problem to be solved by the present application is: for the DC automatic optimization of a wide range of computing fields, how does the original application code run on different systems to realize performance portability, and how does the performance optimization according to different systems improve the application performance.

[0090] Therefore, the embodiment of the present application provides a data processing device and method, which is used for obtaining an initial computation graph by multi-layer IR decomposition of the original application code, extracting more rich computation and data flow characteristics, and performing graph transformation processing and parameter transformation processing on the initial computation graph respectively to obtain a target computation graph, so that the application corresponding to the original application code runs on different systems and realizes performance portability. Compared with the mode of realizing transformation by manual selection of the user, the optimization effect and efficiency of the application optimization process are improved. The embodiments of the present application will be described in detail below with reference to the drawings.

[0091] Please refer to Figure 1This is a schematic diagram of a data processing method provided in an embodiment of this application, which includes the following steps.

[0092] S101. Obtain the original application code;

[0093] In this embodiment, when performing the compilation task, the data processing device obtains the original application code of the application to be optimized for compilation in step S101.

[0094] Specifically, the data processing device can be a server, data center, mobile or user equipment, network component, or a part of an execution module of such a device.

[0095] Furthermore, one implementation example of the data processing device can be achieved through... Figure 2 Indicates. For example... Figure 2 As shown, the data processing device 200 may include at least an input module 201, a multilayer IR decomposition module 202, a transformation module 203, a code generation module 204, and an output module 205. In step S101, the original application code can be obtained through the input module 201 in the data processing device 200. Since the input module 201 can obtain the original application code based on DSL, it can also be represented as a DSL interface module.

[0096] In one possible implementation, the application to be optimized can include applications in a wide range of computing fields, such as high-performance computing (HPC) applications, cloud computing applications, and AI applications. Furthermore, the original application code can also be represented as the original application's DSL code, which specifically can include at least one of the following: mathematical equation operators, geometric discrete abstractions, typical data structures, and DC primitives.

[0097] Specifically, to support a wide range of computing applications, facilitate application development, and improve coding efficiency, this embodiment analyzes and summarizes commonly used mathematical operators and data structures in various computing fields. It designs and provides a highly abstract DSL interface that closely resembles mathematical expressions, including: mathematical equation operators (e.g., n-order differential equations, matrix operations, LU decomposition, convolution operations, etc.), geometric discrete abstractions, typical data structures (e.g., vectors, two-dimensional matrices, n-dimensional matrices, trees, linked lists, etc.), and DC primitives. Furthermore, this embodiment also supports user-defined extended DSL interfaces.

[0098] Further, in the execution of step S101, the data processing apparatus can acquire, in addition to the original application code, target hardware information, which is used to indicate hardware information of a target device running the target application code compiled using the original application code. Thus, in the subsequent optimization process, targeted optimization can be performed in combination with the target hardware information, thereby improving the optimization effect.

[0099] For example, the target hardware information can include at least one of the number of central processing unit (CPU) cores, the frequency, the cache capacity at each level, the vectorization length, the memory size, the GPU memory capacity, and the like of the target device.

[0100] S102. Decompose the original application code into multiple layers of IR, and determine an initial computation graph according to the multiple layers of IR.

[0101] In this embodiment, the data processing apparatus decomposes the original application code obtained in step S101 to obtain multiple layers of IR, and determines an initial computation graph according to the multiple layers of IR. The initial computation graph can be a DC-based computation graph.

[0102] The step S102 can be implemented by Figure 2 The multi-layer IR decomposition module 202 in the data processing apparatus 200 shown in FIG. 2 decomposes the original application code obtained by the input module 201 into multiple layers of IR, and determines an initial computation graph according to the multiple layers of IR.

[0103] Specifically, in step S102, the data processing apparatus can first decompose the multiple layers of IR to obtain a first layer of IR, and then further obtain a next layer of IR according to the first layer of IR, and so on, to obtain multiple layers of IR; and further determine an initial computation graph according to the multiple layers of IR. Compared with the single layer of IR extracted in the traditional application optimization method, the original application code is decomposed into multiple layers of IR in step S102, and more abundant computation and data flow features are extracted to obtain the initial computation graph.

[0104] For example, the number of layers of the multiple layers of IR is taken as 3 layers as an example for illustration, please refer to Figure 3 , Figure 2The multi-layer IR decomposition module 202 shown at least includes a first layer IR decomposition module 2021, a second layer IR decomposition module 2022, and a third layer IR decomposition module 2023. The first layer IR decomposition module 2021 is configured to determine a first IR according to the original application code, the first IR including a plurality of operators; the second layer IR decomposition module 2022 is configured to construct a second IR according to the first IR, the second IR including a structured pattern corresponding to the plurality of operators; and the third layer IR decomposition module 2023 is configured to determine a DC primitive corresponding to the structured pattern according to the second IR, the DC primitive being used to construct the initial computation graph. Compared with the way of extracting a single-level IR in the original application code, the initial computation graph obtained by performing multi-layer IR decomposition on the original application code can extract more abundant computing and data flow features.

[0105] Figure 3 The first layer IR decomposition module 2021 shown is configured to determine a first IR corresponding to the original application code according to the original application code obtained in step S101, the first IR including a plurality of operators.

[0106] Specifically, the input of the first layer IR decomposition module 2021 is the original application code (or the DSL code of the original application), and the output is the first IR including mathematical equations, data structures, and other operators. The first IR includes operator disassembly based on mathematical equations, geometric discrete abstraction (such as the calculation method and classification of a grid), basic data types, and the like. The first layer IR decomposition module 2021 can obtain the relevant mathematical and data information of the application by scanning the keywords and key information in the original application DSL code, to determine the first IR including operators. The operators determined by the first layer IR decomposition module 2021 can come from at least one of operator disassembly based on mathematical equations, geometric discrete abstraction, and basic data types in the original application code. Since the first IR obtained by the first layer IR decomposition module 2021 includes operators, the first layer IR decomposition module 2021 can also be denoted as an operator layer module.

[0107] Figure 3 The second layer IR decomposition module 2022 shown is configured to further construct a second IR according to the first IR determined by the first layer IR decomposition module 2021, wherein the second IR includes a structured pattern corresponding to the plurality of operators in the first IR.

[0108] Specifically, the input of the second layer IR decomposition module 2022 is the first IR containing the operator, and the output is the second IR containing the best structured mode corresponding to the operator in the first IR. For example, the second IR can include the representation of typical structured modes such as Stencil mode, Reduce mode, Package mode, etc. The second layer IR decomposition module 2022 can establish the correspondence between the operator and the structured mode by combining expert experience, and automatically select the best structured mode. Since the second IR obtained by the second layer IR decomposition module 2022 includes the structured mode, the second layer IR decomposition module 2022 can also be represented as a structured mode layer module.

[0109] In a possible implementation, in addition to the first IR, the second layer IR decomposition module 2022 can also construct the second IR according to the hardware information of the target device. That is, the second IR is constructed according to the first IR and the hardware information of the target device, wherein, as described in step S101, the target hardware information is used to indicate the hardware information of the target device, so that the second IR constructed by the second layer IR decomposition module 2022 matches the hardware running environment of the target device, and the optimization effect is improved.

[0110] Figure 3 The third layer IR decomposition module 2023 is shown, which is configured to determine the DC primitive corresponding to the structured mode according to the second IR constructed by the second layer IR decomposition module 2022, and the DC primitive is used to construct the initial computing graph.

[0111] Specifically, the input of the third layer IR decomposition module 2023 is the second IR containing the structured mode, and the output is the DC primitive corresponding to the structured mode in the second IR, which is used to construct the initial computing graph. For example, the third IR can include data, data flow, computing task, loop mapping, etc. The third layer IR decomposition module 2023 further establishes a conversion library of the structured mode and the DC primitive by combining expert experience, and directly gives the IR representation and converts it into the DC computing graph. It should be noted that the third layer IR decomposition module 2023 can support user-defined and supplemented IR representation provided by each layer, and unlike the traditional application optimization method, the expert experience combined in the above content can be provided by the user. Since the third IR obtained by the third layer IR decomposition module 2023 includes the DC computing graph, the third layer IR decomposition module 2023 can also be represented as a DC primitive layer module.

[0112] For example, Figure 4 A schematic diagram of the hierarchical relationship from the computing application to the optimized implementation designed for the embodiment.

[0113] In Figure 4In the specific implementation, the original application code input to the first-layer IR decomposition module 2021 includes a plurality of mathematical equations corresponding to the computing application. For example, when the computing application is computational fluid dynamics (CFD), the corresponding mathematical equations include at least a Level Set method, a Machine Learning method, and the like; when the computing application is Machine Learning, the corresponding mathematical equations include at least a support vector machine Classification (SVM Classification), a k-means clustering algorithm (or K-Means for short), and the like. The correspondence between different applications and the plurality of mathematical equations is as shown in the following table. Figure 4 It is obvious that the original application code can also be implemented by other applications, which is not limited herein.

[0114] The operator mode layer IR (i.e., the first IR) decomposed by the first-layer IR decomposition module 2021 includes operator decomposition based on mathematical equations, geometric discrete abstraction (such as a calculation manner and classification of a grid), a basic data type, and the like. The structured mode layer IR (i.e., the second IR) decomposed by the second-layer IR decomposition module 2022 includes one or more of a plurality of structured modes as shown in the following table. Figure 4 The DC primitive layer IR (i.e., the third IR) for constructing an initial computing graph includes data, data movement, a computation task, and the like, which are data-centric primitive representations. Further, the hardware information of the foregoing target device can be represented by Figure 4 The target hardware information indicates hardware parameters possessed by the target device, for example, indicating that a chip used in the target device is Kunpeng, Ascend, or another chip.

[0115] In the embodiment, the multi-layer decomposition by the multi-layer IR decomposition module 202 is performed to obtain a multi-layer computing IR, which has algorithm and optimization separation, can abstract more rich computing and data flow features, and derives a regular, concise, and preliminarily optimized IR. In the embodiment, the computing application is parsed into the first IR corresponding to the operator mode layer module, the second IR corresponding to the structured mode layer module, and the third IR corresponding to the DC primitive layer module, and is built into the DSL design, so that the DSL code of the original application can be scanned and analyzed to obtain more rich computing and data flow features for automatic optimization in the subsequent steps.

[0116] S103. performing at least one graph transformation on the initial computation graph to obtain a target computation graph;

[0117] In this embodiment, the data processing apparatus performs at least one graph transformation on the initial computation graph determined in step S102 in step S103, i.e., performs optimization of graph transformation on the initial computation graph to obtain a target computation graph.

[0118] In step S103, the data processing apparatus can perform at least one graph transformation on the initial computation graph to obtain a target computation graph. Figure 2 As shown in the data processing apparatus 200, the transformation module 203 performs at least one graph transformation on the initial computation graph determined by the multi-layer IR decomposition module 202 to obtain a target computation graph.

[0119] In one possible implementation, the process of performing at least one graph transformation on the initial computation graph to obtain a target computation graph in step S103 can include: decomposing the initial computation graph to obtain a plurality of subgraphs; and performing at least one graph transformation on the plurality of subgraphs according to a preset subgraph transformation library to obtain a target computation graph. That is, the initial computation graph is optimized in the granularity of computation graph.

[0120] Optionally, in step S103, the initial computation graph can be iteratively transformed multiple times in the preset subgraph transformation library to obtain a final target computation graph. In step S103, the data processing apparatus can automatically perform graph transformation on the plurality of subgraphs according to the preset subgraph transformation library to obtain the second DC computation graph, which can include: performing graph transformation on the plurality of subgraphs according to the preset subgraph transformation library and a first parameter to obtain a second DC computation graph, the first parameter including at least one of transformation times, transformation duration, data movement overhead, and cache miss rate. In the process of graph transformation on the subgraph, multiple iterations of optimization can be performed in the subgraph transformation graph according to different optimization requirements, and different optimization requirements can be determined by the first parameter. Optionally, the first parameter can be preconfigured in the data processing apparatus, or can be determined by responding to the input operation of the user, or can be configured by other means, which is not limited here.

[0121] In one possible implementation, for the subgraph transformation library used in step S103, the method can further include: obtaining subgraph transformation update information; and then updating the preset subgraph transformation library according to the subgraph transformation update information. That is, the subgraph transformation library can be updated according to the experience given by experts or the configuration customized by the user.

[0122] In this embodiment, in order to support DC optimization, a subgraph decomposition and transformation library is designed in step S103, which is used to decompose the DC computation graph into several subgraphs, provide several DC optimization methods (expressed by subgraph transformation), and support user-defined and supplemented subgraph decomposition methods and subgraph transformation library. The purpose of subgraph decomposition is to divide the original computation graph into several subgraphs, and to determine whether the subgraph meets the applicability matching condition of subgraph transformation, that is, to find the available optimization method for the computation graph. The subgraph transformation library provides several subgraph transformation methods for expressing DC optimization methods, such as fusion, tile, local-storage, etc. In addition, in order to improve scalability and optimization effect, step S103 supports user-defined and supplemented subgraph decomposition methods and subgraph transformation (DC optimization method) library.

[0123] Figure 5 An example of a DC computation subgraph after vectorization transformation is shown, wherein, Figure 5 The original DC computation subgraph shown is an example of a subgraph obtained by subgraph decomposition on the initial computation graph. After graph transformation processing by the subgraph transformation library, the transformed DC computation subgraph (which is an example of the target computation graph) is obtained. In Figure 5 , the DC computation subgraph input is a one-dimensional vector, and the computation operation is bit-wise summation, which meets Vectorization. Therefore, the transformed computation subgraph omits the loop mapping process. Specifically, in Figure 5 , the code logic represented by the original DC computation subgraph is: input two one-dimensional vectors (arrays) M and N with length n, perform addition operation on the two vectors, and assign the result to vector N. As can be seen from Figure 5 , the original DC computation subgraph adds each element of M and N one by one through a layer of n times loop and assigns the result to N. Since the original computation subgraph meets the vectorization instruction supported by the target architecture, the corresponding transformation method is determined in the subgraph transformation library and after vectorization transformation, it can be seen that the transformed computation graph omits the loop operation and directly uses the vectorization instruction to add the data of vectors M and N at once and copy it to N. Further, the transformed computation graph omits the n times loop process, greatly reducing the related memory access, computation, judgment, etc. operations and instruction calls.

[0124] Further, after the initial computation graph is optimized to obtain the target computation graph in step S103 with the computation graph as the optimization granularity, since the target computation graph contains the initial parameters, i.e. the related performance parameters, the processing process can be further optimized in step S103 with the parameters as the optimization granularity. For example, please refer to Figure 3 , Figure 2The transformation module 203 shown can include a graph transformation module 2031 and a parameter transformation module 2032.

[0125] In a possible implementation, the graph transformation module 2031 is specifically configured to perform at least one graph transformation on the initial computing graph to obtain a graph-transformed computing graph, the graph-transformed computing graph including original parameters; and then the parameter transformation module 2032 performs parameter transformation on the original parameters in code corresponding to the graph-transformed computing graph to obtain the target computing graph. The transformation module in the data processing apparatus can transform the initial computing graph to obtain the target computing graph through different granularities, that is, the transformed computing graph is obtained by optimizing the computing graph as the optimization granularity, and then the parameters included in the graph-transformed computing graph are optimized as the optimization granularity to obtain the target computing graph. The transformation module completes the automatic optimization of the initial computing graph from two tuning granularities respectively, which can fully improve the application performance and reduce the system overhead.

[0126] Further, the process of optimizing the initial parameters in the code corresponding to the transformed computing graph to obtain the target computing graph including target parameters can include: optimizing the initial parameters based on the hardware information of the target device to obtain the target parameters. Since the target hardware information is used to indicate the hardware information of the target device, the transformed computing graph constructed is matched with the hardware running environment of the target device, and the optimization effect is further improved.

[0127] An exemplary, Figure 6 The framework and flow of the automatic tuning module are shown, the input of the automatic tuning engine (that is, the transformation module 203) is the DC computing graph (that is, the initial computing graph) and the hardware information of the target computing system, the subgraph transformation library applicability matching rule can be pre-stored in the data processing apparatus or input to obtain, and the output is the target computing graph obtained by the optimized graph transformation and the optimized parameter combination.

[0128] In Figure 6In the embodiment, the subgraph transformation library applicability matching rule can include subgraph transformation by eliminating redundant variables to expand a loop, subgraph transformation by GPU variable binding to merge a loop, subgraph transformation by FPGA loop optimization to exchange a loop, and subgraph transformation by MPI parallel processing to process an open multi-processing (OpenMP) parallel processing. The automatic tuning module (i.e., the transformation module 203) performs automatic optimization from two tuning granularities. First, the DC computation graph is taken as a granularity to find an optimized graph transformation combination. Then, the performance parameters exposed by the graph transformation combination are finely tuned to sufficiently improve application performance and reduce overhead. The iterative tuning process of the DC computation graph is as follows. First, subgraph decomposition and matching are performed on the current DC computation graph. Then, a solution space is constructed according to the subgraph decomposition and matching result. The solution is a usable subgraph transformation (DC optimization mode). Finally, the optimized subgraph transformation mode is searched, evaluated, and used to generate a new DC computation graph. The performance is evaluated based on the first parameter used to indicate the optimization requirement to complete multiple iterations. In addition, the fine-grained parameter tuning part supports user use of any parameter automatic tuning method, and finally outputs a target computation graph. The target computation graph includes an optimized graph transformation and an optimized parameter value combination.

[0129] S104. Generating a target application code according to the target computation graph;

[0130] In the embodiment, the data processing apparatus further generates a target application code according to the target computation graph obtained after the optimization processing in step S103. The target application code is used to run in the target device.

[0131] The step S104 can be performed by the code generation module 204 in the data processing apparatus 200 shown in FIG. 2 to process the target computation graph obtained by the transformation module 203 and generate a target application code. Figure 2 The step S104 can be performed by the code generation module 204 in the data processing apparatus 200 shown in FIG. 2 to process the target computation graph obtained by the transformation module 203 and generate a target application code.

[0132] Optionally, in step S104, when the data processing apparatus generates the target application code, the target application code can also be obtained by processing the transformed computation graph according to the hardware information of the target device. The target hardware information is used to indicate the hardware information of the target device, so that the generated target application code matches the hardware running environment of the target device, and the optimization effect is further improved.

[0133] S105. Outputting the target application code to the target device.

[0134] In the embodiment, the data processing apparatus outputs the target application code generated in step S104 to the target device in step S105, so that the target device runs the application corresponding to the target application code.

[0135] The step S105 can be performed by Figure 2 The output module 205 in the data processing apparatus 200 shown in the figure outputs the target application code generated by the code generation module 204.

[0136] Specifically, in the process of optimizing the application, the input of the data processing apparatus is the DSL code of the original application and the target hardware information, and the output is the optimized application binary for the target system structure. The workflow in the compilation process is as follows: first, the original application DSL code input by the user is subjected to multi-layered computation IR decomposition, and a DC computation graph is obtained; then, the DC computation graph is decomposed into a plurality of subgraphs; then, the automatic optimization engine automatically optimizes the DC computation graph according to the optimization modes in the subgraph transformation library, and then optimizes the related parameters exposed by the fine-grained graph transformation mode to obtain the optimal combination of graph transformation and parameter values; finally, the target code is generated for the optimized computation graph, and the application binary is compiled and output.

[0137] Please refer to Figure 7 An example of a framework to which the data processing method provided in the embodiments of the present application is applied is shown in the figure, which is a data-centric "computation-data" automatic optimization framework. The framework is used to optimize the input information such as business algorithms and hardware configurations, so that the optimal performance of the computing system can be achieved. Figure 7 In the implementation framework shown in the figure, the following implementation process is included:

[0138] The input module (i.e., the DSL interface in the figure) 201 is configured to obtain the original application code and the hardware information.

[0139] The multi-layered IR decomposition module 202 is configured to perform multi-layered computation IR decomposition on the original application code to obtain an initial computation graph expressed in the DSL-Model graph.

[0140] The transformation module 203 is configured to decompose the initial computation graph into a computation subgraph (SubGraph), and then perform subgraph transformation based on the automatic optimization engine and the subgraph transformation library to obtain a target computation graph.

[0141] The code generation module 204 is configured to generate code according to the target computation graph to obtain a target application code. The target application code can be different based on different hardware, such as one or more of the target application code (Code for Kunpeng) suitable for running on the Kunpeng chip, the target application code (Code for Ascend) suitable for running on the Ascend chip, the target application code (Code for GPU) suitable for running on the GPU, etc.

[0142] The output module 205 is configured to output the target application code to a target device, so that the target device uniformly compiles the target application code to obtain and run the optimized application binary code, and realizes that the original application code runs on different systems and realizes performance portability. Compared with the mode of realizing transformation by manual selection of a user, the optimization effect and efficiency of the application optimization process are improved.

[0143] Please refer to Figure 8 For the embodiment of the present application Figure 4 to Figure 7 A specific application example of the implementation process is shown. Figure 8 The workflow includes the following.

[0144] In the input module 201, the input is the DSL code of the application (i.e., the original application code) and the hardware information of the system. The application can be any HPC application, cloud computing application, or AI application. The hardware information includes the number of CPU cores, frequency, cache capacity at each level, vectorization length, memory size, GPU memory capacity, and the like.

[0145] In the multi-layer IR decomposition module 202, first, based on the key information of the DSL interface, the key information in the application DSL code is scanned and analyzed to construct the operator layer IR. Then, according to the system hardware information, the correspondence between the operator and the structured mode is selected to construct the structured mode layer IR. Thereafter, according to the correspondence between the structured mode and the DC primitive, the DC computation graph (i.e., the initial computation graph) is constructed.

[0146] In the transformation module 203, the DC computation graph and its parameters are automatically optimized, and the optimized graph transformation mode and parameter combination are given.

[0147] Specifically, first, the current DC computation graph is decomposed to generate a plurality of computation subgraphs. Then, the graph transformation mode in the subgraph transformation library is read. Next, according to the graph transformation mode, the DC computation subgraph is adaptively matched to find a usable graph transformation mode for the DC computation subgraph, and the solution space is constructed. Thereafter, it is determined whether the current solution space is empty, that is, whether all DC computation subgraphs do not have a usable graph transformation mode.

[0148] If the current solution space is not empty, the optimal graph transformation mode is searched and evaluated in the solution space, and the current DC computation graph is transformed. When it is determined that the current computation graph meets the optimization requirement, the fine-grained optimization process is executed. When it is determined that the current computation graph does not meet the optimization requirement, the subgraph decomposition and the solution space processing are iteratively executed.

[0149] If the current solution space is empty, fine-grained optimization is performed, that is, the performance parameters exposed by the currently used graph transformation mode are automatically optimized in combination with the target system hardware information to obtain a target computation graph.

[0150] In the code generation module 204, target code is generated according to the target computation graph combined by the optimized graph transformation mode and parameters in the transformation module 203, and binary is compiled and generated;

[0151] In the output module 205, the optimized application binary is output to the target device.

[0152] It should be noted that:

[0153] (1) Figure 8 The DSL interface, the correspondence between the structured mode and the operator, the correspondence between the structured mode and the DC primitive used in the multi-layer IR decomposition module 202, and the subgraph transformation library used in the transformation module 203 all support user-defined supplement;

[0154] (2) The judgment condition for judging whether the optimization requirement is met in the transformation module 203 is to judge whether the specified number of iterations is met (for example, whether 30 iterations are met). The judgment condition supports user modification, which can be but is not limited to: application execution time, data movement overhead, cache miss rate, etc.

[0155] (3) In the transformation module 203, the search and evaluation method used when the current solution space is not empty supports user customization and replacement. For example, the full-space search and actual measurement method can be used to evaluate the solution (subgraph available graph transformation mode).

[0156] In addition, the OpenTuner, an extensible framework for program autotuning, can be used in the transformation module 203 to automatically optimize the performance parameters. Users can use other parameter automatic tuning methods, such as ACCTuner for adjusting vector length and FAST for adjusting Stencil calculation.

[0157] In summary, the data processing apparatus and method provided by the embodiments of the present application support DC automatic optimization in a wide range of computing field applications, realize application performance portability, improve application performance, reduce power consumption overhead, reduce optimization door opening, and improve optimization efficiency. In addition, compared with traditional application tuning methods, the user does not need to accumulate and combine optimization experience to manually complete the DC optimization process, which improves the optimization efficiency. Furthermore, the DC computation graph can be automatically optimized at different granularities, not just parameter tuning, without relying on user experience. Further, a highly abstract DSL interface is provided, which can be used in a wide range of computing fields to perform multi-layer computation IR decomposition on the DSL source code, extract more rich computing and data flow features, realize automatic optimization of DC, and improve optimization effect and efficiency. The innovations and benefits of each technical point are as follows:

[0158] (1) Highly abstract and close to mathematical expression DSL interface:

[0159] By analyzing and summarizing the mathematical operators and data structures commonly used in the wide computing field, a highly abstract and close to mathematical expression DSL interface is designed and provided, including: mathematical equation operators (differential equation, LU decomposition, etc.), geometric discrete abstraction, typical data structures (vector, matrix, etc.), DC primitives, etc. Compared with the prior art, the DSL interface provided by the application is highly abstracted application computing and data flow; close to the mathematical expression method of the application, the user coding efficiency is improved; support for the expression of computing applications in a wide range of fields, wide application range.

[0160] (2) Multi-layer computing IR decomposition:

[0161] The application innovatively divides the computing application IR into three levels: operator mode layer, structured mode layer, and DC layer, and is built into the DSL design. Compared with the prior art, the application decomposes the application into the above three levels and the IR with preliminary optimization by scanning the keyword information of the DSL code of the application, combining the transformation relationship between the IRs of each level and the hardware information constructed by expert experience, and realizing the separation of algorithm and optimization, and grabbing richer computing and data flow characteristics, such as: computing equation operator, communication mode, computing mode, data flow, etc.

[0162] (3) DC automatic tuning engine:

[0163] The application first takes graph transformation as the granularity, iteratively searches, evaluates, and applies the optimized graph transformation mode by constructing the solution space, automatically selects the optimized subgraph transformation combination, and then automatically tunes the performance parameters exposed by the graph transformation. Compared with the prior art, the application realizes the automatic optimization of DC and the automatic tuning of related parameters, does not need to rely on user experience, saves the process of manual selection of graph transformation by the user, realizes the performance portability, improves the optimization efficiency, and can be used for computing applications in a wide range of fields, wide application range.

[0164] The embodiments of the application are described from the method aspect above, and the embodiments of the application are further described from the device aspect below.

[0165] Please refer to Figure 9 , the hardware structure schematic diagram of the data processing device provided by the embodiments of the application. Figure 9 The data processing device 900 (the device 900 can be a computer device specifically) shown includes a memory 901, a processor 902, a communication interface 903, and a bus 904. The memory 901, the processor 902, and the communication interface 903 are in communication connection with each other through the bus 904.

[0166] The memory 901 can be a read only memory (ROM), a static storage device, a dynamic storage device or a random access memory (RAM). The memory 901 can store programs, and when the programs stored in the memory 901 are executed by the processor 902, the processor 902 and the communication interface 903 are used to execute various steps of the model processing method of the embodiments of the present application.

[0167] The processor 902 can be a general central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU) or one or more integrated circuits, used to execute related programs to implement the functions required to be executed by the units in the data processing apparatus of the embodiments of the present application, or to execute the model processing method of the method embodiments of the present application.

[0168] The processor 902 can also be an integrated circuit chip with signal processing capability. In the implementation process, various steps of the model processing method of the present application can be completed by integrated logic circuits or instructions in the form of software in the processor 902. The processor 902 described above can also be a general processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The disclosed methods, steps and logic block diagrams in the embodiments of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as a hardware code processor to execute, or executed by a combination of hardware and software modules in the code processor. The software module can be located in a random access memory, a flash memory, a read only memory, a programmable read only memory or an electrically erasable programmable memory, a register or other mature storage medium in the art. The storage medium is located in the memory 901, and the processor 902 reads the information in the memory 901, and combines the hardware to complete the functions required to be executed by the units included in the data processing apparatus of the embodiments of the present application, or to execute the model processing method of the method embodiments of the present application.

[0169] The communication interface 903 uses a transceiving device such as, but not limited to, a transceiver, to implement communication between the device 900 and other devices or communication networks. For example, training data (such as training images according to an embodiment of the present application) can be obtained through the communication interface 903.

[0170] The bus 904 can include a path for conveying information between the various components (for example, the memory 901, the processor 902, the communication interface 903) of the device 900.

[0171] It should be noted that, although Figure 9 The device 900 shown only shows the memory, the processor, the communication interface, but in the specific implementation process, those skilled in the art should understand that the device 900 also includes other devices necessary for normal operation. At the same time, according to the specific needs, those skilled in the art should understand that the device 900 can also include hardware devices that realize other additional functions. In addition, those skilled in the art should understand that the device 900 can also only include devices necessary for realizing the embodiments of the present application, and does not have to include all the devices shown in the above. Figure 9 At the same time, the device 900 can also include hardware devices that realize other additional functions. In addition, those skilled in the art should understand that the device 900 can also only include devices necessary for realizing the embodiments of the present application, and does not have to include all the devices shown in the above.

[0172] It should be noted that, Figure 9 The data processing device shown can be used to realize the steps realized by the data processing device in the foregoing method embodiments, and realize the corresponding technical effects of the data processing device, Figure 9 The specific implementation of the data processing device shown can be referred to the description in the foregoing method embodiments, which will not be repeated here.

[0173] Please refer to Figure 10 Another schematic structural diagram of the data processing device provided in the present application, the data processing device 1000 includes a logic circuit 1001 and an input and output interface 1002. Wherein, the data processing device 1000 can be a chip or an integrated circuit.

[0174] Wherein, Figure 9 The communication interface 903 shown can be Figure 10 The input and output interface 1002 in the above, the input and output interface 1002 can include an input interface and an output interface. Or, the communication interface can also be a transceiving circuit, which can include an input interface circuit and an output interface circuit. In addition, Figure 9 The processor 902 shown can be Figure 10 The logic circuit 1001 in the above.

[0175] Specifically, the input and output interface 1002 is used to obtain the original application code, the logic circuit 1001 is used to process the original application code to obtain the target application code, and the target application code is output through the input and output interface 1002.

[0176] In a possible implementation, the logic circuit 1001 can further perform other steps executed by the processor 902 and achieve corresponding beneficial effects, and the input and output interface 1002 can further perform other steps executed by the communication interface 903 and achieve corresponding beneficial effects, which are not described herein.

[0177] In a possible implementation, the logic circuit 1001 can be a processing apparatus, and functions of the processing apparatus can be partially or entirely implemented by software.

[0178] Optionally, the processing apparatus can include a memory and a processor, where the memory is configured to store a computer program, and the processor is configured to read and execute the computer program stored in the memory to perform corresponding processing and / or steps in any one of the method embodiments.

[0179] Optionally, the processing apparatus can include only the processor. The memory for storing the computer program is located outside the processing apparatus, and the processor is connected with the memory through a circuit / wire to read and execute the computer program stored in the memory. The memory and the processor can be integrated together or can be physically independent of each other.

[0180] Optionally, the processing apparatus can be one or more chips or one or more integrated circuits. For example, the processing apparatus can be one or more field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), system on chips (SoCs), central processing units (CPUs), network processors (NPs), digital signal processors (DSPs), microcontroller units (MCUs), programmable logic devices (PLDs), or other integrated chips, or any combination of the chips or processors.

[0181] The embodiments of the present application further provide a computer readable storage medium storing one or more computer-executable instructions, which, when executed by a processor, cause the processor to perform the method of the possible implementation of the data processing apparatus in the foregoing embodiments.

[0182] The embodiment of the present application further provides a computer program product (or computer program) storing one or more computers, when the computer program product is executed by the processor, the processor executes the method of the possible implementation manners of the data processing device.

[0183] The embodiment of the present application further provides a chip system, which comprises at least one processor for supporting the terminal device to implement the functions involved in the possible implementation manners of the data processing device. Optionally, the chip system further comprises an interface circuit, which provides program instructions and / or data for the at least one processor. In a possible design, the chip system can further comprise a memory, which is used to store the necessary program instructions and data of the terminal device. The chip system can be composed of a chip, or can comprise the chip and other discrete devices.

[0184] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented by other manners. For example, the above-described device embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0185] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, can be located in one place, or can be distributed on a plurality of network units. According to actual needs, part or all of the units can be selected to achieve the purpose of the embodiment scheme.

[0186] In addition, each of the functional units in the various embodiments of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit. When the integrated unit is realized in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application, essentially or in terms of contribution to the prior art, or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods according to the various embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk, or an optical disk.

[0187] The above-described embodiments are merely used to illustrate the technical solutions of the present application, rather than limit the technical solutions; even though the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some of the technical features; and these modifications or replacements do not cause the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data processing apparatus, characterized in that, include: The multi-layer intermediate representation IR decomposition module is used to decompose the original application code into multi-layer IR and determine the initial computation graph based on the multi-layer IR. The original application code is DSL code and the initial computation graph is a DC-based computation graph. A transformation module is used to perform at least one graph transformation on the initial computation graph to obtain a target computation graph; The code generation module is used to generate target application code based on the target computation graph; The output module is used to output the target application code to the target device; The multi-layer intermediate representation IR decomposition module includes a first-layer IR decomposition module, a second-layer IR decomposition module, and a third-layer IR decomposition module; The first-layer IR decomposition module is used to determine a first IR based on the original application code, wherein the first IR includes multiple operators; The second-layer IR decomposition module is used to perform IR decomposition on the operators among the plurality of operators based on the first IR to construct a second IR, wherein the second IR includes the structured patterns corresponding to the operators among the plurality of operators; The third-layer IR decomposition module is used to determine the DC primitives corresponding to the structured pattern based on the second IR. The DC primitives are used to construct the initial computation graph. The DC primitives include primitive representations of at least one of data, data flow, computation task, and cyclic mapping.

2. The apparatus according to claim 1, characterized in that, The transformation module is specifically used for: The initial computational graph is subjected to at least one graph transformation to obtain a graph-transformed computational graph, wherein the graph-transformed computational graph includes the original parameters; In the code corresponding to the transformed computational graph, the original parameters are transformed to obtain the target computational graph.

3. The apparatus according to claim 2, characterized in that, The transformation module is specifically used for: Based on the hardware information of the target device, the original parameters are transformed in the code corresponding to the transformed computation graph to obtain the target computation graph.

4. The apparatus according to any one of claims 1 to 3, characterized in that, The second IR decomposition module is specifically used for: The second IR is constructed based on the first IR and the hardware information of the target device.

5. The apparatus according to any one of claims 1 to 3, characterized in that, The transformation module is specifically used for: The initial computation graph is decomposed to obtain multiple subgraphs; The target computation graph is obtained by performing at least one graph transformation on the multiple subgraphs according to a preset subgraph transformation library.

6. The apparatus according to claim 5, characterized in that, The transformation module is specifically used for: The target computation graph is obtained by performing at least one graph transformation on the plurality of subgraphs according to the preset subgraph transformation library and the first parameter. The first parameter includes at least one of the following: number of transformations, transformation duration, data movement overhead, and cache miss rate.

7. The apparatus according to claim 5, characterized in that, It also includes an input module for obtaining subgraph transformation update information; The device further includes: The update module is used to update the preset subgraph transformation library according to the subgraph transformation update information.

8. The apparatus according to any one of claims 1 to 3, characterized in that, The original application code includes at least one of the following: mathematical equation operators, geometric discrete abstractions, typical data structures, and DC primitives.

9. The apparatus according to any one of claims 1 to 3, characterized in that, The operator includes at least one of the following: operator decomposition based on mathematical equations, geometric discrete abstraction, and basic data types.

10. The apparatus according to any one of claims 1 to 3, characterized in that, The structured pattern includes at least one of the Stencil pattern, Reduce pattern, and Package pattern.

11. The apparatus according to any one of claims 1 to 3, characterized in that, The initial computation graph includes at least one of the following: data, data flow, computation task, and cyclic mapping.

12. A data processing method, characterized in that, include: The original application code is decomposed into multiple layers of IR, and an initial computation graph is determined based on the multiple layers of IR. The original application code is DSL code, and the initial computation graph is a DC-based computation graph. Perform at least one graph transformation on the initial computation graph to obtain the target computation graph; Generate target application code based on the target computation graph; Output the target application code to the target device; The process of decomposing the original application code into multiple layers of IR includes: A first IR is determined based on the original application code, and the first IR includes multiple operators; Based on the first IR, the operators among the plurality of operators are decomposed into IRs to construct a second IR, the second IR including the structured patterns corresponding to the operators among the plurality of operators; The DC primitives corresponding to the structured pattern are determined based on the second IR. The DC primitives are used to construct the initial computation graph. The DC primitives include primitive representations of at least one of data, data flow, computation task, and loop mapping.

13. The method according to claim 12, characterized in that, The step of performing at least one graph transformation on the initial computation graph to obtain the target computation graph includes: The initial computational graph is subjected to at least one graph transformation to obtain a graph-transformed computational graph, wherein the graph-transformed computational graph includes the original parameters; In the code corresponding to the transformed computational graph, the original parameters are transformed to obtain the target computational graph.

14. The method according to claim 13, characterized in that, The step of performing parameter transformation processing on the original parameters in the code corresponding to the transformed computation graph to obtain the target computation graph includes: Based on the hardware information of the target device, the original parameters are transformed in the code corresponding to the transformed computation graph to obtain the target computation graph.

15. The method according to any one of claims 12 to 14, characterized in that, The construction of the second IR based on the first IR includes: The second IR is constructed based on the first IR and the hardware information of the target device.

16. The method according to any one of claims 12 to 14, characterized in that, The step of performing at least one graph transformation on the initial computation graph to obtain the target computation graph includes: The initial computation graph is decomposed to obtain multiple subgraphs; The target computation graph is obtained by performing at least one graph transformation on the multiple subgraphs according to a preset subgraph transformation library.

17. The method according to claim 16, characterized in that, The step of performing at least one graph transformation on the plurality of subgraphs according to a preset subgraph transformation library to obtain the target computation graph includes: The target computation graph is obtained by performing at least one graph transformation on the plurality of subgraphs according to the preset subgraph transformation library and the first parameter. The first parameter includes at least one of the following: number of transformations, transformation duration, data movement overhead, and cache miss rate.

18. The method according to claim 16, characterized in that, The method further includes: Obtain subgraph transformation update information; The preset subgraph transformation library is updated according to the subgraph transformation update information.

19. A data processing apparatus, characterized in that, The method includes a processor coupled to a memory for storing computer programs or instructions, the processor for executing the computer programs or instructions in the memory such that the method of any one of claims 12 to 18 is performed.

20. A computer storage medium, characterized in that, The computer storage medium stores instructions that, when executed on the computer, cause the computer to perform the method as described in any one of claims 12 to 18.

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