Command transmission circuit and storage device

Abstract

The embodiment of the invention provides a command transmission circuit and a storage device. The command transfer circuit includes a shifter, a logic processing circuit, and an output circuit. The shifter is configured to receive a write command and generate a first trigger signal based on the write command. A logic processing circuit configured to logically process the first trigger signal based on the type of the write command received by the shifter to generate and output a second trigger signal; if the type of the write command is a write type after read modification, taking an effective pulse corresponding to the write command in the first trigger signal as an effective pulse of a second trigger signal; and if the type of the write command is a write-only type, delaying an effective pulse corresponding to the write command in the first trigger signal and then taking the effective pulse as an effective pulse of the second trigger signal. The output circuit is configured to sample the address information in response to the second trigger signal and the write strobe signal, and output the address information corresponding to each write command.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a command transmission circuit and a storage device. Background Art

[0002] Memory systems are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to save its data, including random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM). Non-volatile memory can save stored data when not powered, including flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), erasable programmable ROM (EPROM), resistance variable memory (such as phase change random access memory (PCRAM)), resistance random access memory (RRAM) or magnetoresistive random access memory (MRAM).

[0003] The command transmission circuit is one of the components of the storage device and is used to transmit various commands, such as transmitting various command address information. However, the current command transmission circuit has the problem of transmission error. Summary of the invention

[0004] The embodiments of the present disclosure provide a command transmission circuit and a storage device, which are at least conducive to ensuring that correct address information can be transmitted regardless of whether the write command type is a write-only type or a read-modify-write type.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a command transmission circuit, including: a shifter, configured to receive a write command and generate a first trigger signal based on the write command; wherein the write command for the same target storage body group includes a first write command and a second write command that appear in sequence, wherein the first trigger signal has a valid pulse corresponding to each of the write commands, and there is a preset time interval between adjacent valid pulses corresponding to the first write command and the second write command, and the preset time interval is determined by the type of the second write command, which is a write-only type or a read-modify-write type; a logic processing circuit, configured to, based on the The shifter performs logic processing on the first trigger signal according to the type of the write command received by the shifter to generate and output a second trigger signal; wherein, if the type of the write command is a read-modify-write type, the valid pulse corresponding to the write command in the first trigger signal is used as the valid pulse of the second trigger signal; if the type of the write command is a write-only type, the valid pulse corresponding to the write command in the first trigger signal is delayed and used as the valid pulse of the second trigger signal; the output circuit is configured to sample the address information in response to the second trigger signal and the write select signal, and output the address information corresponding to each of the write commands.

[0006] In some embodiments, the output circuit includes: a first latch, configured such that a data input terminal receives the address information, a clock terminal receives the second trigger signal, and an output terminal outputs the internal address information; a second latch, configured such that a data input terminal receives the internal address information, a clock terminal receives the write enable signal, and an output terminal outputs the address information.

[0007] In some embodiments, the address information includes storage body group address information and command address information; the output circuit also includes: a first NAND gate, whose two input ends respectively receive the storage body group address information and the command address information, and whose output end is connected to the data input end of the first latch.

[0008] In some embodiments, the logic processing circuit includes: a delay circuit, configured to receive the first trigger signal and delay the first trigger signal to generate and output a trigger delay signal; an identification signal generating circuit, configured to receive a control signal and generate an identification signal in response to the control signal, wherein the identification signal is used to characterize the type of the write command; and a processing circuit, configured to receive the first trigger signal and the trigger delay signal, and generate and output the second trigger signal in response to the identification signal.

[0009] In some embodiments, the control signal includes a first sub-control signal, a second sub-control signal and a third sub-control signal, wherein if any one of the first sub-control signal, the second sub-control signal and the third sub-control signal is valid, the identification signal indicates that the type of the write command is a read-modify-write type, and if the first sub-control signal, the second sub-control signal and the third sub-control signal are all invalid, the identification signal indicates that the type of the write command is a write-only type; the identification signal generating circuit includes: a first NOR gate, whose two input ends respectively receive the first sub-control signal and the second sub-control signal; a first inverter, whose input end receives the third sub-control signal; a second NAND gate, whose two input ends are respectively connected to the output end of the first NOR gate and the output end of the first inverter; a second inverter, whose input end is connected to the output end of the second NAND gate, and the output end of the second inverter outputs the first sub-identification signal; a third inverter, whose input end is connected to the output end of the second inverter, and the output end of the third inverter outputs the second sub-identification signal; wherein the first sub-identification signal and the second sub-identification signal constitute the identification signal.

[0010] In some embodiments, the command transmission circuit is applied to a memory; the first sub-control signal is used to indicate whether the memory has four data ports; the second sub-control signal is used to indicate whether the data burst length is determined in flight mode; and the third sub-control signal is used to indicate whether it is a partial write mode.

[0011] In some embodiments, the identification signal includes a first sub-identification signal and a second sub-identification signal that are inverted from each other, wherein when the second sub-identification signal is 1, the identification signal indicates that the type of the write command is a read-modify-write type, and when the second sub-identification signal is 0, the identification signal indicates that the type of the write command is a write-only type; the processing circuit includes: a third NAND gate, whose two input ends respectively receive the second sub-identification signal and the first trigger signal; a fourth NAND gate, whose two input ends respectively receive the first sub-identification signal and the trigger delay signal; a fifth NAND gate, whose two input ends are respectively connected to the output end of the third NAND gate and the output end of the fourth NAND gate, and the output end of the fifth NAND gate outputs the second trigger signal.

[0012] In some embodiments, the command transmission circuit further includes: a register connected between the shifter and the logic processing circuit, configured to store the address information in response to the write command; and output the stored address information in response to the first trigger signal.

[0013] In some embodiments, the address information includes storage body group address information; the command transmission circuit also includes: a selection signal generation circuit, connected between the register and the logic processing circuit, configured to receive a shift command and the address information output by the register, generate and output the write selection signal; wherein the shift command is a command obtained by the shifter shifting the write command, and the write selection signal carries the storage body group address information.

[0014] According to some other embodiments of the present disclosure, the embodiments of the present disclosure further provide a storage device, including the command transmission circuit provided by any of the above embodiments.

[0015] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0016] In the technical solution of the command transmission circuit provided by the embodiment of the present disclosure, the logic processing circuit processes the first trigger signal based on the type of the write command to generate a second trigger signal, thereby ensuring that when the types of the previous write command and the next write command are read-modify-write (RMW) type and write-only (JW) type respectively, the time interval between the valid pulse corresponding to the JW write command (i.e., the second write command, or the next write command) and the valid pulse corresponding to the RMW write command (i.e., the first write command, or the previous write command) in the second trigger signal becomes longer, and this time interval is greater than the time interval between the two valid pulses corresponding to the two write commands in the first trigger signal. In this way, the start time of the address information determined by the second write command can also have a delay, and the end time of the address information determined by the first write command can have a delay, so that the output circuit can sample and transmit the address information determined by the first write command address in response to the write selection signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and the figures in the drawings do not constitute a scale limitation unless otherwise stated. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 is a block diagram of a command transmission circuit;

[0019] Figure 2 for Figure 1 Timing diagram of the signal in the figure;

[0020] Figure 3 A block diagram of a command transmission circuit provided by an embodiment of the present disclosure;

[0021] Figure 4 for Figure 3 Timing diagram of each signal in;

[0022] Figure 5 A block diagram of an output circuit;

[0023] Figure 6 A block diagram of a logic processing circuit;

[0024] Figure 7 A circuit structure diagram of a logic processing circuit;

[0025] Figure 8 To include Figure 7 A timing diagram of multiple signals of each signal in;

[0026] Fig. 9 Another block diagram of the command transmission circuit. DETAILED DESCRIPTION

[0027] Figure 1 It is a block diagram of a command transmission circuit. Figure 2 for Figure 1 Timing diagram of the signals in .

[0028] Combined with reference Figure 1 and Figure 2 A command transmission circuit includes a decoder 10, a shifter 11, a shift register 12, a selection signal generator 13 and an output circuit 14. The decoder 12 decodes the received command to generate a write command WR_CMD, and the write command WR_CMD is processed by the shifter 11 for column address write delay (CWL, CAS Write Latency) to generate a plurality of shift commands (including a first shift command WR_CWL0_CLK and a second shift command WR_CWL8_CLK) including an internal clock FIFO_LAT_CLK. The command transmission circuit operates in response to a clock CLK, and one clock cycle of the clock CLK is 1tck.

[0029] The write command WR_CMD is also used to generate a write pointer of the shift register 12. The write counter in the shift register 12 receives the write command WR_CMD and counts to generate a write pointer IN. The FIFO (First In First Out) in the shift register 12 stores address information in response to the write pointer IN. The address information includes bank group (BG, Bank Group) address information BG, command address (CA, Command Address) information CA and storage block (BK, BNAK) address information BK, etc. The internal clock FIFO_LAT_CLK is used to generate a read pointer OUT of the shift register 12. The read counter in the shift register 12 receives the internal clock FIFO_LAT_CLK and counts to generate a read pointer OUT. The FIFO responds to the read pointer OUT to release the address information.

[0030] The strobe signal generator 13 receives the bank group address information BG released from the shift register 12, and generates a write strobe signal WCSLEN corresponding to each bank group based on the second shift command WR_CWL8_CLK generated by the shifter 11. That is, the strobe signal generator 13 combines the bank group address information with the shift command WR_CWL8_CLK to generate a write strobe signal WCSLEN with the bank group address information.

[0031] In addition, after the output circuit 14 latches the address information in response to the internal clock FIFO_LAT_CLK and holds it for a certain length of time, it transmits the address information in response to the write enable signal WCSLEN, for example, to the storage block of the corresponding storage group. Specifically, the address information is transmitted when the write enable signal WCSLEN is high and effective. Here, the certain length of time is related to the interval between two write commands WR_CMD. The specific analysis is as follows:

[0032] If the write operation is performed on the same storage body group, that is, the consecutive write commands WR_CMD are for the same storage body group, if the type of the second write command is JW (Just Write), then the timing requirement between the two consecutive write commands WR_CMD is TCCD_L_WR2 (for example, 10ns); if the type of the second write command is RMW (ReadModify Write), then the timing requirement between the two consecutive write commands WR_CMD is TCCD_L_WR (for example, 20ns), and TCCD_L_WR is greater than TCCD_L_WR2.

[0033] The internal clock signal FIFO_LAT_CLK has a valid pulse corresponding to each write command WR_CMD. When the first write command is RMW and the second command is JW, the time from the valid pulse corresponding to the first write command in the internal clock signal FIFO_LAT_CLK to the write enable signal WCSLEN signal high level effective will be slightly greater than 10ns. This is because after the first write command, there are read ECC (Error Correction Code) processing and write ECC processing, which will take some time, which will affect the normal operation of the second write command, resulting in the valid pulse of the internal clock signal FIFO_LAT_CLK generated based on the second write command cannot latch the correct storage group address information, so when the write enable signal WCSLEN is high level effective, the wrong address information is transmitted.

[0034] Specifically, refer to Figure 2 Taking the first write command as RMW and the second write command as JW as an example, when the write selection signal WCSLEN is at a valid high level, the address information BG0_CAD determined by the first write command RMW should be transmitted out. However, due to the above reasons, the address information BG0_CAD determined by the second write command JW will be transmitted out by mistake. Figure 2 In FIG. 1 , BG0 represents the memory bank group address information corresponding to a memory bank group, and BG1 represents the memory bank group address information corresponding to another memory bank group. BG_CA represents the command address information carrying all memory bank group address information, and BG0_CAD represents the command address information carrying the memory bank group address information BG0. For the convenience of illustration, Figure 2 In the figure, an arrow is shown at the transition edge of the write strobe enable signal WCSLEN, and the storage bank group address information pointed by the arrow is the address information of the sample output. It can be understood that if the arrow points to the first address information BG0_CAD, the sample outputs the correct address information; if the arrow points to the second address information BG0_CAD, the sample outputs the wrong address information.

[0035] When the second write command is RMW, since the timing requirement between the two write commands is TCCD_L_WR, and TCCD_L_WR is greater than TCCD_L_WR2, the above transmission error problem is less likely to occur in this case.

[0036] When the first write command and the second write command are both JW, since there will be no processing time occupied by reading ECC and writing ECC, the time from the valid pulse corresponding to the first write command in the internal clock signal FIFO_LAT_CLK to the high level of the write enable signal WCSLEN will be TCCD_L_WR2, which is 10ns. Therefore, the above-mentioned transmission error problem is less likely to occur.

[0037] It is understandable that the above 10ns and 20ns are only a specific example, and the specific values ​​of the above TCCD_L_WR and TCCD_L_WR2 may be set differently according to different product specification requirements of the command transmission circuit application.

[0038] Further analysis revealed that, at the transition edge of the write enable signal WCSLEN changing from the invalid level to the valid level, the address information corresponding to the first write command (the address information corresponding to the first write command is the first BG0_CAD that appears) is sampled, and the end time of the address information BG0_CAD of the first write command is aligned with the time of the appearance of the valid pulse corresponding to the second write command in the internal clock signal FIFO_LAT_CLK. As long as the end time of the address information BG0_CAD corresponding to the first write command is ensured to be later than the transition edge of the write enable signal WCSLEN, the address information BG0_CAD corresponding to the first write command can be accurately sampled. In other words, as long as the valid pulse corresponding to the second write command in the internal clock signal FIFO_LAT_CLK is later than the transition edge, that is, the time of the appearance of the valid pulse corresponding to the second write command in the internal clock signal FIFO_LAT_CLK is delayed, the address information BG0_CAD corresponding to the first write command can be accurately sampled.

[0039] Based on this, the embodiment of the present disclosure provides a command transmission circuit, which can ensure that no matter whether each write command in the continuous write commands is JW or RMW, the output circuit can transmit the correct address information.

[0040] The following will describe in detail various embodiments of the present disclosure in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed for protection in the embodiments of the present disclosure can also be implemented. It is understood that, in the absence of mutual contradiction, the aforementioned detailed descriptions of various circuits in the command transmission circuit can also be applied to the embodiments of the command transmission circuit described below.

[0041] Figure 3 A block diagram of a command transmission circuit provided in an embodiment of the present disclosure.

[0042] refer to Figure 3 The command transmission circuit includes a shifter 101, a logic processing circuit 102 and an output circuit 103.

[0043] The shifter 101 is configured to receive a write command WR_CMD and generate a first trigger signal FIFO_LAT_CLK_PRE based on the write command WR_CMD; wherein the write command WR_CMD for the same target storage body group includes a first write command and a second write command that appear in sequence, wherein the first trigger signal FIFO_LAT_CLK_PRE has a valid pulse corresponding to each write command WR_CMD, and there is a preset time interval between adjacent valid pulses corresponding to the first write command and the second write command, and the preset time interval is determined by the type of the second write command, which is a write-only type or a read-modify-write type.

[0044] The logic processing circuit 102 is configured to perform logic processing on the first trigger signal FIFO_LAT_CLK_PRE based on the type of the write command WR_CMD received by the shifter 101 to generate and output the second trigger signal INTWT_CTRL_F; wherein, if the type of the received write command WR_CMD is a read-modify-write type, then the valid pulse corresponding to the write command WR_CMD in the first trigger signal FIFO_LAT_CLK_PRE is used as the valid pulse of the second trigger signal INTWT_CTRL_F; if the type of the received write command WR_CMD is a write-only type, then the valid pulse corresponding to the write command WR_CMD in the first trigger signal FIFO_LAT_CLK_PRE is delayed and used as the valid pulse of the second trigger signal INTWT_CTRL_F.

[0045] The output circuit 103 is configured to sample the address information in response to the second trigger signal INTWT_CTRL_F and the write strobe signal WCSLEN, and output the address information corresponding to each write command WR_CMD.

[0046] In the above embodiment, the logic processing circuit 102 processes the first trigger signal FIFO_LAT_CLK_PRE based on the type of the write command WR_CMD to generate the second trigger signal INTWT_CTRL_F, thereby ensuring that when the types of two consecutive write commands WR_CMD are respectively RMW type (the corresponding write command can be referred to as RMW write command) and JW type (the corresponding write command can be referred to as JW write command), the time interval between the two valid pulses corresponding to the RMW write command and the JW write command in the second trigger signal INTWT_CTRL_F becomes longer, and this time interval is greater than the time interval between the two valid pulses corresponding to the two write commands in the first trigger signal FIFO_LAT_CLK_PRE. In this way, the start time of the address information determined by the second write command can also be delayed, and the end time of the address information determined by the first write command can be delayed, so that the output circuit 103 can transmit the address information sample determined by the first write command address in response to the write selection signal WCSLEN.

[0047] Figure 4 for Figure 3 Timing diagram of each signal in . Figure 3 In the example, BG0_CAD represents the address information to be sampled and output by the output circuit, wherein the end time of the address information BG0_CAD corresponding to the previous write command is the same as the start time of the valid pulse corresponding to the next write command in the second trigger signal INTWT_CTRL_F.

[0048] Combined with reference Figure 3 and Figure 4 , the write command WR_CMD includes a first write command, a second write command, a third write command and a fourth write command that appear in sequence. Take the type of the first write command as RMW, the type of the second write command as JW, the type of the third write command as JW, and the type of the fourth write command as RMW as an example. In the first trigger signal FIFO_LAT_CLK_PRE, the preset time interval between the valid pulses corresponding to the first write command and the second write command is the first preset duration TCCD_L_WR2, the preset time interval between the valid pulses corresponding to the second write command and the third write command is the first preset duration TCCD_L_WR2, and the preset time interval between the valid pulses corresponding to the third write command and the fourth write command is the second preset duration TCCD_L_WR. In other words, the second preset duration TCCD_L_WR is greater than the first preset duration TCCD_L_WR2. Take the first preset duration TCCD_L_WR2 as 10ns and the second preset duration TCCD_L_WR as 20ns as an example.

[0049] The valid pulse corresponding to the first write command in the second trigger signal INTWT_CTRL_F is defined as the first pulse, the valid pulse corresponding to the first write command in the first trigger signal FIFO_LAT_CLK_PRE is defined as the second pulse, and the first pulse is aligned with the second pulse. The valid pulse corresponding to the second write command in the second trigger signal INTWT_CTRL_F is defined as the third pulse, the valid pulse corresponding to the second write command in the first trigger signal FIFO_LAT_CLK_PRE is defined as the fourth pulse, and there is a delay amount t between the third pulse and the fourth pulse. The valid pulse corresponding to the third write command in the second trigger signal INTWT_CTRL_F is defined as the fifth pulse, the valid pulse corresponding to the third write command in the first trigger signal FIFO_LAT_CLK_PRE is defined as the sixth pulse, and there is a delay amount t between the fifth pulse and the sixth pulse. The valid pulse corresponding to the fourth write command in the second trigger signal INTWT_CTRL_F is defined as the seventh pulse, the valid pulse corresponding to the fourth write command in the first trigger signal FIFO_LAT_CLK_PRE is defined as the eighth pulse, and the seventh pulse is aligned with the eighth pulse.

[0050] It is not difficult to find that the time interval between adjacent valid pulses corresponding to the first write command and the second write command in the first trigger signal FIFO_LAT_CLK_PRE is the first preset time length TCCD_L_WR2, and the time interval between the valid pulses corresponding to the first write command and the second write command in the second trigger signal INTWT_CTRL_F is the third preset time length t3, and the third preset time length t3 is greater than the first preset time length TCCD_L_WR2. Taking the first preset time length as 10ns as an example, the third preset time length t3 is greater than 10ns. In this way, even if the time interval between the valid level of the write enable signal WCSLEN corresponding to the first write command and the valid pulse in the first trigger signal FIFO_LAT_CLK_PRE is greater than the first preset time length TCCD_L_WR2, it can still be ensured that the transition edge (hereinafter referred to as the transition edge) of the write enable signal WCSLEN from the invalid level to the valid level is earlier than the valid pulse corresponding to the second write command in the second trigger signal INTWT_CTRL_F, so that it is ensured that the address information BG0_CA determined for the first write command can be accurately sampled in response to the transition edge.

[0051] In the second trigger signal, the valid pulses corresponding to the second write command and the third write command are delayed relative to the valid pulse corresponding to the first trigger signal FIFO_LAT_CLK_PRE, so the time interval between adjacent valid pulses corresponding to the second write command and the third write command in the second trigger signal INTWT_CTRL_F is also the first preset duration TCCD_L_WR2. The time interval between the valid level of the write enable signal WCSLEN corresponding to the second write command and the corresponding valid pulse in the first trigger signal FIFO_LAT_CLK_PRE is the first preset duration TCCD_L_WR2. Therefore, for the second write command, the transition edge of the write enable signal WCSLEN is still earlier than the valid pulse corresponding to the third write command in the second trigger signal INTWT_CTRL_F, so that it is guaranteed that the address information BG0_CA determined by the second write command can be accurately sampled in response to the transition edge.

[0052] In the second trigger signal INTWT_CTRL_F, the valid pulse corresponding to the fourth write command is aligned with the valid pulse corresponding to the first trigger signal FIFO_LAT_CLK_PRE, so the time interval between adjacent valid pulses corresponding to the third write command and the fourth write command in the second trigger signal INTWT_CTRL_F will be less than the second preset time length TCCD_L_WR, which is the second preset time length TCCD_L_WR minus the delay amount t. However, since the second preset time length TCCD_L_WR is relatively large, even if the delay amount t is subtracted, for the third write command, the transition edge of the write selection signal WCSLEN is still earlier than the valid pulse corresponding to the fourth write command in the second trigger signal INTWT_CTRL_F, so that it is guaranteed that the address information BG0_CA determined by the third write command can be accurately sampled in response to the transition edge.

[0053] Each write command WR_CMD determines a corresponding address information, and the address information may be the address information of the storage group, that is, a write command corresponds to a corresponding storage group address information; the write enable signal WCSLEN has a valid level corresponding to each write command WR_CMD, that is, a high level, and in response to the transition edge of the write enable signal WCSLEN changing from an invalid level to a valid level, the address information corresponding to the write command WR_CMD is sampled and transmitted. The time from the valid pulse corresponding to the write command WR_CMD in the first trigger signal FIFO_LAT_CLK_PRE to the valid level of the write enable signal WCSLEN corresponding to the write command WR_CMD is the fourth preset duration t4, and the fourth preset duration t4 is the first preset duration TCCD_L_WR2 or greater than the first preset duration TCCD_L_WR2. It can be considered that each write command WR_CMD has a corresponding fourth preset duration t4. Specifically, if the type of the write command WR_CMD received by the shifter 101 is RMW, the fourth preset duration t4 corresponding to the write command WR_CMD is greater than the first preset duration TCCD_L_WR2. If the type of the write command WR_CMD received by the shifter 101 is JW, the fourth preset duration t4 corresponding to the write command WR_CMD is the first preset duration TCCD_L_WR2, that is, the fourth preset duration t4 is the same as the first preset duration TCCD_L_WR2.

[0054] It can be understood that the "first" and "second" in the first write command and the second write command are only used to distinguish the order of occurrence of two consecutive write commands, and the first one is the "first write command" and the second one is the "second write command". Then, for the second write command and the third write command, the second write command is the "first write command" and the third write command is the "second write command"; for the third write command and the fourth write command, the third write command is the "first write command" and the fourth write command is the "second write command".

[0055] That is, if the type of the received write command WR_CMD is RMW, the start time of the corresponding valid pulse in the first trigger signal FIFO_LAT_CLK_PRE is aligned with the start time of the corresponding valid pulse in the second trigger signal INTWT_CTRL_F. If the type of the received write command WR_CMD is JW, the corresponding valid pulse in the second trigger signal INTWT_CTRL_F has a delay t compared to the corresponding valid pulse in the first trigger signal FIFO_LAT_CLK_PRE. It can be understood that the setting of the delay t can be determined based on the time occupied by the processing of reading ECC and writing ECC, and the delay t can be greater than or equal to the aforementioned occupied time.

[0056] Figure 5A block diagram of an output circuit.

[0057] refer to Figure 5 The output circuit 103 may include a first latch 113 and a second latch 123. The first latch 113 is configured to receive address information at a data input terminal, receive a second trigger signal INTWT_CTRL_F at a clock terminal, and output internal address information BG0_CAD at an output terminal. The second latch 123 is configured to receive internal address information BG0_CAD at a data input terminal, receive a write enable signal WCSLEN at a clock terminal, and output address information at an output terminal.

[0058] That is, the address information is retained for a certain time by the first latch 113 to regenerate and output the internal address information BG0_CAD, and then the internal address information is sampled and output via the second latch 123 in response to the write enable signal WCSLEN.

[0059] The length of time that the first latch 113 holds the address information determined by the write command is determined by the start time of the valid pulse corresponding to the next write command in the second trigger signal INTWT_CTRL_F. When the start time of the valid pulse corresponding to the next write command comes, the first latch 113 will no longer latch the address information determined by the previous write command. In other words, the end time of the internal address information BG0_CAD is the same or substantially the same as the start time of the valid pulse corresponding to the next write command in the second trigger signal.

[0060] The first latch 113 has a positive clock end and a negative clock end, the positive clock end receives the second trigger signal INTWT_CTRL_F, and the negative clock end receives the second inverted trigger signal INTWT_CTRL_FB, and the second inverted trigger signal INTWT_CTRL_FB and the second trigger signal INTWT_CTRL_F are mutually inverted signals. The second latch 123 has a positive clock end and a negative clock end, the positive clock end receives the write enable inverted signal WCSLENB, and the negative clock end receives the write enable signal WCSLEN, and the write enable inverted signal WCSLENB and the write enable signal write enable inverted signal WCSLEN are mutually inverted signals. In addition, the inverted output end of the first latch 113 and the inverted output end of the second latch 123 can be connected to the ground terminal GND, the positive output end of the first latch 113 outputs the internal address information BG0_CAD, and the positive output end of the second latch 123 transmits the sampled address information.

[0061] The address information may include the memory bank group address information BG and the command address information CA, and the command address information CA may include the row address information and the column address information. The output circuit 103 may further include a first NAND gate 133. The two input ends of the first NAND gate 133 receive the memory bank group address information BG and the command address information CA respectively, and the output end is connected to the data input end of the first latch 113. In this way, the address information received by the data input end of the first latch 113 includes the memory bank group address information BG and the command address information CA. It can be considered that the address information received by the data input end of the first latch 113 is the command address information carrying the memory bank group address information.

[0062] In the case where the storage group address information corresponding to the write command is BG0, the address information outputted from the output terminal of the first NAND gate 133 is identified as BG_CA, and the address information outputted by the first NAND gate 133 carries the storage group address information BG0 and the storage group address information BG1. The first latch 113 outputs the corresponding internal address information BG0_CAD in response to the valid pulse of the second trigger signal INTWT_CTRL_F corresponding to the write command, and then the internal address information BG0_CAD outputted by the first latch 113 will no longer carry the storage group address information BG1, but only carry the storage group address information BG0, and therefore, the internal address information is identified as BG0_CAD.

[0063] Figure 6 A block diagram of a logic processing circuit.

[0064] refer to Figure 6 , the logic processing circuit 102 may include a delay circuit 112 , an identification signal generating circuit 122 , and a processing circuit 132 .

[0065] The delay circuit 112 is configured to receive the first trigger signal FIFO_LAT_CLK_PRE and delay the first trigger signal FIFO_LAT_CLK_PRE to generate and output the trigger delay signal FIFO_LAT_CLK_PRED. The identification signal generating circuit 122 is configured to receive a control signal (not shown) and generate an identification signal FLAG in response to the control signal, and the identification signal FLAG is used to characterize the type of the write command. The processing circuit 132 is configured to receive the first trigger signal FIFO_LAT_CLK_PRE and the trigger delay signal FIFO_LAT_CLK_PRED, and generate and output the second trigger signal INTWT_CTRL_F in response to the identification signal FLAG.

[0066] The delay circuit 112 delays each valid pulse in the first trigger signal FIFO_LAT_CLK_PRE to obtain a trigger delay signal FIFO_LAT_CLK_PRED, and delays each valid pulse by a delay amount t.

[0067] The identification signal generating circuit 122 is used to generate an identification signal FLAG representing the type of the write command. Specifically, the identification signal FLAG has a state corresponding to each write command, and based on the state of the identification signal FLAG corresponding to the write command, it can be reflected whether the type of the write command is RMW or JW.

[0068] The processing circuit 132 processes the first trigger signal FIFO_LAT_CLK_PRE and the trigger delay signal FIFO_LAT_CLK_PRED based on the identification signal FLAG to generate and output the second trigger signal INTWT_CTRL_F. Specifically, if the identification signal FLAG indicates that the type of the write command is RMW, the valid pulse corresponding to the write command in the second trigger signal INTWT_CTRL_F is aligned with the valid pulse corresponding to the write command in the first trigger signal FIFO_LAT_CLK_PRE; if the identification signal FLAG indicates that the type of the write command is JW, the valid pulse corresponding to the write command in the second trigger signal INTWT_CTRL_F is aligned with the valid pulse corresponding to the write command in the trigger delay signal FIFO_LAT_CLK_PRED.

[0069] In some examples, the control signal may include a first sub-control signal, a second sub-control signal, and a third sub-control signal, wherein if any one of the first sub-control signal, the second sub-control signal, and the third sub-control signal is valid, then the identification signal FLAG indicates that the type of the write command is a read-modify-write type; if the first sub-control signal, the second sub-control signal, and the third sub-control signal are all invalid, then the identification signal FLAG indicates that the type of the write command is a write-only type.

[0070] Figure 7 A circuit structure diagram of a logic processing circuit.

[0071] refer to Figure 7, the identification signal generating circuit 122 may include: a first NOR gate 122_1, two input ends of which respectively receive the first sub-control signal ORGX4 and the second sub-control signal OTF_FLAG; a first inverter 122_2, an input end of which receives the third sub-control signal WR_P; a second NAND gate 122_3, two input ends of which are respectively connected to the output end of the first NOR gate 122_1 and the output end of the first inverter 122_2; a second inverter 122_4, an input end of which is connected to the output end of the second NAND gate 122_3, and the output end of the second inverter 122_4 outputs the first sub-identification signal RMW_FLAG_B; a third inverter 122_5, an input end of which is connected to the output end of the second inverter 122_4, and the output end of the third inverter 122_5 outputs the second sub-identification signal RMW_FLAG_T; wherein the first sub-identification signal RMW_FLAG_B and the second sub-identification signal RMW_FLAG_T constitute the identification signal FLAG.

[0072] If the first sub-identification signal RMW_FLAG_B is 1 and the second sub-identification signal RMW_FLAG_T is 0, it indicates that the type of the write command is JW. If the first sub-identification signal RMW_FLAG_B is 0 and the second sub-identification signal RMW_FLAG_T is 1, it indicates that the type of the write command is RMW.

[0073] It can be understood that as long as at least one of the above three sub-control signals (i.e., the first sub-control signal ORGX4, the second sub-control signal OTF_FLAG and the third sub-control signal WR_P) is 1, the first sub-identification signal RMW_FLAG_B is 0, the second sub-identification signal RMW_FLAG_T is 1, that is, the type of the write command is RMW; when the above three sub-control signals are all 0, the first sub-identification signal RMW_FLAG_B is 1 and the second sub-identification signal RMW_FLAG_T is 0, that is, the type of the write command is JW.

[0074] The command transmission circuit is applied to the memory. In some examples, the first sub-control signal ORGX4 can be used to characterize whether the memory has 4 data ports (or whether the data bit width is 4-bit). If so, the first sub-control signal is valid, that is, 0; if not, the first sub-control signal is invalid, that is, 0. The second sub-control signal OTF_FLAG can be used to characterize whether the data burst length is determined in flight mode, that is, the working mode of the memory is OTF (on the fly) mode. If so, the second sub-control signal OTF_FLAG is valid, that is, 1; if not, the second sub-control signal OTF_FLAG is invalid, that is, 0. The OTF mode is also called BL16 in BL32 mode, and BL is the burst length. The third sub-control signal WR_P can be used to characterize whether it is a partial write (write paritial) mode. If so, the third sub-control signal WR_P is valid, that is, 1; if not, the third sub-control signal WR_P is invalid, that is, 0.

[0075] It should be noted that the specific composition of the above control signal is an example, and the embodiments of the present disclosure do not limit the specific composition of the control signal, and the control signal may also be composed of other sub-control signals.

[0076] In addition, it can be understood that the embodiments of the present disclosure do not limit the specific circuit structure of the identification signal generating circuit 122, and any circuit that can generate an identification signal representing the type of a write command can be applied to the embodiments of the present disclosure.

[0077] Continue to refer Figure 7 The processing circuit 132 includes: a third NAND gate 132_1, two input ends of which respectively receive the second sub-identification signal RMW_FLAG_T and the first trigger signal FIFO_LAT_CLK_PRE; a fourth NAND gate 132_2, two input ends of which respectively receive the first sub-identification signal RMW_FLAG_B and the trigger delay signal FIFO_LAT_CLK_PRED; a fifth NAND gate 132_3, two input ends of which are respectively connected to the output end of the third NAND gate 132_1 and the output end of the fourth NAND gate 132_2, and the output end of the fifth NAND gate 132_3 outputs the second trigger signal INTWT_CTRL_F.

[0078] The processing circuit 132 may further include an even number of cascaded fourth inverters 132_4, the input end of the first-stage fourth inverter 132_4 is connected to the output end of the fifth NAND gate 132_3, and the output end of the last-stage fourth inverter 132_4 outputs the second trigger signal INTWT_CTRL_F. The fourth inverter 132_4 is conducive to improving the transmission capability of the second trigger signal INTWT_CTRL_F.

[0079] Continue to refer Figure 7 The delay circuit 112 may include an even number of cascaded fifth inverters 112_1 and a delayer 112_2 connected between any two adjacent fifth inverters 112_1, the input end of the first-stage fifth inverter 112_1 receives the first trigger signal FIFO_LAT_CLK_PRE, and the last-stage fifth inverter 112_1 outputs a trigger delay signal FIFO_LAT_CLK_PRED. The delayer 112_2 performs a delay operation on the first trigger signal FIFO_LAT_CLK_PRE, and the fifth inverter 112_1 is beneficial to improving the transmission capability of the first trigger signal FIFO_LAT_CLK_PRE.

[0080] Figure 8 To include Figure 7 For simplicity, Figure 8 Only the case where the type of the first write command is RMW and the type of the second write command is JW is illustrated. And BG_CA is the first NAND gate 133 (refer to Figure 5 ) output signal.

[0081] Combined with reference Figures 3 to 8 , a JW write operation is performed on the same storage body group BG0 (that is, the type of write command is JW), and the time interval between the next write command (that is, the JW write operation) and the previous write command is the first preset time length TCCD_L_WR2, so the command address information or the storage block address information (address information determined by the previous write command) latched by the first latch 113 will be greater than the first preset time length TCCD_L_WR2, that is, the effective time length of the internal address information BG0_CAD corresponding to the previous write command is greater than the first preset time length TCCD_L_WR2, and the internal address information BG0_CAD is then sampled by the second latch 123 in response to the write enable signal WCSLEN for transmission.

[0082] As mentioned above, if the type of the first write command in two adjacent commands is RMW and the type of the second write command is JW, then the time interval between the two write commands is the first preset time length TCCD_L_WR2, and the time length of the command address information or the storage block address information latched by the first latch 112 is greater than the first preset time length TCCD_L_WR2, that is, the time length of the input signal received by the data input end of the second latch 123 is increased, so that the time interval between the effective level of the write enable signal WCSLEN, that is, the high level and the effective pulse of the first trigger signal FIFO_LAT_CLK_PRE is greater than the first preset time length TCCD_L_WR2, which can still ensure that the second latch 123 samples the correct address information in response to the write enable signal WCSLEN.

[0083] For other types of combinations between adjacent write commands, please refer to the above Figure 4 In order to avoid redundancy, the timing diagram shown will not be described in detail for each different situation. In short, when the types of the two previous and subsequent write commands are both JW, then the valid pulses of the second trigger signal INTWT_CTRL_F of the two previous and subsequent write commands are delayed relative to the valid pulses of the first trigger signal FIFO_LAT_CLK_PRE, which can also ensure that the address information determined by the previous write command is correctly transmitted. The type of the previous write command is JW, and the type of the next write command is RMW, then the valid pulse of the second trigger signal INTWT_CTRL_F of the previous write command is delayed relative to the valid pulse of the first trigger signal FIFO_LAT_CLK_PRE, and the valid pulse of the second trigger signal INTWT_CTRL_F of the previous write command is aligned with the valid pulse of the first trigger signal FIFO_LAT_CLK_PRE, but because the second preset time length TCCD_L_WR is greater than the first preset time length TCCD_L_WR2, it can still ensure that the address information determined by the previous write command is correctly transmitted.

[0084] Fig. 9 Another block diagram of the command transmission circuit.

[0085] refer to Fig. 9 The command transmission circuit may further include a register 104. The register 104 is connected between the shifter 101 and the logic processing circuit 102, and is configured to store address information in response to a write command WR_CMD; and output the stored address information in response to a first trigger signal FIFO_LAT_CLK_PRE.

[0086] The register 104 may include a first-in first-out circuit, a write counter and a read counter. The write counter is used to generate a write pointer, and the read counter is used to generate a read pointer. The first-in first-out circuit stores address information in response to the write pointer. The first-in first-out circuit releases the stored address information in response to the read pointer. The write pointer is generated based on the write command WR_CMD, and the read pointer is generated based on the first trigger signal FIFO_LAT_CLK_PRE.

[0087] It should be noted that the embodiments of the present disclosure do not limit the specific type of the register 104 , and any register that can store address information and output the stored address information based on a write command can be applied to the embodiments of the present disclosure.

[0088] Continue to refer Fig. 9The command transmission circuit may further include a strobe signal generating circuit 105. The strobe signal generating circuit 105 is connected between the register 104 and the logic processing circuit 103. The strobe signal generating circuit 105 is configured to receive a shift command WR_CWL8_CLK and address information output by the register 104, and generate and output a write strobe signal WCSLEN. The shift command is a shift command WR_CWL8_CLK obtained by shifting the write command by the shifter 101, and the write strobe signal WCSLEN carries the storage bank group address information BG.

[0089] The shift command WR_CWL8_CLK has a delay of 8tck compared to the write command WR_CMD, where 1tck is 1 clock cycle.

[0090] The strobe signal generating circuit 105 may include a latch, wherein a data input terminal of the latch receives the bank group address information BG, a clock terminal receives the shift command WR_CWL8_CLK, and a positive phase output terminal outputs a write strobe signal WCSLEN.

[0091] The command transmission circuit may further include a decoder, which receives the command and decodes it to generate a write command WR_CMD and address information, such as bank group address information BG, memory block address information BK and command address information CA.

[0092] From the foregoing analysis, it can be seen that the same command transmission circuit can be used in the embodiments of the present disclosure to solve the problem of transmitting incorrect address information when the type of the previous write command is RMW and the type of the next write command is JW, so that no matter what type of write command is, the address information determined by each write command can be correctly transmitted.

[0093] Accordingly, an embodiment of the present disclosure further provides a storage device, comprising the command transmission circuit provided by any of the above embodiments. It should be noted that the description in the above embodiments is also applicable to the embodiments of the storage device.

[0094] The storage device may be a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). In some embodiments, the storage device may be an SDRAM (Synchronous Dynamic Random Access Memory), which may be a DDR (Double Data Rate) SDRAM, such as a DDR4 memory, a DDR5 memory, a DDR6 memory, a LPDDR4 memory, a LPDDR5 memory, or a LPDDR6 memory. It is understandable that the storage device may also be a memory or a memory chip.

[0095] It should be noted that the high level and low level referred to in the above embodiments are relative concepts (i.e., the voltage value of the high level is higher than the voltage value of the corresponding low level), and neither the specific voltage value of the high level nor the specific voltage value of the low level is limited.

[0096] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A command transmission circuit, characterized in that: include: A shifter, configured to receive a write command and generate a first trigger signal based on the write command; wherein the write command for the same target memory bank group includes a first write command and a second write command that appear in sequence, wherein the first trigger signal has a valid pulse corresponding to each of the write commands, and there is a preset time interval between adjacent valid pulses corresponding to the first write command and the second write command, and the preset time interval is determined by the type of the second write command, which is a write-only type or a read-modify-write type; The logic processing circuit is configured to perform logic processing on the first trigger signal based on the type of the write command received by the shifter to generate and output a second trigger signal; wherein, if the type of the write command is a read-modify-write type, then the valid pulse corresponding to the write command in the first trigger signal is used as the valid pulse of the second trigger signal; if the type of the write command is a write-only type, then the valid pulse corresponding to the write command in the first trigger signal is delayed and used as the valid pulse of the second trigger signal; The output circuit is configured to sample the address information in response to the second trigger signal and the write enable signal, and output the address information corresponding to each of the write commands.

2. The command transmission circuit according to claim 1, characterized in that: The output circuit comprises: A first latch, configured such that a data input terminal receives the address information, a clock terminal receives the second trigger signal, and an output terminal outputs internal address information; The second latch is configured such that a data input terminal receives the internal address information, a clock terminal receives the write enable signal, and an output terminal outputs the address information.

3. The command transmission circuit according to claim 2, characterized in that: The address information includes memory bank group address information and command address information; the output circuit also includes: The first NAND gate has two input terminals respectively receiving the memory bank group address information and the command address information, and an output terminal connected to the data input terminal of the first latch.

4. The command transmission circuit according to any one of claims 1 to 3, characterized in that: The logic processing circuit comprises: a delay circuit, configured to receive the first trigger signal and delay the first trigger signal to generate and output a trigger delay signal; an identification signal generating circuit, configured to receive a control signal and generate an identification signal in response to the control signal, wherein the identification signal is used to characterize the type of the write command; The processing circuit is configured to receive the first trigger signal and the trigger delay signal, and generate and output the second trigger signal in response to the identification signal.

5. The command transmission circuit according to claim 4, characterized in that: The control signal includes a first sub-control signal, a second sub-control signal and a third sub-control signal, wherein any one of the first sub-control signal, the second sub-control signal and the third sub-control signal is valid, then the identification signal indicates that the type of the write command is a read-modify-write type, and if the first sub-control signal, the second sub-control signal and the third sub-control signal are all invalid, then the identification signal indicates that the type of the write command is a write-only type; the identification signal generating circuit includes: A first NOR gate, two input terminals of which receive the first sub-control signal and the second sub-control signal respectively; A first inverter, an input terminal of which receives the third sub-control signal; A second NAND gate, two input ends of which are respectively connected to the output end of the first NOR gate and the output end of the first inverter; a second inverter, an input end of which is connected to an output end of the second NAND gate, and an output end of the second inverter outputs a first sub-identification signal; a third inverter, an input end of which is connected to the output end of the second inverter, and an output end of the third inverter outputs a second sub-identification signal; The first sub-identification signal and the second sub-identification signal constitute the identification signal.

6. The command transmission circuit according to claim 5, characterized in that: The command transmission circuit is applied to the memory; the first sub-control signal is used to indicate whether the memory has 4 data ports; the second sub-control signal is used to indicate whether the data burst length is determined in the flight mode; the third sub-control signal is used to indicate whether it is a partial write mode.

7. The command transmission circuit according to claim 4, characterized in that: The identification signal includes a first sub-identification signal and a second sub-identification signal which are inverted from each other, wherein when the second sub-identification signal is 1, the identification signal indicates that the type of the write command is a read-modify-write type, and when the second sub-identification signal is 0, the identification signal indicates that the type of the write command is a write-only type; the processing circuit includes: a third NAND gate, two input ends of which respectively receive the second sub-identification signal and the first trigger signal; a fourth NAND gate, two input terminals of which receive the first sub-identification signal and the trigger delay signal respectively; A fifth NAND gate, wherein two input terminals are respectively connected to the output terminal of the third NAND gate and the output terminal of the fourth NAND gate, and the output terminal of the fifth NAND gate outputs the second trigger signal.

8. The command transmission circuit according to claim 1, characterized in that: The command transmission circuit also includes: The register is connected between the shifter and the logic processing circuit, and is configured to store the address information in response to the write command; and output the stored address information in response to the first trigger signal.

9. The command transmission circuit according to claim 8, characterized in that: The address information includes memory bank group address information; The command transmission circuit also includes: A write enable signal generating circuit is connected between the register and the logic processing circuit, and is configured to receive a shift command and the address information output by the register, and to generate and output the write enable signal; wherein the shift command is a command obtained by the shifter shifting the write command, and the write enable signal carries the storage body group address information.

10. A storage device, characterized in that: The method comprises the command transmission circuit as claimed in any one of claims 1 to 9.

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