Low-noise dynamic comparator based on imbalance self-calibration

Abstract

The invention relates to a low-noise dynamic comparator based on imbalance self-calibration. According to the low-noise dynamic comparator, an improved imbalance self-calibration technology is introduced by integrating an improved imbalance calibration module based on a charge pump, a calibration switch, a two-stage dynamic comparator module and a latch buffer stage module, so that the input imbalance voltage of the dynamic comparator is greatly reduced; by introducing a dummy charge pump, the grid leakage characteristics of calibration input geminate transistors are ensured to be consistent, and the calibration stability is improved; the kickback noise elimination circuit can reduce the kickback effect on comparator input; and finally, the pre-amplification stage input transconductance is optimized, so that the noise influence can be effectively reduced, kickback noise can be suppressed, the overall performance of the comparator is improved, and powerful support is provided for application in the fields of vehicle-mounted high-precision analog signal processing, analog-to-digital converters and the like.

Description

Technical Field

[0001] The present application relates to the technical field of comparators, and in particular to a low-noise dynamic comparator based on offset self-calibration. Background Art

[0002] With the continuous development and popularization of automotive electronic technology and sensor technology, analog-to-digital converters (ADCs) have important value in automotive safety applications such as tire pressure detection and speed sensing, and higher requirements are placed on their reliability. Among them, the dynamic comparator is a key component in the ADC circuit, and its performance directly affects the overall performance of the ADC. However, while pursuing high speed and low noise, traditional full-dynamic comparators often find it difficult to take into account low input offset voltage and robustness. Especially when processing high-precision (such as more than 12 bits) SAR ADCs and high voltage (such as 5 V) signals, the above problems are particularly significant, limiting their widespread application in high-end automotive sensing electronic applications. Summary of the invention

[0003] Based on this, it is necessary to provide a low-noise dynamic comparator based on offset self-calibration to address the above technical issues. The comparator combines the kickback noise elimination technology to solve the technical problem of the input offset voltage, noise, speed and input capacitance that are difficult to effectively balance in the existing full-dynamic comparator.

[0004] A low-noise dynamic comparator based on offset self-calibration comprises: an improved offset calibration module based on a charge pump, a calibration switch, a two-stage dynamic comparator module and a latch buffer stage module.

[0005] The improved offset calibration module based on the charge pump is used to ensure the power-on process of the calibration capacitor by introducing the bootstrap pre-charging method of the lower board when entering the calibration stage, and establish the calibration voltage and the calibration reference voltage according to the reference voltage; in the offset calibration stage, the signal output by the latch buffer stage module is controlled by the current source through the feedback mechanism to charge or discharge the calibration capacitor; and after the calibration is completed, a dummy charge pump is used to maintain the calibrated offset voltage stored in the calibration capacitor.

[0006] The calibration switch is used to transmit the reference voltage information to the two input terminals of the two-stage dynamic comparator module when the calibration module enable signal en_cal is valid; and to transmit the input signal to the two input terminals of the two-stage dynamic comparator module when the calibration module enable signal en_cal is invalid.

[0007] The two-stage dynamic comparator module is used to receive the input signal in the comparison stage, eliminate the kickback noise, and then process it through the first stage pre-amplifier stage. The positive and negative signals output by the first stage pre-amplifier stage are used to directly drive the second stage output lock storage stage to output the negative signal V onand the positive signal V op To the latch buffer stage module, Latch buffer module for negative signal V on and the positive signal V op Perform latch buffering, filter out signal glitches, and output comparison results.

[0008] In one embodiment, an improved offset calibration module based on a charge pump includes: a Dummy charge pump and an offset calibration circuit.

[0009] The dummy charge pump includes a charging current source, a discharging current source, MOS tubes Mc1 and Mc2, dummy tubes Mc1d and Mc1d, a reset tube M3d, a second calibration capacitor and an OR gate; the gate of the MOS tube Mc1 is connected to the vddh terminal, the source of the MOS tube Mc1 is connected to one end of the charging current source, the drain of the MOS tube Mc1 is connected to the source of the dummy tube Mc1d, the other end of the charging current source is connected to the vddh terminal, the gate of the dummy tube Mc1d is grounded, the drain of the dummy tube Mc1d is connected to the drain of the dummy tube Mc2d, the gate of the dummy tube Mc2d is connected to the vddh terminal, the source of the dummy tube Mc2d is connected to one end of the discharging current source, and the other end of the discharging current source is grounded; the two ends of the second correction capacitor are respectively connected to the drain and source of the reset tube M3d, the drain of the reset tube M3d is connected to the drain of the dummy tube Mc1d, and the source of the reset tube M3d receives the reference voltage V cm The gate of the reset tube M3d is connected to the output of the OR gate, and the input of the OR gate is used to receive the calibration module enable signal en_cal and the capacitor reset signal enb; the drain of the reset tube M3d outputs the calibration reference voltage V cm_cal To the two-stage dynamic comparator module.

[0010] The offset calibration circuit includes: a first charging current source, a first discharging current source, MOS tubes Mc3 and Mc4, dummy tubes Mc3d and Mc4d, a reset tube M4d, a first calibration capacitor, two NOT gates and four AND gates.

[0011] The two input ends of the first AND gate are used to receive the calibration module enable signal en_cal and the dynamic comparator enable signal en_cmp, and its output end is connected to the first input end of the second AND gate. The second input end of the second AND gate is used to receive the clock clk signal. The output end of the second AND gate is connected to one input end of the third and fourth AND gates, and the other input end of the third AND gate is used to receive the signal V op_cmp , the other input of the fourth AND gate is used to receive the signal V on_cmpThe output end of the third AND gate is connected to the input end of the first NOT gate, the output end of the first NOT gate is connected to the gate of the MOS tube Mc3, the source of the MOS tube Mc3 is connected to one end of the first charging power supply, the other end of the first charging power supply is connected to the vddh end, the drain of the MOS tube Mc3 is connected to the source of the dummy tube Mc3d, the source and drain of the dummy tube Mc3d are connected, the drain of the dummy tube Mc3d is connected to the drain of the dummy tube Mc4d, the drain and source of the dummy tube Mc4d are connected, the source of the dummy tube Mc4d is connected to the drain of the MOS tube Mc4 The source of the MOS tube Mc4 is connected to one end of the first discharge current source, the other end of the first discharge current source is grounded, the output end of the third AND gate is connected to the gate of the dummy tube Mc3d, the output end of the fourth AND gate is connected to the gate of the MOS tube Mc4, the output end of the first NOT gate is connected to the gate of the MOS tube Mc3, the output end of the second NOT gate is connected to the gate of the dummy tube Mc4d, the two ends of the first calibration capacitor are respectively connected to the source and drain of the reset tube M4d, the gate of the reset tube M4d is used to receive the capacitor reset signal enb, and the source of the reset tube M4d receives the reference voltage V cm , the drain of reset tube M4d outputs the calibration voltage V cal To the two-stage dynamic comparator module.

[0012] In one embodiment, the calibration switch includes: four transmission gates and a first NOT gate.

[0013] The input end of the first NOT gate receives the calibration module enable signal en_cal, and the output end of the first NOT gate is connected to the forward enable end of the first transmission gate, the reverse enable end of the second transmission gate, the forward enable end of the third transmission gate, and the reverse enable end of the fourth transmission gate; the reverse enable end of the first transmission gate, the forward enable end of the second transmission gate, the reverse enable end of the third transmission gate, and the forward enable end of the fourth transmission gate receive the calibration module enable signal en_cal.

[0014] The first transmission gate input is used to receive the positive input signal V ip The output of the first transmission gate is connected to the output of the second transmission gate, and the connection point outputs the inp signal to the two-stage dynamic comparator module; the input of the second transmission gate and the fourth transmission gate receives the reference voltage V cm ; The input of the third transmission gate is used to receive the negative input signal V in ; The output end of the third transmission gate is connected to the output end of the fourth transmission gate, and the connection point outputs the inn signal to the two-stage dynamic comparator module.

[0015] In one embodiment, a two-stage dynamic comparator module includes a kick-back noise elimination circuit, a pseudo-differential pre-amplification stage, and an output amplifier stage.

[0016] The kick-back noise elimination circuit is used to eliminate the kick-back noise of the pseudo-differential pre-amplification stage.

[0017] The pseudo differential pre-amplifier stage is used to perform a differential amplification on the signal selected by the calibration switch and output the first positive signal V dp and the first negative signal V dn , and is also used to compensate for input offset voltage by introducing an unbalanced transconductance current.

[0018] The output amplifier stage is used to adopt the first positive signal V dp and the first negative signal V dn Direct drive, perform secondary amplification on the comparison result of the pseudo differential pre-amplifier output, and output a negative signal V on and the positive signal V op To the latch buffer stage module.

[0019] In one embodiment, the kickback noise elimination circuit includes: a MOS transistor M1n, a MOS transistor M6n, a MOS transistor M2n, a MOS transistor M3n, a MOS transistor M4n and a MOS transistor M5n; wherein the MOS transistor M1n, the MOS transistor M2n and the MOS transistor M3n are P-type MOS transistors, and the MOS transistor M4n, the MOS transistor M5n and the MOS transistor M6n are N-type MOS transistors.

[0020] The drain of the MOS transistor M2n is connected to the drain of the MOS transistor M4n, the source of the MOS transistor M2n is connected to the drain of the MOS transistor M1n, the source of the MOS transistor M1n is connected to the vddh terminal, the gate of the MOS transistor M1n is used to receive the opposite phase driving clock clk, the source of the MOS transistor M4n is connected to the drain of the MOS transistor M6n, the source of the MOS transistor M6n is grounded, the gates of the MOS transistors M1n and M6n are both used to receive the opposite phase driving clock clk, the source of the MOS transistor M3n is connected to the source of the MOS transistor M2n, the source of the MOS transistor M4n is connected to the source of the MOS transistor M5n, the gates of the MOS transistors M2n and M4n are connected to the positive input terminal of the pseudo differential pre-amplifier stage, and the gates of the MOS transistors M3n and M5n are connected to the negative input terminal of the pseudo differential pre-amplifier stage.

[0021] In one embodiment, the pseudo differential pre-amplification stage includes: MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M2c, MOS tube M3c, MOS tube M4c, MOS tube M5c, The source of the MOS transistor M1 is connected to the vddh terminal, the gate of the MOS transistor M1 receives the first clock signal clka, and the sources of the MOS transistors M2c, M2, M3 and M3c are all connected to the drain of the MOS transistor M1.

[0022] The gate of MOS tube M2c receives the calibration reference voltage V cm_cal , the gate of MOS tube M2c is connected to the gate of MOS tube M4c, the drain of MOS tube M2c is connected to the drain of MOS tube M4c, the source of MOS tube M4c is connected to the source of MOS tube M4, the drain of MOS tube M2 is connected to the drain of MOS tube M4, the gate of MOS tube M2 is connected to the gate of MOS tube M4, the gate of MOS tube M4 is connected to the positive output end of the kick-back noise elimination circuit, the source of MOS tube M4 is connected to the drain of MOS tube M6, the source of MOS tube M6 is connected to the source of MOS tube M7, the source of MOS tube M7 is grounded, the gate of MOS tube M6 is connected to the gate of MOS tube M7, the gate of MOS tube M6 receives the first clock signal clka, the drain of MOS tube M2c is connected to the negative input end V of the output amplifier stage dn connect.

[0023] The drain of MOS tube M3 is connected to the drain of MOS tube M5, the gate of MOS tube M3 is connected to the gate of MOS tube M5, the source of MOS tube M5 is connected to the drain of MOS tube M7; the drain of MOS tube M3c is connected to the drain of MOS tube M5c, the gate of MOS tube M3c is connected to the gate of MOS tube M5c, and the gate of MOS tube M3c receives the calibration voltage V cal The source of MOS tube M5c is connected to the source of MOS tube M5; the drain of MOS tube M5 is connected to the negative output terminal of the kickback noise elimination circuit; the drain of MOS tube M3c is connected to the negative input terminal V dp connect.

[0024] In one embodiment, the first clock signal clka is obtained by processing the clock signal clk and the enable signal en_cmp of the dynamic comparator through an AND gate and then through an inverter.

[0025] In one embodiment, the output amplifier stage includes: MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16 and MOS tube M17.

[0026] The gate of MOS tube 10 receives the negative output signal V of the pseudo differential pre-amplifier stage. dnThe gate of MOS tube 10 and the gate of MOS tube 14 are connected to the gate of MOS tube M8, the source of MOS tube M10 is connected to the vddh terminal, the drain of MOS tube M10 is connected to the source of MOS tube M12 and the drain of MOS tube M8, the source of MOS tube M8 is connected to the source of MOS tube M9, and the source of MOS tube M8 is grounded; the source of MOS tube M14 and the source of MOS tube M16 are both connected to the vddh terminal, the drain of MOS tube M16 is connected to the drain of MOS tube M12, the gate of MOS tube M16 is connected to the gate of MOS tube M12, the drain of MOS tube M14 is connected to the drain of MOS tube M16 and the gate of MOS tube M17, and the drain of MOS tube M14 outputs a positive signal V op To the latch buffer stage module.

[0027] The source of the MOS tube M17 and the source of the MOS tube M15 are both connected to the vddh terminal, the gate of the MOS tube M17 is connected to the gate of the MOS tube M13, the drain of the MOS tube M17 is connected to the drain of the MOS tube M13, the source of the MOS tube M13 is connected to the drain of the MOS tube M9, the drain of the MOS tube M9 is connected to the drain of the MOS tube M11, the source of the MOS tube M11 is connected to the vddh terminal, and the gates of the MOS tube M15, the MOS tube M11 and the MOS tube M9 are all connected to the positive output signal V of the pseudo differential pre-amplifier stage. dp The gate of MOS tube M16 is connected to the drain of MOS tube M17 and the drain of MOS tube M15, and the drain of MOS tube M15 outputs a negative signal V on To the latch buffer stage module.

[0028] In one embodiment, the latch buffer stage module includes two buffers and a NAND latch structure.

[0029] The NAND gate latch structure includes two NAND gates and two NOT gates; the output end of the first NAND gate is connected to an input end of the second NAND gate, the output end of the second NAND gate is connected to an input end of the first NAND gate, the second input end of the first NAND gate and the second input end of the second NAND gate both receive an enable signal en_cmp of the dynamic comparator; the output end of the first NAND gate is connected to the input end of the first NOT gate, and the output end of the second NAND gate is connected to the input end of the second NOT gate.

[0030] The first buffer input is used to receive the negative signal V on The output of the first buffer is connected to the third input of the first NAND gate, and the first NAND gate outputs the negative signal V of the comparison result. on_cmp .

[0031] The second buffer input is used to receive the positive signal Vop The output of the second buffer is connected to the third input of the second NAND gate, and the second NAND gate outputs the positive signal V of the comparison result. op_cmp .

[0032] The above-mentioned low-noise dynamic comparator based on offset self-calibration, the low-noise dynamic comparator introduces an improved offset self-calibration technology by integrating an improved offset calibration module based on a charge pump, a calibration switch, a two-stage dynamic comparator module and a latch buffer stage module, thereby greatly reducing the input offset voltage of the dynamic comparator; by introducing a dummy charge pump, the gate leakage characteristics of the calibration input pair tube are guaranteed to be consistent, thereby improving the stability of the calibration; the designed kickback noise elimination circuit can reduce the kickback effect on the comparator input; finally, optimizing the input transconductance of the pre-amplifier stage can effectively reduce the noise impact and suppress the kickback noise, thereby improving the overall performance of the comparator, and providing strong support for applications in the fields of vehicle-mounted high-precision analog signal processing and analog-to-digital converters. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a structural block diagram of a low-noise dynamic comparator based on offset self-calibration in one embodiment; Figure 2 It is a principle block diagram of an improved offset calibration module in another embodiment; Figure 3 A block diagram of a calibration switch in another embodiment; Figure 4 is a principle block diagram of a two-stage dynamic comparator module in another embodiment; Figure 5 It is a functional block diagram of a latch buffer stage module in another embodiment; Figure 6 A schematic diagram of an uncalibrated input offset voltage in another embodiment; Figure 7 FIG. 1 is a schematic diagram of input offset voltage after calibration in another embodiment. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0035] In one embodiment, Figure 1 As shown, a low noise dynamic comparator based on offset self-calibration is provided, which includes: an improved offset calibration module 10 based on a charge pump, a calibration switch 20, a two-stage dynamic comparator module 30 and a latch buffer stage module 40.

[0036] The improved offset calibration module 10 based on the charge pump is used to ensure the power-on process of the calibration capacitor by introducing the bootstrap pre-charging method of the lower board when entering the calibration stage, and establish the calibration voltage and the calibration reference voltage according to the reference voltage; in the offset calibration stage, the signal output by the latch buffer stage module is controlled by the current source through the feedback mechanism to charge or discharge the calibration capacitor; and after the calibration is completed, a dummy charge pump is used to maintain the calibrated offset voltage stored in the calibration capacitor.

[0037] The calibration switch 20 is used to transmit the reference voltage information to the two input terminals of the two-stage dynamic comparator module when the calibration module enable signal en_cal is valid; and to transmit the input signal to the two input terminals of the two-stage dynamic comparator module when the calibration module enable signal en_cal is invalid.

[0038] The two-stage dynamic comparator module 30 is used to receive the input signal in the comparison stage, eliminate the kickback noise, and then process it through the first stage pre-amplifier stage, using the positive and negative output signals of the first stage pre-amplifier stage to directly drive the second stage output lock storage amplification stage, and output a negative signal V on and the positive signal V op To the latch buffer stage module, The latch buffer module 40 is used to latch the negative signal V on and the positive signal V op Perform latch buffering, filter out signal glitches, and output comparison results.

[0039] Specifically, the low-noise dynamic comparator based on offset self-calibration can enter two working states: calibration state and comparison state. In the calibration state, the improved offset calibration module 10 based on the charge pump starts to work, so that the comparator input offset voltage is gradually calibrated to zero; after the calibration is completed, it enters the normal comparison state.

[0040] In the above-mentioned low-noise dynamic comparator based on offset self-calibration, the low-noise dynamic comparator introduces an improved offset self-calibration technology by integrating an improved offset calibration module based on a charge pump, a calibration switch, a two-stage dynamic comparator module and a latch buffer stage module, thereby greatly reducing the input offset voltage of the dynamic comparator; by introducing a dummy charge pump, the gate leakage characteristics of the calibration input pair tube are guaranteed to be consistent, thereby improving the stability of the calibration; the designed kickback noise elimination circuit can reduce the kickback effect on the comparator input; finally, optimizing the input transconductance of the pre-amplifier stage can effectively reduce the noise impact and suppress the kickback noise, thereby improving the overall performance of the comparator, and providing strong support for applications in the fields of vehicle-mounted high-precision analog signal processing and analog-to-digital converters.

[0041] In one embodiment, if Figure 2As shown, the improved offset calibration module based on the charge pump includes: a Dummy charge pump and an offset calibration circuit.

[0042] Dummy charge pump includes charging current source i chg , discharge current source i dischg , MOS tubes Mc1 and Mc2, dummy tubes Mc1d and Mc1d, reset tube M3d, a second calibration capacitor Ccal2 and an OR gate OR1; the gate of MOS tube Mc1 is connected to the vddh terminal, the source of MOS tube Mc1 is connected to one end of the charging current source, the drain of MOS tube Mc1 is connected to the source of dummy tube Mc1d, the other end of the charging current source is connected to the Vddh terminal, the gate of dummy tube Mc1d is grounded, the drain of dummy tube Mc1d is connected to the drain of dummy tube Mc2d, the gate of dummy tube Mc2d is connected to the vddh terminal, the source of dummy tube Mc2d is connected to one end of the discharge current source, and the other end of the discharge current source is grounded; the two ends of the second correction capacitor are respectively connected to the drain and source of reset tube M3d, the drain of reset tube M3d is connected to the drain of dummy tube Mc1d, and the source of reset tube M3d receives the reference voltage V cm The gate of the reset tube M3d is connected to the output of the OR gate, and the input of the OR gate is used to receive the calibration module enable signal en_cal and the capacitor reset signal enb; the drain of the reset tube M3d outputs the calibration reference voltage V cm_cal To the two-stage dynamic comparator module.

[0043] The offset calibration circuit includes: a first charging current source i chg1 , the first discharge current source i dischg1 , MOS tubes Mc3 and Mc4, dummy tubes Mc3d and Mc4d, reset tube M4d, first calibration capacitor C cal1 , two NOT gates, and four AND gates.

[0044] The two input terminals of the first AND gate U1 are used to receive the calibration module enable signal en_cal and the dynamic comparator enable signal en_cmp , its output end is connected to the first input end of the second AND gate U2, the second input end of the second AND gate U2 is used to receive the clock clk signal, the output end of the second AND gate U2 is connected to the third AND gate U3 and one input end of the fourth AND gate U4, the other input end of the third AND gate U3 is used to receive the signal V op_cmp , the other input terminal of the fourth AND gate U4 is used to receive the signal V on_cmpThe output end of the third AND gate U3 is connected to the input end of the first NOT gate U5, the output end of the first NOT gate U5 is connected to the gate of the MOS tube Mc3, the source of the MOS tube Mc3 is connected to the first charging power supply i chg1 One end of the first charging power supply is connected i chg1 The other end of the MOS tube Mc3 is connected to the vddh end, the drain of the MOS tube Mc3 is connected to the source of the dummy tube Mc3d, the source and drain of the dummy tube Mc3d are connected, the drain of the dummy tube Mc3d is connected to the drain of the dummy tube Mc4d, the drain and source of the dummy tube Mc4d are connected, the source of the dummy tube Mc4d is connected to the drain of the MOS tube Mc4, and the source of the MOS tube Mc4 is connected to one end of the first discharge current source. i dischg1 The other end of the third AND gate U3 is connected to the gate of the dummy tube Mc3d, the output end of the fourth AND gate U4 is connected to the gate of the MOS tube Mc4, the output end of the first NOT gate U5 is connected to the gate of the MOS tube Mc3, the output end of the second NOT gate U6 is connected to the gate of the dummy tube Mc4d, and the first calibration capacitor C cal1 The two ends of the reset tube M4d are respectively connected to the source and drain of the reset tube M4d. The gate of the reset tube M4d is used to receive the capacitor reset signal enb. The source of the reset tube M4d receives the reference voltage V cm , the drain of reset tube M4d outputs the calibration voltage V cal To the two-stage dynamic comparator module.

[0045] Specifically, Figure 2 shown (calibration switch omitted). Figure 2 Where en_cal is the calibration module enable signal. When it is high, the calibration enable becomes effective. en_cmp is the dynamic comparator enable signal. When it is high, the dynamic comparator enable becomes effective. enb is the capacitor reset signal. The value of the capacitor reset signal enb is the negation of the dynamic comparator enable signal en_cmp, which is used to control the second calibration capacitor C cal2 Charge reset, that is, when the enable signal en_cmp of the dynamic comparator is low, the capacitor reset signal enb is high, resetting the second calibration capacitor C cal2 .

[0046] The improved offset calibration module based on charge pump includes two parts: offset calibration circuit and dummy charge pump. When entering the calibration phase, in order not to affect the calibration and comparison functions, the calibration input pair of tubes M2c to M5c of the two-stage dynamic comparator module should be connected to an appropriate reference voltage V cm , while in the traditional solution based on charge pump offset calibration, an additional first calibration capacitor Ccal1 The offset calibration circuit proposed in the present invention introduces a bootstrap pre-charging method for the lower board, that is, the first calibration capacitor C cal1 and the second calibration capacitor C cal2 The lower board is connected to the reference voltage V cm , the upper board is connected to the calibration input to the gate of the tube to ensure the power-on process, the calibration voltage V cal and calibration reference voltage V cm_cal Follow the reference voltage V cm Establish, thus eliminating the need for pre-charging circuit design.

[0047] During the calibration phase, when the calibration module enable signal en_cal and the dynamic comparator enable signal en_cmp are both high, the capacitor reset tube M3d is turned on, the capacitor reset tube M4d is turned off, and the comparator input is switched to the reference voltage V cm Due to the influence of offset, the comparator outputs a positive signal V op_cmp and negative signal V on_cmp Generate high and low level comparison results and control the charging current source through feedback mechanism i chg and discharge power supply i dischg For the first calibration capacitor C cal1 When the comparator output flips, it indicates that the offset voltage has been calibrated to an acceptable range. The introduction of dummy tubes Mc3d and Mc4d can reduce the voltage on the first calibration capacitor C when Mc3 and Mc4 are turned off. cal1 Channel injection effect and clock feedthrough influence.

[0048] Among them, the clock feedthrough effect specifically refers to: for a capacitor charging circuit, when the transmission tube is turned off, part of the charge in the channel will flow into the capacitor, causing the voltage on the capacitor to change, which is the charge injection effect; when the gate terminal voltage of the transmission tube is switched quickly, it will be coupled to the capacitor through the gate-source capacitance of the transmission tube, causing the voltage on the capacitor to change, which is the clock feedthrough effect.

[0049] On the other hand, after the calibration is completed, the calibration module enable signal en_cal and the dynamic comparator enable signal en_cmp are both low, and the first calibration capacitor C cal1 and the second calibration capacitor C cal2 There is no charge and discharge path, but due to the existence of leakage current, there is an unbalanced weak charge and discharge current in the two calibration capacitors, which will affect the offset voltage in the subsequent comparison stage, especially under various process corners with high temperature, the leakage is more serious. In order to further improve the calibration accuracy and stability, this embodiment introduces a dummy charge pump, such as Figure 2As shown in the offset calibration circuit section, after the calibration is completed, the calibration module enable signal en_cal and the dynamic comparator enable signal en_cmp are both low, then the reset tube M3d is turned off, ensuring that the first calibration capacitor C cal1 The upper plate and the second calibration capacitor C cal2 The upper plate is also in a floating state. The size of the MOS tube and the current source in the dummy charge pump are consistent with those in the offset calibration module. Through the reasonable symmetrical layout matching of the layout, it is ensured that in the same chip, the first calibration capacitor C cal1 and the second calibration capacitor C cal2 have the same leakage current, so the calibration voltage V cal and calibration reference voltage V cm_cal The leakage characteristics are consistent, thus maintaining the calibrated offset voltage stored in the calibration capacitor and improving the stability of the calibration.

[0050] In one embodiment, if Figure 3 As shown, the calibration switch includes: four transmission gates and a first NOT gate.

[0051] The input end of the first NOT gate receives the calibration module enable signal en_cal, and the output end of the first NOT gate is connected to the forward enable end of the first transmission gate TG1, the reverse enable end of the second transmission gate TG2, the forward enable end of the third transmission gate TG3 and the reverse enable end of the fourth transmission gate TG4; the reverse enable end of the first transmission gate TG1, the forward enable end of the second transmission gate TG2, the reverse enable end of the third transmission gate TG3 and the forward enable end of the fourth transmission gate TG4 receive the calibration module enable signal en_cal.

[0052] The input terminal of the first transmission gate TG1 is used to receive the positive input signal V ip The output end of the first transmission gate TG1 is connected to the output end of the second transmission gate TG2, and the connection point outputs the inp signal to the two-stage dynamic comparator module; the input ends of the second transmission gate TG2 and the fourth transmission gate TG4 receive the reference voltage V cm The input of the third transmission gate TG3 is used to receive the negative input signal V in The output end of the third transmission gate TG3 is connected to the output end of the fourth transmission gate TG4, and the connection point outputs the inn signal to the two-stage dynamic comparator module.

[0053] Specifically, the calibration switch is as follows Figure 3 During the calibration phase, the calibration module enable signal en_cal is high and the reference voltage V cm, through the second transmission gate TG2 and the fourth transmission gate TG4, the input terminals inp and inn of the two-stage dynamic comparator module are connected respectively, and the first transmission gate TG1 and the third transmission gate TG3 are disconnected. In the normal comparison stage, the calibration module enable signal en_cal is the input signal V ip and V in The first transmission gate TG1 and the third transmission gate TG3 are connected to the input terminals inp and inn of the two-stage dynamic comparator module, and the second transmission gate TG2 and the fourth transmission gate TG4 are disconnected.

[0054] In one embodiment, if Figure 4 As shown, the two-stage dynamic comparator module includes: a kick-back noise elimination circuit, a pseudo-differential pre-amplification stage, and an output amplifier stage.

[0055] The kick-back noise elimination circuit is used to eliminate the kick-back noise of the pseudo-differential pre-amplification stage.

[0056] The pseudo differential pre-amplifier stage is used to perform a differential amplification on the signal selected by the calibration switch and output the first positive signal V dp and the first negative signal V dn , and is also used to compensate for input offset voltage by introducing an unbalanced transconductance current.

[0057] The output amplifier stage is used to adopt the first positive signal V dp and the first negative signal V dn Direct drive, perform secondary amplification on the comparison result of the pseudo differential pre-amplifier output, and output a negative signal V on and the positive signal V op To the latch buffer stage module.

[0058] In one embodiment, if Figure 4 As shown, the kickback noise elimination circuit includes: MOS transistor M1n, MOS transistor M6n, MOS transistor M2n, MOS transistor M3n, MOS transistor M4n and MOS transistor M5n; wherein MOS transistor M1n, MOS transistor M2n and MOS transistor M3n are P-type MOS transistors, and MOS transistor M4n, MOS transistor M5n and MOS transistor M6n are N-type MOS transistors.

[0059] The drain of the MOS transistor M2n is connected to the drain of the MOS transistor M4n, the source of the MOS transistor M2n is connected to the drain of the MOS transistor M1n, the source of the MOS transistor M1n is connected to the vddh terminal, the gate of the MOS transistor M1n is used to receive the opposite phase driving clock clk, the source of the MOS transistor M4n is connected to the drain of the MOS transistor M6n, the source of the MOS transistor M6n is grounded, the gates of the MOS transistors M1n and M6n are both used to receive the opposite phase driving clock clk, the source of the MOS transistor M3n is connected to the source of the MOS transistor M2n, the source of the MOS transistor M4n is connected to the source of the MOS transistor M5n, the gates of the MOS transistors M2n and M4n are connected to the positive input terminal of the pseudo differential pre-amplifier stage, and the gates of the MOS transistors M3n and M5n are connected to the negative input terminal of the pseudo differential pre-amplifier stage.

[0060] In one embodiment, if Figure 4 As shown, the pseudo differential pre-amplification stage includes: MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M2c, MOS tube M3c, MOS tube M4c, MOS tube M5c, The source of the MOS transistor M1 is connected to the Vddh terminal, the gate of the MOS transistor M1 receives the first clock signal clka, and the sources of the MOS transistors M2c, M2, M3 and M3c are all connected to the drain of the MOS transistor M1.

[0061] The gate of MOS tube M2c receives the calibration reference voltage V cm_cal , the gate of MOS tube M2c is connected to the gate of MOS tube M4c, the drain of MOS tube M2c is connected to the drain of MOS tube M4c, the source of MOS tube M4c is connected to the source of MOS tube M4, the drain of MOS tube M2 is connected to the drain of MOS tube M4, the gate of MOS tube M2 is connected to the gate of MOS tube M4, the gate of MOS tube M4 is connected to the positive output end of the kick-back noise elimination circuit, the source of MOS tube M4 is connected to the drain of MOS tube M6, the source of MOS tube M6 is connected to the source of MOS tube M7, the source of MOS tube M7 is grounded, the gate of MOS tube M6 is connected to the gate of MOS tube M7, the gate of MOS tube M6 receives the first clock signal clka, the drain of MOS tube M2c is connected to the negative input end V of the output amplifier stage dn connect.

[0062] The drain of MOS tube M3 is connected to the drain of MOS tube M5, the gate of MOS tube M3 is connected to the gate of MOS tube M5, the source of MOS tube M5 is connected to the drain of MOS tube M7; the drain of MOS tube M3c is connected to the drain of MOS tube M5c, the gate of MOS tube M3c is connected to the gate of MOS tube M5c, and the gate of MOS tube M3c receives the calibration voltage V cal The source of MOS tube M5c is connected to the source of MOS tube M5; the drain of MOS tube M5 is connected to the negative output terminal of the kickback noise elimination circuit; the drain of MOS tube M3c is connected to the negative input terminal V dp connect.

[0063] In one embodiment, if Figure 4 As shown, the first clock signal clka is obtained by processing the clock signal clk and the enable signal en_cmp of the dynamic comparator through an AND gate and then through an inverter.

[0064] In one embodiment, if Figure 4 As shown, the output amplifier stage includes: MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16 and MOS tube M17.

[0065] The gate of MOS tube 10 receives the negative output signal V of the pseudo differential pre-amplifier stage. dn The gate of MOS tube 10 and the gate of MOS tube 14 are connected to the gate of MOS tube M8, the source of MOS tube M10 is connected to the vddh terminal, the drain of MOS tube M10 is connected to the source of MOS tube M12 and the drain of MOS tube M8, the source of MOS tube M8 is connected to the source of MOS tube M9, and the source of MOS tube M8 is grounded; the source of MOS tube M14 and the source of MOS tube M16 are both connected to the vddh terminal, the drain of MOS tube M16 is connected to the drain of MOS tube M12, the gate of MOS tube M16 is connected to the gate of MOS tube M12, the drain of MOS tube M14 is connected to the drain of MOS tube M16 and the gate of MOS tube M17, and the drain of MOS tube M14 outputs a positive signal V op To the latch buffer stage module.

[0066] The source of the MOS tube M17 and the source of the MOS tube M15 are both connected to the vddh terminal, the gate of the MOS tube M17 is connected to the gate of the MOS tube M13, the drain of the MOS tube M17 is connected to the drain of the MOS tube M13, the source of the MOS tube M13 is connected to the drain of the MOS tube M9, the drain of the MOS tube M9 is connected to the drain of the MOS tube M11, the source of the MOS tube M11 is connected to the vddh terminal, and the gates of the MOS tube M15, the MOS tube M11 and the MOS tube M9 are all connected to the positive output signal V of the pseudo differential pre-amplifier stage. dp .

[0067] The gate of the MOS tube M16 is connected to the drain of the MOS tube M17 and the drain of the MOS tube M15 , and the drain of the MOS tube M15 outputs a negative signal Von to the latch buffer stage module.

[0068] Specifically, compared with the traditional pre-amplifier stage, the pre-amplifier stage structure adds a layer of nmos tubes M4 and M5, thereby improving the pre-amplifier stage input transconductance, which can effectively reduce input noise and isolate part of the kickback noise from the clock; usually in order to obtain lower input noise and input offset, the size of the pre-amplifier stage input MOS tube is set larger, so the kickback on the comparator input is particularly serious. The kickback noise is essentially the parasitic capacitance (C) of the output MOS tube pair (M2 to M5) during the switching of the clock clka. GS and C GD Specifically, when clka switches from "1" to "0", the source and drain of the input tube are quickly pulled up to the power supply voltage. This voltage drop is caused by the parasitic capacitance C GD , C GS Coupled to the input of the comparator and interferes with inp and inn. And due to the parasitic capacitance C GD , C GS The value of varies with the amplitude of the input signal (i.e., at higher input voltages generally result in larger parasitic capacitances), and the interference on INP and INN is unbalanced (i.e., the kick-back noise contains both common-mode and differential components).

[0069] In order to further reduce the impact of kickback noise, a kickback noise elimination circuit is designed, such as Figure 4 As shown. The kickback noise is eliminated by introducing MOS tubes (M1n and M6n) and input pairs (M2n to M5n) with opposite phase driving clock clk. When the source and drain voltages of the input tube pair (M2 to M5) rise, the clock clk generates an opposite voltage drop at the source and drain of the MOS tubes M2n to M5n, that is, its potential decreases accordingly, and passes through the parasitic capacitance C of the input MOS tubes M2n~M5n. GD , C GSCoupled to the pre-amplifier input, thereby canceling the kickback noise generated by the pre-amplifier itself. At the same time, the pre-amplifier adds a pair of calibration input tubes M2c to M5c to introduce unbalanced transconductance current to compensate for the input offset voltage.

[0070] The second stage of the two-stage dynamic comparator module is the output latch amplification stage. Compared with the traditional Strong ARM comparator, this structure omits the clock drive of the output latch stage, and directly uses the output V of the first stage pre-amplification stage. dp and V dn Direct drive reduces the clock drive requirements. The small deviation caused by the instantaneous amplification of the first-stage comparison can be quickly identified and amplified by the second-stage output latch, effectively improving the comparison speed.

[0071] In one embodiment, if Figure 5 As shown, the latch buffer stage module includes two buffers and a NAND gate latch structure.

[0072] The NAND gate latch structure includes two NAND gates and two NOT gates; the output end of the first NAND gate U7 is connected to an input end of the second NAND gate U8, the output end of the second NAND gate U8 is connected to an input end of the first NAND gate U7, the second input end of the first NAND gate U7 and the second input end of the second NAND gate U8 both receive an enable signal en_cmp of the dynamic comparator; the output end of the first NAND gate U7 is connected to the input end of the first NOT gate U9, and the output end of the second NAND gate U8 is connected to the input end of the second NOT gate U10.

[0073] The input terminal of the first buffer Buffer1 is used to receive the negative signal V on The output of the first buffer Buffer1 is connected to the third input of the first NAND gate U7, and the first NAND gate U9 outputs the negative signal V of the comparison result. on_cmp .

[0074] The input end of the second buffer Buffer2 is used to receive the positive signal V op The output of the second buffer Buffer2 is connected to the third input of the second NAND gate U8, and the second NAND gate U10 outputs the positive signal V of the comparison result. op_cmp .

[0075] Specifically, due to the regeneration process of the output lock storage amplifier, the output of the comparator has metastable state and burrs at the moment of comparison. Figure 5 The buffers Buffer1 and Buffer2 can filter out this part of the burrs, and the NAND gate latch structure can extract the effective comparison result.

[0076] Compared with the traditional dynamic comparator, the advantage of the present application is that it introduces an improved offset self-calibration technology, which greatly reduces the input offset voltage of the dynamic comparator. The input offset voltage Monte Carlo simulation is as follows: Figure 6 (uncalibrated) and Figure 7 As shown in (Calibration), the input offset voltage after calibration is greatly reduced. At the same time, the present invention optimizes the pre-charging scheme of the calibration capacitor and eliminates the pre-charging circuit. By introducing a dummy charge pump, the gate leakage characteristics of the calibration input are guaranteed to be consistent with the tube, thereby improving the stability of the calibration. The designed kickback noise elimination circuit can reduce the kickback effect on the comparator input. Finally, the input transconductance of the pre-amplifier stage is optimized to effectively reduce the input noise.

[0077] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0078] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A low-noise dynamic comparator based on offset self-calibration, characterized in that: The low-noise dynamic comparator comprises: an improved offset calibration module based on a charge pump, a calibration switch, a two-stage dynamic comparator module and a latch buffer stage module; The improved offset calibration module based on the charge pump is used to ensure the power-on process of the calibration capacitor by introducing the bootstrap pre-charging mode of the lower board when entering the calibration phase, and establish the calibration voltage and the calibration reference voltage according to the reference voltage; in the offset calibration phase, the signal output by the latch buffer stage module is used to control the current source through the feedback mechanism to charge or discharge the calibration capacitor; and after the calibration is completed, a dummy charge pump is used to maintain the calibrated offset voltage stored in the calibration capacitor; The calibration switch is used to transmit the reference voltage information to the two input terminals of the two-stage dynamic comparator module when the calibration module enable signal en_cal is valid; and transmit the input signal to the two input terminals of the two-stage dynamic comparator module when the calibration module enable signal en_cal is invalid; The two-stage dynamic comparator module is used to receive the input signal in the comparison stage, eliminate the kickback noise, process it through the first stage pre-amplifier stage, use the output positive and negative signals of the first stage pre-amplifier stage to directly drive the second stage output lock storage amplification stage, and output the negative signal V on and the positive signal V op To the latch buffer stage module, The latch buffer module is used to store the negative signal V on and the positive signal V op Perform latch buffering, filter out signal glitches, and output comparison results.

2. The low noise dynamic comparator based on offset self-calibration according to claim 1, characterized in that: The improved offset calibration module based on the charge pump comprises: a Dummy charge pump and an offset calibration circuit; The dummy charge pump includes a charging current source, a discharging current source, MOS tubes Mc1 and Mc2, dummy tubes Mc1d and Mc1d, a reset tube M3d, a second calibration capacitor and an OR gate; the gate of the MOS tube Mc1 is connected to the vddh terminal, the source of the MOS tube Mc1 is connected to one end of the charging current source, the drain of the MOS tube Mc1 is connected to the source of the dummy tube Mc1d, the other end of the charging current source is connected to the vddh terminal, the gate of the dummy tube Mc1d is grounded, the drain of the dummy tube Mc1d is connected to the drain of the dummy tube Mc2d, the gate of the dummy tube Mc2d is connected to the vddh terminal, the source of the dummy tube Mc2d is connected to one end of the discharging current source, and the other end of the discharging current source is grounded; the two ends of the second correction capacitor are respectively connected to the drain and source of the reset tube M3d, the drain of the reset tube M3d is connected to the drain of the dummy tube Mc1d, and the source of the reset tube M3d receives the reference voltage V cm The gate of the reset tube M3d is connected to the output end of the OR gate, and the input end of the OR gate is used to receive the calibration module enable signal en_cal and the capacitor reset signal enb; the drain of the reset tube M3d outputs the calibration reference voltage V cm_cal to the two-stage dynamic comparator module; The offset calibration circuit includes: a first charging current source, a first discharging current source, MOS tubes Mc3 and Mc4, dummy tubes Mc3d and Mc4d, a reset tube M4d, a first calibration capacitor, two NOT gates and four AND gates; The two input ends of the first AND gate are used to receive the calibration module enable signal en_cal and the dynamic comparator enable signal en_cmp, and its output end is connected to the first input end of the second AND gate. The second input end of the second AND gate is used to receive the clock clk signal. The output end of the second AND gate is connected to one input end of the third and fourth AND gates, and the other input end of the third AND gate is used to receive the signal V op_cmp , the other input of the fourth AND gate is used to receive the signal V on_cmp The output end of the third AND gate is connected to the input end of the first NOT gate, the output end of the first NOT gate is connected to the gate of the MOS tube Mc3, the source of the MOS tube Mc3 is connected to one end of the first charging power supply, the other end of the first charging power supply is connected to the vddh end, the drain of the MOS tube Mc3 is connected to the source of the dummy tube Mc3d, the source and drain of the dummy tube Mc3d are connected, the drain of the dummy tube Mc3d is connected to the drain of the dummy tube Mc4d, the drain and source of the dummy tube Mc4d are connected, the source of the dummy tube Mc4d is connected to the drain of the MOS tube Mc4 The source of the MOS tube Mc4 is connected to one end of the first discharge current source, the other end of the first discharge current source is grounded, the output end of the third AND gate is connected to the gate of the dummy tube Mc3d, the output end of the fourth AND gate is connected to the gate of the MOS tube Mc4, the output end of the first NOT gate is connected to the gate of the MOS tube Mc3, the output end of the second NOT gate is connected to the gate of the dummy tube Mc4d, the two ends of the first calibration capacitor are respectively connected to the source and drain of the reset tube M4d, the gate of the reset tube M4d is used to receive the capacitor reset signal enb, and the source of the reset tube M4d receives the reference voltage V cm , the drain of reset tube M4d outputs the calibration voltage V cal To the two-stage dynamic comparator module.

3. The low noise dynamic comparator based on offset self-calibration according to claim 1, characterized in that: The calibration switch comprises: four transmission gates and a first NOT gate; The input end of the first NOT gate receives the calibration module enable signal en_cal, and the output end of the first NOT gate is connected to the forward enable end of the first transmission gate, the reverse enable end of the second transmission gate, the forward enable end of the third transmission gate, and the reverse enable end of the fourth transmission gate; the reverse enable end of the first transmission gate, the forward enable end of the second transmission gate, the reverse enable end of the third transmission gate, and the forward enable end of the fourth transmission gate receive the calibration module enable signal en_cal; The first transmission gate input is used to receive the positive input signal V ip The output of the first transmission gate is connected to the output of the second transmission gate, and the connection point outputs the inp signal to the two-stage dynamic comparator module; the input of the second transmission gate and the fourth transmission gate receives the reference voltage V cm ; The input of the third transmission gate is used to receive the negative input signal V in ; The output end of the third transmission gate is connected to the output end of the fourth transmission gate, and the connection point outputs the inn signal to the two-stage dynamic comparator module.

4. The low noise dynamic comparator based on offset self-calibration according to claim 1, characterized in that: The two-stage dynamic comparator module includes: a kickback noise elimination circuit, a pseudo-differential pre-amplification stage, and an output amplifier stage; The kickback noise elimination circuit is used to eliminate the kickback noise of the pseudo differential pre-amplification stage; The pseudo differential pre-amplifier stage is used to perform a first-order differential amplification on the signal selected by the calibration switch, and output a first positive signal V dp and the first negative signal V dn , is also used to compensate for input offset voltage by introducing unbalanced transconductance current; The output amplifier stage is used to adopt the first positive signal V dp and the first negative signal V dn Direct drive, perform secondary amplification on the comparison result of the pseudo differential pre-amplifier output, and output a negative signal V on and the positive signal V op To the latch buffer stage module.

5. The low noise dynamic comparator based on offset self-calibration according to claim 4, characterized in that: The kickback noise elimination circuit comprises: a MOS tube M1n, a MOS tube M6n, a MOS tube M2n, a MOS tube M3n, a MOS tube M4n and a MOS tube M5n; wherein the MOS tube M1n, the MOS tube M2n and the MOS tube M3n are P-type MOS tubes, and the MOS tube M4n, the MOS tube M5n and the MOS tube M6n are N-type MOS tubes; The drain of the MOS transistor M2n is connected to the drain of the MOS transistor M4n, the source of the MOS transistor M2n is connected to the drain of the MOS transistor M1n, the source of the MOS transistor M1n is connected to the vddh terminal, the gate of the MOS transistor M1n is used to receive the opposite phase driving clock clk, the source of the MOS transistor M4n is connected to the drain of the MOS transistor M6n, the source of the MOS transistor M6n is grounded, the gates of the MOS transistors M1n and M6n are both used to receive the opposite phase driving clock clk, the source of the MOS transistor M3n is connected to the source of the MOS transistor M2n, the source of the MOS transistor M4n is connected to the source of the MOS transistor M5n, the gates of the MOS transistors M2n and M4n are connected to the positive input terminal of the pseudo differential pre-amplifier stage, and the gates of the MOS transistors M3n and M5n are connected to the negative input terminal of the pseudo differential pre-amplifier stage.

6. The low noise dynamic comparator based on offset self-calibration according to claim 4, characterized in that: The pseudo differential pre-amplification stage includes: MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M2c, MOS tube M3c, MOS tube M4c, MOS tube M5c, The source of the MOS transistor M1 is connected to the vddh terminal, the gate of the MOS transistor M1 receives the first clock signal clka, and the sources of the MOS transistors M2c, M2, M3 and M3c are all connected to the drain of the MOS transistor M1; The gate of MOS tube M2c receives the calibration reference voltage V cm_cal , the gate of MOS tube M2c is connected to the gate of MOS tube M4c, the drain of MOS tube M2c is connected to the drain of MOS tube M4c, the source of MOS tube M4c is connected to the source of MOS tube M4, the drain of MOS tube M2 is connected to the drain of MOS tube M4, the gate of MOS tube M2 is connected to the gate of MOS tube M4, the gate of MOS tube M4 is connected to the positive output end of the kick-back noise elimination circuit, the source of MOS tube M4 is connected to the drain of MOS tube M6, the source of MOS tube M6 is connected to the source of MOS tube M7, the source of MOS tube M7 is grounded, the gate of MOS tube M6 is connected to the gate of MOS tube M7, the gate of MOS tube M6 receives the first clock signal clka, the drain of MOS tube M2c is connected to the negative input end V of the output amplifier stage dn connect; The drain of MOS tube M3 is connected to the drain of MOS tube M5, the gate of MOS tube M3 is connected to the gate of MOS tube M5, the source of MOS tube M5 is connected to the drain of MOS tube M7; the drain of MOS tube M3c is connected to the drain of MOS tube M5c, the gate of MOS tube M3c is connected to the gate of MOS tube M5c, and the gate of MOS tube M3c receives the calibration voltage V cal The source of the MOS tube M5c is connected to the source of the MOS tube M5; the drain of the MOS tube M5 is connected to the negative output end of the kickback noise elimination circuit; the drain of the MOS tube M3c is connected to the negative input end V dp connect.

7. The low noise dynamic comparator based on offset self-calibration according to claim 6, characterized in that: The first clock signal clka is obtained by processing the clock signal clk and the enable signal en_cmp of the dynamic comparator through an AND gate and then through an inverter.

8. The low noise dynamic comparator based on offset self-calibration according to claim 4, characterized in that: The output amplifier stage includes: MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16 and MOS tube M17; The gate of MOS tube 10 receives the negative output signal V of the pseudo differential pre-amplifier stage. dn The gate of MOS tube 10 and the gate of MOS tube 14 are connected to the gate of MOS tube M8, the source of MOS tube M10 is connected to the vddh terminal, the drain of MOS tube M10 is connected to the source of MOS tube M12 and the drain of MOS tube M8, the source of MOS tube M8 is connected to the source of MOS tube M9, and the source of MOS tube M8 is grounded; the source of MOS tube M14 and the source of MOS tube M16 are both connected to the vddh terminal, the drain of MOS tube M16 is connected to the drain of MOS tube M12, the gate of MOS tube M16 is connected to the gate of MOS tube M12, the drain of MOS tube M14 is connected to the drain of MOS tube M16 and the gate of MOS tube M17, and the drain of MOS tube M14 outputs a positive signal V op To the latch buffer level module; The source of the MOS tube M17 and the source of the MOS tube M15 are both connected to the vddh terminal, the gate of the MOS tube M17 is connected to the gate of the MOS tube M13, the drain of the MOS tube M17 is connected to the drain of the MOS tube M13, the source of the MOS tube M13 is connected to the drain of the MOS tube M9, the drain of the MOS tube M9 is connected to the drain of the MOS tube M11, the source of the MOS tube M11 is connected to the vddh terminal, and the gates of the MOS tube M15, the MOS tube M11 and the MOS tube M9 are all connected to the positive output signal V of the pseudo differential pre-amplifier stage. dp , The gate of MOS tube M16 is connected to the drain of MOS tube M17 and the drain of MOS tube M15. The drain of MOS tube M15 outputs a negative signal V on To the latch buffer stage module.

9. The low noise dynamic comparator based on offset self-calibration according to claim 1, characterized in that: The latch buffer stage module includes two buffers and a NAND gate latch structure; The NAND gate latch structure includes two NAND gates and two NOT gates; the output end of the first NAND gate is connected to an input end of the second NAND gate, the output end of the second NAND gate is connected to an input end of the first NAND gate, the second input end of the first NAND gate and the second input end of the second NAND gate both receive an enable signal en_cmp of the dynamic comparator; the output end of the first NAND gate is connected to the input end of the first NOT gate, and the output end of the second NAND gate is connected to the input end of the second NOT gate; The input terminal of the first buffer is used to receive the negative signal V on The output of the first buffer is connected to the third input of the first NAND gate, and the first NAND gate outputs the negative signal V of the comparison result. on_cmp ; The input of the second buffer is used to receive the positive signal V op The output of the second buffer is connected to the third input of the second NAND gate, and the second NAND gate outputs the positive signal V of the comparison result. op_cmp .

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