An AVX data vector segmentation optimization method based on data access semantic analysis

Abstract

The present invention discloses an AVX data vector segmentation optimization method based on data access semantic analysis. In the dynamic instruction conversion process of executable files, the instruction function and the precision and number of bits of data vectors are clarified according to the semantic analysis of AVX instructions, and the Neon instructions corresponding to the computing AVX instructions are dynamically determined; the instruction function, the precision and number of bits of data vectors and the data segmentation strategy are clarified according to the semantic analysis of AVX instructions and related AVX instructions, and the instruction-level data segmentation strategy optimization is realized, and the Neon instructions corresponding to the data loading AVX instructions and the mapping relationship between AVX registers and Neon registers are dynamically determined. On this basis, the execution of Neon instructions simulating AVX instructions is realized, and the execution performance of AVX instructions when simulating execution on an ARM platform is effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer software development, and in particular relates to an AVX data vector segmentation optimization method based on data access semantic analysis. Background Art

[0002] AVX (Advanced Vector Extensions) is a SIMD (Single Instruction Multiple Data) instruction set introduced by Intel in its processors, which aims to improve the performance of floating-point operations and integer operations. The AVX instruction set allows the processor to process more data at a time, thereby improving the parallelism and throughput of the processing process. The key features of the AVX instruction set include: the use of larger registers, AVX can use 256-bit or even 512-bit wide YMM registers, which can process more data at a time than the 128-bit wide XMM registers used by the SSE instruction set; operand fusion, AVX instructions can operate on two 128-bit operands at the same time and store the results in a 256-bit register, effectively reducing the number of instructions required and potential delays; mixed precision, AVX supports mixed precision operations, that is, it allows single-precision (32-bit) and double-precision (64-bit) floating-point numbers to be processed in the same instruction.

[0003] The SIMD instruction set of the ARM64 architecture, commonly known as Neon, also known as Advanced SIMD, is an instruction set extension introduced in the ARMv7 architecture and later versions. It is used to accelerate applications such as multimedia and signal processing that require large amounts of data processing, and provides support for high-performance computing. In practice, when industrial computing software of the x86 architecture is efficiently executed on the ARM64 platform, it is necessary to use the ARM64 SIMD instructions to efficiently simulate the execution of AVX instructions. However, since AVX instructions support 256-bit or 512-bit data vectors and Neon instructions mainly support 128-bit data vectors, when using Neon instructions to simulate the execution of AVX instructions to process AVX data vectors, they need to be split and reorganized before processing.

[0004] The existing strategies for data segmentation using Neon instructions to process AVX data vectors mainly include bit width adjustment segmentation strategy and element matching segmentation strategy. Among them, the bit width adjustment segmentation strategy refers to segmenting the AVX data vector into 128-bit units to adapt it to the bit width processed by the Neon instruction. The advantage of this strategy is that the segmentation method is simple, direct and easy to implement, which can give full play to the parallel computing ability of the Neon instruction and improve the data processing efficiency. The disadvantage is that it may destroy the integrity of the data; the element matching segmentation strategy refers to dividing the elements in the AVX data vector according to the number of data elements that the Neon data vector can process based on the size and type of the data elements themselves. The advantage is that it can ensure the integrity of the data. The disadvantage is that when the number of data elements does not match the capacity of the Neon data vector, it may cause space waste, increase code complexity, and reduce data processing efficiency.

[0005] In summary, when using Neon instructions to simulate the execution of AVX instructions to process AVX data vectors, how to dynamically determine the data segmentation strategy of AVX data vectors is a key issue that needs to be solved. Summary of the invention

[0006] In view of this, the present invention provides an AVX data vector segmentation optimization method based on data access semantic analysis, which optimizes the data segmentation strategy at the instruction level and realizes the efficient simulation execution of AVX instructions on the ARM platform.

[0007] The present invention provides an AVX data vector segmentation optimization method based on data access semantic analysis, which specifically includes the following steps:

[0008] Step 1, calculate the hash value of the executable file to be executed, load and execute the executable file through dynamic instruction conversion, and search the segmentation strategy mapping list for a file mapping relationship corresponding to the executable file according to the hash value. If so, obtain the file mapping relationship and execute step 6. Otherwise, create a file mapping relationship identified by the hash value for the executable file and execute step 2.

[0009] Step 2: record the current instruction to be converted as the first AVX instruction, record the address of the first AVX instruction as the first AVX instruction address, and obtain the precision and number of bits of the data vector of the first AVX instruction; if the type of the first AVX instruction is a data load instruction, execute step 3; otherwise, if it is a calculation instruction, execute step 4;

[0010] Step 3: According to the semantic analysis of the first AVX instruction and related AVX instructions, determine the data segmentation strategy of the first AVX instruction and the mapping relationship between the AVX register and the Neon register, add the first AVX instruction address, the type of the corresponding first AVX instruction, the precision and number of bits of the data vector, the data segmentation strategy and the mapping relationship between the AVX register and the Neon register to the file mapping relationship; the Neon instruction converted from the first AVX instruction completes the operation on the Neon register, and executes step 5;

[0011] Step 4: Determine the Neon instruction corresponding to the first AVX instruction according to the semantics of the first AVX instruction and the precision and number of bits of its data vector; add the first AVX instruction address, the type of the corresponding first AVX instruction, the precision and number of bits of the data vector, and the Neon instruction to the file mapping relationship; the Neon instruction converted from the first AVX instruction completes the operation on the Neon register, and executes step 5;

[0012] Step 5: If the executable file has not been executed completely, execute step 2; otherwise, add the hash value and file mapping relationship of the executable file to the segmentation strategy mapping list, and end this process;

[0013] Step 6: According to the file mapping relationship corresponding to the executable file, complete the conversion of AVX instructions to Neon instructions, complete the execution of the executable file, and end this process.

[0014] Furthermore, in step 3, according to the semantic analysis of the first AVX instruction and related AVX instructions, the method of determining the data segmentation strategy of the first AVX instruction is:

[0015] Step 2.1, record the register corresponding to the source operand of the first AVX instruction as the first source register, and record the register corresponding to the destination operand as the first destination register; obtain all AVX instructions and their operation codes, instruction suffixes and operands from the instruction-related data to form a related AVX instruction set;

[0016] Step 2.2, select an AVX instruction in the relevant AVX instruction set as the second AVX instruction, record the register corresponding to the source operand of the second AVX instruction as the second source register, and record the register corresponding to the destination operand as the second target register; if the second AVX instruction is a bitwise operation instruction and the second source register is the first target register, set the data splitting strategy of the first AVX instruction to the bitwise splitting strategy; otherwise, execute step 2.3;

[0017] Step 2.3, if the first target register has been modified by the second AVX instruction, set the data segmentation strategy of the first AVX instruction to the data element segmentation strategy; otherwise, execute step 2.4;

[0018] Step 2.4: If the data in the second source register contains a control mask and the second source register is the first target register, the data splitting strategy of the first AVX instruction is set to a bitwise splitting strategy; otherwise, the data splitting strategy of the first AVX instruction is set to a data element splitting strategy.

[0019] Furthermore, in step 3, according to the semantic analysis of the first AVX instruction and related AVX instructions, the mapping relationship between the AVX register and the Neon register of the first AVX instruction is determined as follows:

[0020] Step 3.1, record the data vector of the first AVX instruction as the first data vector, record the precision of the data vector of the first AVX instruction as the first precision, and record the number of bits of the data vector of the first AVX instruction as the first digit; if the data segmentation strategy of the first AVX instruction is a bit-by-bit segmentation strategy, execute step 3.2; if it is a data element segmentation strategy, execute step 3.3;

[0021] Step 3.2, taking the quotient of the first bit of the first data vector and the bit number of the Neon register as the number of data segments N, dividing the first data vector into N data segments, using the data loading instruction in the Neon instruction set to perform N data loading operations from the low bit to the high bit of the first data vector to complete the loading of the first data vector into the Neon register; recording the mapping relationship between the AVX register of the first AVX instruction and the Neon register;

[0022] Step 3.3: According to the first precision of the first data vector, use the data element load instruction in the Neon instruction set to load the first data vector into the Neon register, and record the mapping relationship between the AVX register of the first AVX instruction and the Neon register.

[0023] Furthermore, the instruction-related data in step 2.1 is obtained by reversely analyzing from the first AVX instruction address to the first non-AVX instruction, and using the data from the first AVX instruction to the first non-AVX instruction as instruction-related data.

[0024] Furthermore, the first AVX instruction address is an offset address.

[0025] Furthermore, the precision is single precision or double precision.

[0026] Furthermore, the number of bits is 128 bits, 256 bits or 512 bits. Beneficial Effects

[0027] In the dynamic instruction conversion process of executable files, the present invention clarifies the instruction function and the precision and number of bits of data vectors according to the semantic analysis of AVX instructions, and dynamically determines the Neon instructions corresponding to the computing AVX instructions; clarifies the instruction function, the precision and number of bits of data vectors and the data segmentation strategy according to the semantic analysis of AVX instructions and related AVX instructions, realizes the instruction-level data segmentation strategy optimization, dynamically determines the Neon instructions corresponding to the data loading AVX instructions and the mapping relationship between AVX registers and Neon registers, and on this basis realizes the execution of Neon instructions simulating AVX instructions, effectively improving the execution performance of AVX instructions when simulating execution on the ARM platform. DETAILED DESCRIPTION

[0028] The present invention is described in detail with reference to the following embodiments.

[0029] Among the existing data segmentation strategies, the bit width adjustment segmentation strategy is a bit-by-bit segmentation strategy, which essentially processes the data vector as a bit stream, while the element matching segmentation strategy is a data element-by-data segmentation strategy, which processes the data vector as a number of floating-point numbers.

[0030] Specifically, the use scenario of the bitwise splitting strategy is when the data being processed has low precision requirements and needs to maximize the parallel processing capabilities of the Neon instruction. For example, in some image or audio processing algorithms, the original data may be stored in a high-precision format (such as high-precision floating-point numbers processed by AVX instructions), but lower precision can be used in the intermediate calculation process. For example, suppose that the AVX instruction processes a 256-bit data vector of 32-bit floating-point numbers, that is, it contains 8 32-bit floating-point numbers, and the data vector of the Neon instruction is 128 bits, that is, it contains 4 32-bit floating-point numbers. If the algorithm only needs the lower few bits of the integer part, such as only caring about the lower 4 bits of the color value for fast pixel filtering, each 32-bit floating-point number in the AVX instruction data vector can be bitwise split, the required bits can be extracted, and then combined into a 128-bit data vector suitable for Neon instruction processing.

[0031] The use scenario of the data element splitting strategy is when it is necessary to maintain the integrity of the data elements for processing. This situation is more common when processing structured data such as arrays or matrices, where each data element has its own independent semantics and purpose. For example, taking matrix operations as an example, AVX instructions may process larger matrix data vectors, where each element is a complete numerical value, such as a double-precision floating point number. If the Neon instruction is used to process the matrix, it is necessary to split it by data elements, extract the double-precision floating point numbers in the longer data vector processed by the AVX instruction one by one, and combine them into 128-bit data vectors suitable for Neon instruction processing, to ensure that the operation of each data element during the Neon instruction processing is semantically correct, so that subsequent matrix operations, such as addition, multiplication, etc., can be performed correctly at the matrix element level.

[0032] The present invention provides an AVX data vector segmentation optimization method based on data access semantic analysis, and its core idea is: in the dynamic instruction conversion process of executable files, the instruction function and the precision and bit number of the data vector are clarified according to the semantic analysis of the AVX instruction, and the Neon instruction corresponding to the computing AVX instruction is dynamically determined; the instruction function, the precision and bit number of the data vector and the data segmentation strategy are clarified according to the semantic analysis of the AVX instruction and related AVX instructions, the instruction-level data segmentation strategy is optimized, the Neon instruction corresponding to the data loading AVX instruction and the mapping relationship between the AVX register and the Neon register are dynamically determined, and on this basis, the execution of the Neon instruction simulating the AVX instruction is realized.

[0033] The present invention provides an AVX data vector segmentation optimization method based on data access semantic analysis, which specifically includes the following steps:

[0034] Step 1, calculate the hash value of the executable file to be executed, load and execute the executable file through dynamic instruction conversion, and search the segmentation strategy mapping list according to the hash value to see whether there is a file mapping relationship corresponding to the executable file. If so, obtain the file mapping relationship and execute step 13, otherwise create a file mapping relationship identified by the hash value for the executable file and execute step 2. Among them, the segmentation strategy mapping list is used to save the file mapping relationship of the executable file, and the file mapping relationship saves the AVX instruction type of the AVX instruction in the executable file, the precision and number of bits of the data vector related to the AVX instruction, the mapping relationship from the AVX instruction name to the Neon instruction name, the mapping relationship from the AVX instruction related register of the type of data loading instruction to the Neon instruction related register, and the data segmentation strategy adopted. The AVX instructions in the file mapping relationship are all represented by AVX instruction addresses, and the optimal AVX instruction address is the offset address. AVX instruction types include data loading class and calculation class.

[0035] Step 2: record the current instruction to be converted as the first AVX instruction, record the address of the first AVX instruction as the first AVX instruction address, and obtain the precision and number of bits of the data vector of the first AVX instruction; if the type of the first AVX instruction is a data load instruction, execute step 3; otherwise, if the type of the first AVX instruction is a calculation instruction, execute step 11.

[0036] Step 3. Record the register corresponding to the source operand of the first AVX instruction as the first source register, and record the register corresponding to the destination operand as the first target register; reversely analyze from the first AVX instruction address to the first non-AVX instruction, and use the data from the first AVX instruction to the first non-AVX instruction as instruction-related data, and obtain all AVX instructions and their opcodes, instruction suffixes and operands from the instruction-related data to form a related AVX instruction set.

[0037] Step 4. Select an AVX instruction from the relevant AVX instruction set as the second AVX instruction, record the register corresponding to the source operand of the second AVX instruction as the second source register, and record the register corresponding to its destination operand as the second target register; if the second AVX instruction is a bitwise operation instruction and the second source register is the first target register, set the data splitting strategy of the first AVX instruction to the bitwise splitting strategy and then execute step 7; otherwise, execute step 5.

[0038] Step 5: If the first target register has been modified by the second AVX instruction, set the data segmentation strategy of the first AVX instruction to the data element segmentation strategy and then execute step 7; otherwise, execute step 6.

[0039] Step 6: If the data in the second source register contains a control mask and the second source register is the first target register, set the data segmentation strategy of the first AVX instruction to a bitwise segmentation strategy and then execute step 7; otherwise, set the data segmentation strategy of the first AVX instruction to a data element segmentation strategy and then execute step 7.

[0040] Different instruction set architectures (such as x86, ARM, etc.) have their own specific instruction formats. Generally speaking, a machine instruction consists of two parts: an opcode and an operand. The opcode is used to specify the specific type of operation to be performed, such as addition, subtraction, data loading, storage, etc.; the operand is used to indicate the source or destination of the data involved in the operation, which may be a register, memory address, etc. The first thing to do in instruction decoding is to identify the opcode and operand parts of the instruction according to the format specified by the instruction set.

[0041] Step 7. Record the data vector of the first AVX instruction as the first data vector, record the precision of the data vector of the first AVX instruction as the first precision, and record the number of bits of the data vector of the first AVX instruction as the first digit; obtain the data segmentation strategy of the first AVX instruction in the file mapping relationship, if the data segmentation strategy is a bit-by-bit segmentation strategy, execute step 8, if the data segmentation strategy is a data element segmentation strategy, execute step 9.

[0042] Step 8. Use the quotient of the first bit of the first data vector and the number of bits of the Neon register as the number of data segments N, divide the first data vector into N data segments, use the data loading instruction in the Neon instruction set to perform N data loading operations from the low bit to the high bit of the first data vector to complete the loading of the first data vector into the Neon register; record the correspondence between the AVX register of the first AVX instruction and the Neon register, and execute step 10.

[0043] Step 9: According to the first precision of the first data vector, use the data element load instruction in the Neon instruction set to load the first data vector into the Neon register, record the correspondence between the AVX register of the first AVX instruction and the Neon register, and execute step 10.

[0044] Step 10: Add the first AVX instruction address, the type of the first AVX instruction corresponding to it, the precision and number of bits of the data vector, the data segmentation strategy, and the mapping relationship between the AVX register and the Neon register to the file mapping relationship; the Neon instruction converted from the first AVX instruction completes the operation on the Neon register, and executes step 12.

[0045] Step 11, reverse the first AVX instruction, determine the name of the Neon instruction corresponding to the first AVX instruction according to the semantics of the first AVX instruction and the precision and number of bits of its data vector; add the first AVX instruction address, the type of the first AVX instruction corresponding to it, the precision and number of bits of the data vector, and the name of the Neon instruction to the file mapping relationship; the Neon instruction converted from the first AVX instruction completes the operation on the Neon register, and executes step 12.

[0046] Step 12: If the executable file has not been executed completely, execute step 2; otherwise, add the hash value and file mapping relationship of the executable file to the segmentation strategy mapping list, and end this process.

[0047] Step 13: According to the file mapping relationship corresponding to the executable file, the conversion from AVX instructions to Neon instructions is completed, the execution of the executable file is completed, and this process ends. Example

[0048] In this embodiment, an AVX data vector segmentation optimization method based on data access semantic analysis provided by the present invention is used to implement the simulation execution of AVX instructions on the ARM platform, which specifically includes the following steps:

[0049] S1. Get the hash value of the executable file currently preparing to perform dynamic instruction conversion. If there is a file mapping relationship for the executable file, load this file mapping relationship and record it as mapInstrAddressToDataSplitStrategy, where each element is a two-tuple<instrAddress,dataSplitStrategy> , instrAddress is the offset address of the AVX instruction, dataSplitStrategy is the data splitting strategy, dataSplitStrategy value 0 indicates bit-wise splitting strategy, and value 1 indicates data element-wise splitting strategy.

[0050] S2. Modify the AVX instruction conversion module of the dynamic instruction conversion engine of the ARM platform to analyze the instruction context and dynamically determine the data segmentation strategy. The specific steps are as follows:

[0051] In this embodiment, when mapInstrAddressToDataSplitStrategy is empty, that is, when the executable file is executed for the first time through dynamic instruction conversion, the data split determination strategy processing process established by the present invention will be executed, and the execution speed will be slow. However, starting from the second time, it can be executed according to the file mapping relationship, and the execution speed will be faster.

[0052] S2.1. The AVX instruction currently to be dynamically converted is recorded as avxInstr, and the corresponding instruction address is avxInstrAddress.

[0053] S2.2. Check in mapInstrAddressToDataSplitStrategy whether the data splitting strategy of the AVX instruction avxInstr at this address has been determined according to avxInstrAddress. If not found, execute S2.3; otherwise, execute S2.4.

[0054] S2.3. Determine through instruction decoding whether the operand of avxInstr is a 256-bit data vector or a 512-bit data vector. If the register of the instruction operand is ymmN, N is an integer, then the operand is a 256-bit data vector; if the register of the instruction operand is zmmN, then the operand is a 256-bit data vector.

[0055] In the AVX instruction set, the YMM register is used to process 256-bit data vectors. For example, the instruction `vaddps ymm0,ymm1, ymm2`, where ymm0, ymm1, and ymm2 are YMM registers, indicates that the instruction performs a single-precision floating-point addition operation on a 256-bit data vector.

[0056] For example, the instruction `vmulpd zmm3, zmm4, zmm5`, where zmm3, zmm4, and zmm5 are ZMM registers, indicates that the instruction performs a double-precision floating-point multiplication operation on a 512-bit data vector.

[0057] S2.4. By decoding the opcode part of avxInstr, determine whether the data vector of the avxInstr instruction contains single precision or double precision, including:

[0058] In the AVX instruction set, instructions ending with ps are used to process single-precision floating-point numbers. For example, the multiplication instruction vmulps is used to multiply multiple single-precision floating-point numbers, and the instruction vmovaps is used to load and store aligned single-precision floating-point AVX data vectors. The partial byte sequence of the instruction vmulps in the machine code is similar to `C4 41 F0 4C 24xx`, where `C4` is the AVX instruction prefix, `F0` is the opcode part of the instruction vmulps. The relevant bytes are used to specify the multiplication operation and single-precision floating-point numbers, and `4C 24 xx` is used to specify the addressing information of the memory operand, where xx represents other possible bytes, depending on the specific memory address, etc.

[0059] In addition, instructions ending with pd are used to process double-precision floating-point numbers. For example, the instruction vmulpd is used to multiply multiple double-precision floating-point numbers, and the instruction vmovapd is used to load double-precision data from memory to AVX registers. For example, a partial byte sequence in the machine code of the instruction vmulpd is similar to `C4 41 F2 4C 24 xx`, where C4 is the AVX instruction prefix, 41 is related to the register operand, F2 is the opcode of the instruction vmulpd, and the relevant bytes are used to specify the multiplication operation and double-precision floating-point numbers, and 4C 24 xx is used to specify the addressing information of the memory operand.

[0060] S2.5. Let the target AVX register in avxInstr be targetRegister, and reversely analyze maxInstrCount entries from avxInstrAddress. If maxInstrCount is equal to 100, it is AVX instruction. If the following two rules are found in the reverse process: one is that targetRegister participates in the bitwise operation, and the other is that targetRegister participates in the mask operation, then mark the segmentation strategy of avxInstr as the bitwise segmentation strategy.

[0061] Generally speaking, in the source code, AVX instructions are distributed continuously in the form of embedded assembly.

[0062] Specifically, reverse from avxInstrAddress to (avxInstrAddress+maxInstrAddress*maximum length of AVX instruction) or the first non-AVX instruction, determine whether the current instruction is a bitwise operation instruction of AVX instruction, such as vpand, vpandn, vpor, vxor, etc., and the source register is targetRegister. If so, mark the splitting strategy of avxInstr as bitwise splitting strategy and end the loop, where maxInstrAddress is the address corresponding to the maxInstrCount instruction;

[0063] Otherwise, determine whether the current instruction modifies the targetRegister. If not, determine whether the current instruction is an instruction with a control mask as a parameter, such as _mm256_shuffle_epi8, _mm256_shuffle_epi16, _mm256_shuffle_epi32, etc., and the source register is targetRegister. If so, mark the splitting strategy of avxInstr as a bitwise splitting strategy and end the loop. Otherwise, end the loop. If modified, end the loop.

[0064] If the data splitting strategy of avxInstr has not been set, mark the splitting strategy of avxInstr as splitting strategy by data element.

[0065] S2.6. Record avxInstrAddress and the data splitting strategy of the current instruction to mapInstrAddressToDataSplitStrategy.

[0066] S3. Perform data segmentation according to the data segmentation strategy of avxInstrAddress, that is, use Neon instructions to process the segmented AVX data vectors. The specific steps are as follows:

[0067] If the bit-wise splitting strategy is used, the AVX data vector in avxInstr is avxData, and the data vector of the generated Neon instruction is neonData. Assuming that avxData is a 256-bit data vector, the vldmia instruction is used to load avxData twice.

[0068] The first time, the first 128 bits are loaded into the Neon registers d0 - d3. The registers starting with d are used to represent the Neon registers related to 32-bit data elements, and a group of d0 - d3 is 128 bits. The second time, the last 128 bits are loaded into the d4 -d7 registers to complete the bit-wise splitting operation and place the 256-bit data into different Neon register groups.

[0069] Assuming the AVX instruction is a 256-bit data vector, the sample code is as follows:

[0070] / / Load 256 data vector (avxData) from memory into register

[0071] vldmia avxData, {d0 - d3} / / Load the first 128 bits into Neon registers d0 - d3 (double word registers, each double word is 32 bits)

[0072] vldmia avxData, {d4 - d7} / / Load the last 128 bits into Neon registers d4 - d7

[0073] If the data element splitting strategy is adopted, the single or double-precision floating-point numbers in the AVX data vector need to be extracted one by one according to the data elements, and combined into a 128-bit data vector suitable for Neon processing, to ensure the integrity of each double-precision floating-point element, so as to perform matrix multiplication correctly later. The specific steps are as follows:

[0074] The AVX data vector in avxInstr is avxData, and the data vector of the generated Neon instruction is NeonData. The instruction vld1 is used to load several single-precision or double-precision floating-point numbers from the simulated AVX data memory area avxData into the Neon register to ensure the integrity of each single-precision or double-precision floating-point number. The number of single-precision data loaded is 4, and the number of double-precision data loaded is 2.

[0075] For example, a 256-length AVX data vector consisting of four double-precision floating points is loaded into Neon registers as shown in the following sample code:

[0076] Sample code 1:

[0077] vld1.64 {d0 - d1}, [%[avxData]]

[0078] vld1.64 {d2 - d3}, [%[avxData +8]]

[0079] vld1.64 {d4 - d5}, [%[avxData +16]]

[0080] vld1.64 {d6 - d7}, [%[avxData +24]]

[0081] Load the AVX data vector of length 256 containing 8 single-precision floating points into Neon registers as shown in the following sample code:

[0082] Sample code 2:

[0083] vld1.32 {d0}, [%[avxData]]

[0084] vld1.32 {d1}, [%[avxData + 4]]

[0085] vld1.32 {d2}, [%[avxData + 8]]

[0086] vld1.32 {d3}, [%[avxData + 12]]

[0087] vld1.32 {d4}, [%[avxData + 16]]

[0088] vld1.32 {d5}, [%[avxData + 20]]

[0089] vld1.32 {d6}, [%[avxData + 24]]

[0090] vld1.32 {d7}, [%[avxData + 28]]

[0091] S4. Record mapInstrAddressToDataSplitStrategy to a file for later use.

[0092] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An AVX data vector segmentation optimization method based on data access semantic analysis, characterized in that: The specific steps include: Step 1, calculate the hash value of the executable file to be executed, load and execute the executable file through dynamic instruction conversion, and search the segmentation strategy mapping list for a file mapping relationship corresponding to the executable file according to the hash value. If so, obtain the file mapping relationship and execute step 6. Otherwise, create a file mapping relationship identified by the hash value for the executable file and execute step 2. Step 2: record the current instruction to be converted as the first AVX instruction, record the address of the first AVX instruction as the first AVX instruction address, and obtain the precision and number of bits of the data vector of the first AVX instruction; if the type of the first AVX instruction is a data load instruction, execute step 3; otherwise, if it is a calculation instruction, execute step 4; Step 3: According to the semantic analysis of the first AVX instruction and related AVX instructions, determine the data segmentation strategy of the first AVX instruction and the mapping relationship between the AVX register and the Neon register, and add the first AVX instruction address, the type of the corresponding first AVX instruction, the precision and number of bits of the data vector, the data segmentation strategy and the mapping relationship between the AVX register and the Neon register to the file mapping relationship; The Neon instruction converted from the first AVX instruction completes the operation on the Neon register, and step 5 is executed; Step 4: Determine the Neon instruction corresponding to the first AVX instruction according to the semantics of the first AVX instruction and the precision and number of bits of its data vector; add the first AVX instruction address, the type of the corresponding first AVX instruction, the precision and number of bits of the data vector, and the Neon instruction to the file mapping relationship; The Neon instruction converted from the first AVX instruction completes the operation on the Neon register, and step 5 is executed; Step 5: If the executable file has not been executed completely, execute step 2; otherwise, add the hash value and file mapping relationship of the executable file to the segmentation strategy mapping list, and end this process; Step 6: According to the file mapping relationship corresponding to the executable file, complete the conversion of AVX instructions to Neon instructions, complete the execution of the executable file, and end this process.

2. The AVX data vector segmentation optimization method according to claim 1, characterized in that: In step 3, according to the semantic analysis of the first AVX instruction and related AVX instructions, the method of determining the data segmentation strategy of the first AVX instruction is: Step 2.1, record the register corresponding to the source operand of the first AVX instruction as the first source register, and record the register corresponding to the destination operand as the first destination register; obtain all AVX instructions and their operation codes, instruction suffixes and operands from the instruction-related data to form a related AVX instruction set; Step 2.2, selecting an AVX instruction in the relevant AVX instruction set as the second AVX instruction, recording the register corresponding to the source operand of the second AVX instruction as the second source register, and recording the register corresponding to the destination operand as the second target register; if the second AVX instruction is a bitwise operation instruction and the second source register is the first target register, setting the data splitting strategy of the first AVX instruction to the bitwise splitting strategy; Otherwise, proceed to step 2.3; Step 2.3, if the first target register has been modified by the second AVX instruction, setting the data splitting strategy of the first AVX instruction to a splitting strategy by data element; Otherwise, proceed to step 2.4; Step 2.4: If the data in the second source register contains a control mask and the second source register is the first target register, the data splitting strategy of the first AVX instruction is set to a bitwise splitting strategy; otherwise, the data splitting strategy of the first AVX instruction is set to a data element splitting strategy.

3. The AVX data vector segmentation optimization method according to claim 1, characterized in that: In step 3, according to the semantic analysis of the first AVX instruction and related AVX instructions, the mapping relationship between the AVX register and the Neon register of the first AVX instruction is determined as follows: Step 3.1, record the data vector of the first AVX instruction as the first data vector, record the precision of the data vector of the first AVX instruction as the first precision, and record the number of bits of the data vector of the first AVX instruction as the first digit; if the data segmentation strategy of the first AVX instruction is a bit-by-bit segmentation strategy, execute step 3.2; if it is a data element segmentation strategy, execute step 3.3; Step 3.2, taking the quotient of the first bit of the first data vector and the bit number of the Neon register as the number of data segments N, dividing the first data vector into N data segments, using the data loading instruction in the Neon instruction set to perform N data loading operations from the low bit to the high bit of the first data vector to complete the loading of the first data vector into the Neon register; recording the mapping relationship between the AVX register of the first AVX instruction and the Neon register; Step 3.3: According to the first precision of the first data vector, use the data element load instruction in the Neon instruction set to load the first data vector into the Neon register, and record the mapping relationship between the AVX register of the first AVX instruction and the Neon register.

4. The AVX data vector segmentation optimization method according to claim 2, characterized in that: The method for acquiring the instruction-related data in step 2.1 is: starting from the first AVX instruction address and reversely analyzing backward to the first non-AVX instruction, and using the data from the first AVX instruction to the first non-AVX instruction as the instruction-related data.

5. The AVX data vector segmentation optimization method according to claim 1, characterized in that: The first AVX instruction address is an offset address.

6. The AVX data vector segmentation optimization method according to claim 1, characterized in that: The precision is single precision or double precision.

7. The AVX data vector segmentation optimization method according to claim 1, characterized in that: The number of bits is 128 bits, 256 bits or 512 bits.