Method and system for generating gpu code strategy based on parallelism inference constraint

Abstract

This invention discloses a GPU code policy-driven generation method and system based on parallelism inference constraints. It collects cross-iteration memory access address features of variables using GDB, constructs a spatiotemporal program graph, and applies a spatiotemporal graph convolutional network for modeling. This yields prediction results for loop parallelism types and a five-dimensional optimization policy prediction vector. For serial loops, it directly returns the original C code. For parallelizable loops, the prediction results are converted into natural language parallelism labels and optimization instruction sets, which are then concatenated in a fixed order to construct structured hints. This drives a large language model as a syntax constraint executor to generate target CUDA code. This invention explicitly decouples parallelism inference from code generation, eliminating erroneous parallelization of the large language model and misjudgment of optimization policies, significantly improving the accuracy and execution performance of the generated code. It can be widely applied in the GPU migration of high-performance computing programs and heterogeneous computing fields.

Description

Technical Field

[0001] This invention relates to the fields of high-performance computing (HPC), program analysis and deep learning, specifically to a GPU code strategy-driven generation method and system based on parallelism inference constraints, which can be applied to scenarios such as automatic parallelization of serial programs and automatic generation of GPU code. Background Technology

[0002] With the rapid development of high-performance computing technology, GPUs have become the core hardware platform for accelerating large-scale computing tasks. Migrating existing serial C / C++ programs to GPU parallel architectures requires developers to manually write CUDA code for each parallelizable loop and explicitly specify hardware-related optimization strategies such as memory merging, warp reduction, partitioning, shared memory, and pipelining. This process demands extremely high levels of expertise and has a long development cycle, becoming a major bottleneck in the GPU-based implementation of high-performance computing programs.

[0003] Existing automated CUDA code generation solutions can be mainly divided into three categories: Compiler-based transformation methods, exemplified by polyhedral compilers such as PPCG and Pluto, automatically generate parallel code using affine transformation theory. However, these methods are only applicable to affine loops and cannot handle loops with pointer indirection or irregular memory access. Their code generation coverage is limited, and their optimization strategies are fixed and cannot be adaptively adjusted to the target hardware.

[0004] Neural translation-based methods, such as CodeRosetta and BabelTower, model the C-to-CUDA conversion as a sequence-to-sequence translation task. These methods lack explicit modeling of loop parallelism semantics, resulting in low code accuracy and failing to guarantee that non-parallelizable loops are correctly identified and rejected for parallelization.

[0005] Methods based on large language models directly prompt the LLM to generate CUDA code from serial C code. While these methods leverage the powerful code generation capabilities of LLM, the LLM needs to autonomously infer optimization strategies such as memory merging and warp reduction, which are determined at runtime. Due to the lack of runtime memory access information, the inference results are unreliable, and the performance of the generated code is difficult to guarantee. Existing patent CN202510761772 incorporates a triple verification feedback mechanism with a large language model as the core engine, but the optimization strategy is still inferred by the LLM from the source code text, without introducing external inference constraints. It remains powerless for optimization strategies that require execution-level evidence to determine.

[0006] The common drawback of the above schemes is that they couple parallel inference, optimization strategy selection and code generation into the same step, and fail to decouple inference decisions that depend on runtime information from code generation at the pure syntax level. This causes LLM to undertake semantic inference tasks beyond its capability boundaries, making it difficult to guarantee the correctness and performance of the generated code.

[0007] Therefore, there is an urgent need for a method to decouple parallel type inference from optimization strategy prediction from the code generation process, using external inference results as hard constraints to drive LLM generation, so that LLM can focus on the code implementation at the syntax level, thereby improving both the accuracy and performance of the generated code. Summary of the Invention

[0008] To address the aforementioned technical problems, this invention provides a GPU code strategy-driven generation method and system based on parallelism inference constraints.

[0009] The technical solution adopted by the method of the present invention is: a GPU code strategy-driven generation method based on parallel inference constraints, comprising the following steps: Step 1: Receive the serial C / C++ loop code to be converted, analyze the loop code, and obtain the prediction result of the loop's parallelism type and the prediction vector of the five-dimensional optimization strategy; Step 2: Determine whether the loop can be parallelized based on the parallelism type prediction result; for loops predicted to be serial, return directly to the original C code without parallelization conversion; for loops predicted to be independent parallel or reduced parallel, proceed to the next step. Step 3: Convert the parallelism type prediction results into parallelism labels in natural language form, convert the activated policy dimensions in the five-dimensional optimization policy prediction vector into specific optimization instruction sets, and concatenate them in the order of task description, source C code, parallelism labels, and optimization instruction sets to construct structured hints; Step 4: Input the structured prompts into the large language model, and use the large language model as a syntax constraint executor to generate the target CUDA code.

[0010] Preferably, in step 1, the loop parallelism inference module is invoked to perform static and dynamic joint analysis on the loop code. The loop parallelism inference module first collects the cross-iteration memory access address features of each variable node through GDB dynamic instrumentation, and constructs a spatiotemporal program graph containing spatial and temporal edges. Then, it performs joint modeling through spatiotemporal graph convolution and spatiotemporal attention pooling to obtain a global spatiotemporal representation. Finally, it obtains the loop parallelism type prediction result and the five-dimensional optimization strategy prediction vector. The parallelism type prediction result includes three categories: independent parallelism, reduction parallelism, and serial parallelism. The five-dimensional optimization strategy prediction vector corresponds to five types of GPU optimization strategies: memory merging, warp reduction, block partitioning, shared memory, and pipelined optimization. Each dimension is a binary output indicating whether the strategy is applicable to the current loop.

[0011] Preferably, the method involves collecting cross-iteration memory access address features of each variable node through dynamic instrumentation using GDB to construct a spatiotemporal program graph containing spatial and temporal edges. The specific implementation process is as follows: First, a lightweight parser is used to parse the loop code, generating a static program graph. This static program graph contains four types of nodes: statement nodes, variable nodes, constant nodes, and control nodes, as well as three types of directed edges: syntactic edges, typed data dependency edges, and control flow edges. Control nodes are inserted at loop exit points and branch confluence points. Typed data dependency edges include three types: write-before-read dependency edges, read-before-write dependency edges, and write-before-write dependency edges. Each of these three types of dependency edges uses an independent learnable weight matrix to differentiate the impact of different data dependencies on parallelism assessment. At the same time, the loop code is executed through GDB. Dynamic instrumentation is performed in the next iteration. The preset number of iterations; in the first iteration... In each iteration, the actual memory access address of each variable node within the loop body is recorded sequentially, forming the... The dynamic features of nodes in each iteration form a node feature matrix. ,in The total number of nodes. Let R be the feature dimension and R be the real number field. ; will the first The static graph structure and dynamic node feature matrix of the next iteration Combining, constructing the first The feature-rich program graph corresponding to the next iteration ;in For a set of nodes, Let be a set of spatial edges containing three types of directed edges. A node feature matrix containing dynamic address characteristics; in the spatial edge set Introducing time edge sets based on this Connect adjacent iterations and The corresponding instances of the same variable node enable the loop parallelism inference module to perceive the cross-iteration change pattern of memory access addresses of each variable in the temporal dimension; constructing a complete spatiotemporal program graph: ; in express The set of all node instances in the next iteration It is the union of the spatial and temporal edges. This is the sequence of feature matrices for each iteration node.

[0012] Preferably, the global spatiotemporal representation is obtained by jointly modeling spatiotemporal graph convolution and spatiotemporal attention pooling; the specific implementation process is as follows: First, the spatiotemporal program diagram Spatiotemporal graph convolution operations are applied to propagate node features along both spatial and temporal edges at each layer; this is done for a set of spatial edge types that includes five categories: syntactic edges, RAW edges, WAR edges, WAW edges, and control flow edges. and time edge type Each uses an independent learnable weight matrix To transmit messages, ;node In the The layer update rules are as follows: ; in, For nodes In the Layer embedding representation; For nodes In edge type The set of neighboring nodes; For the iteration to which the corresponding neighbor node belongs, perform spatial edge... Regarding the time edge ; edge type In the The learnable weight matrix of the layer; It is a non-linear activation function; Normalized coefficients; The spatiotemporal embedding of each node is obtained after convolution of the layer spatiotemporal graph. This enables joint modeling of spatial structure dependence and cross-iterational temporal evolution patterns; Subsequently, spatiotemporal attention pooling is performed to embed all nodes of the spatiotemporal graph convolution output. Simultaneously calculate attention weights in both spatial and temporal dimensions:

[0013] in, For learnable attention vectors, For learnable bias scalars, The node embedding dimension is used, and sigmoid() is the activation function. Weighted summation yields the global spatiotemporal representation of the loop: ; in, For the first The global spatiotemporal representation vector of each loop, denominator This is the normalization coefficient.

[0014] Preferably, the acquisition of the parallelism type prediction result of the loop and the five-dimensional optimization strategy prediction vector, and the global spatiotemporal representation are used. The parallelism type prediction result is output after parallelism classification head and softmax activation. : ; in, This is the class head weight matrix. The bias vector is the output dimension 3, corresponding to three categories: independent parallelism, reduced parallelism, and serial parallelism. R is the real number field. Embed dimensions for nodes; Global spacetime representation Gradient isolation operation The policy prediction head and sigmoid activation then output a five-dimensional optimized policy prediction vector. :

[0015] in, For the strategy prediction head weight matrix, It is the bias vector; This indicates a gradient stopping operation, which blocks the interference of the classification task gradient on the policy prediction head, thus achieving decoupled training for the two prediction tasks. The five dimensions correspond to five types of GPU optimization strategies: memory merging, warp reduction, block partitioning, shared memory, and pipelined. Each dimension is a binary output indicating whether the strategy is applicable to the current loop.

[0016] Preferably, in step 3, the parallelism type prediction result is... Parallelism labels converted to natural language form Independent parallelism describes the analysis conclusions of each iteration being executed independently, while reduction parallelism describes the parallelization method of the reduction operation. The parallelism label is generated by a predefined template mapping function. When the parallelism type is independent parallelism, it generates "each iteration of this loop is independent of each other, there is no cross-iteration data dependency, and it can be safely executed in parallel"; when the parallelism type is reduction parallelism, it generates "this loop contains reduction operations, and the results can be merged through a parallel reduction strategy"; the predefined template mapping function is a natural language mapping rule designed specifically for the semantic characteristics of loop parallelism, and the specific rules are as follows: when When operating in independent parallelism (IND), the activation state of the predicted vector is further refined into the following three sub-rules based on the five-dimensional optimization strategy: Sub-rule IND-1 (Memory Merge Mode): When and When generating the statement, "Each iteration of this loop is independent of the others, there is no cross-iteration data dependency, and it can be safely executed in parallel; the thread memory access mode is suitable for memory merging optimization, requiring adjacent threads to access contiguous global memory addresses to fully utilize memory bandwidth"; Sub-rule IND-2 (Shared Memory Cache Mode): When and When generating the statement, "Each iteration of this loop is independent of the others, there is no cross-iteration data dependency, and it can be safely executed in parallel; there are high-frequency repeated memory accesses, so it is required to cache frequently accessed data blocks in shared memory to reduce the number of global memory accesses and improve data reuse efficiency." Sub-rule IND-3 (Basic Independent Parallel Mode): When and At that time, it generates "each iteration of this loop is independent of each other, there is no cross-iteration data dependency, and it can be safely executed in parallel; each iteration can be directly mapped to an independent CUDA thread for parallel execution"; Sub-rule IND-4 (Memory Merging and Shared Memory Joint Optimization Mode): When and At that time, it was generated that "each iteration of the loop is independent of each other, there is no cross-iteration data dependency, and it can be safely executed in parallel; at the same time, there is a need for memory merging and shared memory optimization, requiring adjacent threads to access global memory at consecutive addresses and to cache frequently accessed data blocks in shared memory, thereby improving memory access efficiency through the collaboration of two types of optimization"; when For Reduction Parallelism (RED), the activation states of the predicted vectors are further refined into the following three sub-rules based on the five-dimensional optimization strategy: Sub-rule RED-1 (Warp-level reduction mode): when When generating the statement, "This loop contains a reduction operation, the reduction scale is suitable for Warp-level parallel processing, and it is required to use Warp-level primitives to complete the reduction within the thread bundle, efficiently merge the local results of each thread within the Warp, and avoid the performance overhead of global memory atomic operations." Sub-rule RED-2 (block reduction mode): when and When the loop contains a reduction operation, it can be processed by a block-based parallel reduction strategy. It requires dividing the data into data blocks suitable for GPU caching. Each thread block first completes local reduction, and then the results of each block are merged into the final result. Sub-rule RED-3 (Basic Reduction Pattern): When o_2=0 and o_3=0, generate "This loop contains a reduction operation. Each iteration performs cumulative updates on the shared variables. It is required that each thread completes its local reduction through a thread-private accumulator before merging, so as to avoid direct competition for writing to shared variables by multiple threads".

[0017] Preferably, in step 3, the five-dimensional optimization strategy prediction vector is traversed. For each dimension, corresponding optimization instructions are generated for the policy dimension with an activation value of 1, forming an optimization instruction set. ;in, The five dimensions correspond to memory merging, Warp reduction, chunking, shared memory, and pipeline strategies, respectively; according to task description Source C code Parallelism label Optimize instruction set By sequentially piecing together the information, a complete structured hint can be constructed:

[0018] in This indicates a sequential concatenation operation.

[0019] As a preferred approach, the correspondence between the five-dimensional optimization strategy vector and the optimization instructions is as follows: when The system generates a memory merge instruction, requiring threads to access global memory at consecutive addresses. when Warp reduction instructions are generated at that time, requiring the use of warp-level primitives to complete the reduction operation; when The system generates block instructions that require the computation task to be broken down into data blocks suitable for GPU caching. when The system generates shared memory instructions that require frequently accessed data to be cached in shared memory. when The pipeline instructions are generated in real time, requiring overlapping data transmission and computation operations.

[0020] Preferably, in step 4, structured prompts are used. Input a large language model and generate the target CUDA code: ; in, This represents the generated CUDA code. This represents the generation function of a large language model.

[0021] The technical solution adopted by the system of this invention is: a GPU code generation system driven by a parallel inference constraint, comprising: One or more processors; A storage device for storing one or more programs, which, when executed by one or more processors, enable the one or more processors to implement the GPU code strategy-driven generation method based on parallelism inference constraints.

[0022] Compared with the prior art, the beneficial effects of the present invention include: (1) This invention constructs a spatiotemporal program graph for the input loop code by calling the loop parallelism inference module and applies a spatiotemporal graph convolutional network for joint modeling. At the same time, it captures the spatial structure dependency and cross-iteration temporal evolution law of the program, obtains the prediction results of parallelism type and optimization strategy, and explicitly decouples parallelism inference from code generation. (2) This invention directly returns the original C code to the serial loop, avoiding erroneous parallelization; (3) This invention configures a large language model as a syntax constraint executor based on structured prompts for parallel loops, uses parallelism labels as semantic boundary constraints and optimized instruction sets as implementation specification constraints, so that the large language model can focus on the code implementation at the syntax level without having to undertake semantic inference tasks, which significantly improves the accuracy and execution performance of the generated code; (4) This invention automatically converts the parallel type prediction results into fine-grained natural language semantic constraints through a predefined template mapping function, which precisely limits the generative semantic space of the large language model and eliminates the problem of ambiguity between multiple feasible implementation schemes of the model; (5) This invention automatically generates corresponding GPU optimization instructions by predicting vectors and policy-instruction conversion rules through five-dimensional optimization strategies, and directly injects the optimization strategies inferred by the neural network into code generation constraints, thus eliminating the problem of misjudgment of optimization strategies caused by the lack of runtime memory access information in existing methods; (6) The present invention adopts a structured prompting mechanism of four-element sequential splicing to ensure that the large language model executes code generation only after receiving complete constraints, thereby avoiding the truncation or ignoring of constraint information; (7) The scope of application of this invention is significantly better than that of compiler methods that only support affine loops. It can handle complex loop patterns such as pointer indirect addressing and irregular memory access, and has stronger versatility and practical value. It can be widely applied to the field of GPU migration of high-performance computing programs, compiler optimization and heterogeneous computing. Attached Figure Description

[0023] The technical solutions of the present invention will be further illustrated below using embodiments and specific implementation methods. In addition, some accompanying drawings are used in the description of the technical solutions. Those skilled in the art can obtain other drawings and the intent of the present invention from these drawings without any creative effort.

[0024] Figure 1 This is a schematic diagram of the method according to an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the working principle of the loop parallelism inference module in an embodiment of the present invention. Detailed Implementation

[0025] To facilitate understanding and implementation of the present invention by those skilled in the art, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0026] Please see Figure 1 This embodiment provides a GPU code strategy-driven generation method based on parallelism inference constraints, which includes the following steps: Step 1: Receive the serial C / C++ loop code to be converted, call the loop parallelism inference module to analyze the loop code, and obtain the prediction result of the loop parallelism type and the prediction vector of the five-dimensional optimization strategy; Please see Figure 2 In one implementation, the loop parallelism inference module first collects the cross-iteration memory access address features of each variable node through GDB dynamic instrumentation, and constructs a spatiotemporal program graph containing spatial and temporal edges; then, it performs joint modeling through spatiotemporal graph convolution and spatiotemporal attention pooling to obtain a global spatiotemporal representation; finally, it obtains the loop parallelism type prediction result and the five-dimensional optimization strategy prediction vector; the parallelism type prediction result includes three categories: independent parallelism, reduction parallelism, and serial parallelism; the five-dimensional optimization strategy prediction vector corresponds to five types of GPU optimization strategies: memory merging, Warp reduction, block partitioning, shared memory, and pipelined optimization, with each dimension being a binary output indicating whether the strategy is applicable to the current loop.

[0027] In one implementation, the method involves dynamically instrumenting GDB to collect the memory access address characteristics of each variable node across iterations, constructing a spatiotemporal program graph containing spatial and temporal edges. Specifically, the process is as follows: First, a lightweight parser is used to parse the loop code, generating a static program graph. This static program graph contains four types of nodes: statement nodes, variable nodes, constant nodes, and control nodes, as well as three types of directed edges: syntactic edges, typed data dependency edges, and control flow edges. Control nodes are inserted at loop exit points and branch confluence points. Typed data dependency edges include three types: read-before-write (RAW) edges, read-before-write (WAR) edges, and write-before-write (WAW) edges. Each type uses an independent learnable weight matrix to differentiate the impact of different data dependencies on parallelism judgment. The static program graph only reflects the syntactic structure of the loop. For loops containing pointer indirect addressing and runtime array index determination, it is impossible to determine whether different iterations access the same memory address solely based on the static structure. Therefore, dynamic execution features are introduced to supplement this.

[0028] At the same time, the loop code is executed through GDB. Dynamic instrumentation is performed in the next iteration. The preset number of iterations; in the first iteration... In each iteration, the actual memory access address of each variable node within the loop body is recorded sequentially, forming the... The dynamic features of nodes in each iteration form a node feature matrix. ,in The total number of nodes. Let R be the feature dimension and R be the real number field. The memory access address directly reflects the read / write behavior of the variable in each iteration and the overlap of addresses across iterations, and is a sufficient source of information for judging data races; the first The static graph structure and dynamic node feature matrix of the next iteration Combining, constructing the first The feature-rich program graph corresponding to the next iteration ;in For a set of nodes, Let be a set of spatial edges containing three types of directed edges. A node feature matrix containing dynamic address characteristics; in the spatial edge set Introducing time edge sets based on this Connect adjacent iterations and The corresponding instances of the same variable node enable the loop parallelism inference module to perceive the cross-iteration change pattern of memory access addresses of each variable in the temporal dimension; constructing a complete spatiotemporal program graph: ; in express The set of all node instances in the next iteration It is the union of the spatial and temporal edges. This is the sequence of feature matrices for each iteration node.

[0029] In one implementation, the global spatiotemporal representation is obtained by joint modeling through spatiotemporal graph convolution and spatiotemporal attention pooling; the specific implementation process is as follows: First, the spatiotemporal program diagram Spatiotemporal graph convolution operations are applied to propagate node features along both spatial and temporal edges at each layer; this is done for a set of spatial edge types that includes five categories: syntactic edges, RAW edges, WAR edges, WAW edges, and control flow edges. and time edge type Each uses an independent learnable weight matrix To transmit messages, ;node In the The layer update rules are as follows: ; in, For nodes In the Layer embedding representation; For nodes In edge type The set of neighboring nodes; For the iteration to which the corresponding neighbor node belongs, perform spatial edge... Regarding the time edge ; edge type In the The learnable weight matrix of the layer; It is a non-linear activation function; Normalized coefficients; The spatiotemporal embedding of each node is obtained after convolution of the layer spatiotemporal graph. This enables joint modeling of spatial structure dependence and cross-iterational temporal evolution patterns; Subsequently, spatiotemporal attention pooling is performed to embed all nodes of the spatiotemporal graph convolution output. Simultaneously calculate attention weights in both spatial and temporal dimensions:

[0030] in, For learnable attention vectors, For learnable bias scalars, The node embedding dimension is used, and sigmoid() is the activation function. Weighted summation yields the global spatiotemporal representation of the loop: ; in, For the first The global spatiotemporal representation vector of each loop, denominator This is the normalization coefficient.

[0031] In one implementation, the acquisition of the parallelism type prediction result of the loop and the five-dimensional optimization strategy prediction vector, global spatiotemporal representation The parallelism type prediction result is output after parallelism classification head and softmax activation. : ; in, This is the class head weight matrix. The bias vector is the output dimension 3, corresponding to three categories: independent parallelism, reduced parallelism, and serial parallelism. R is the real number field. Embed dimensions for nodes; Global spacetime representation Gradient isolation operation The policy prediction head and sigmoid activation then output a five-dimensional optimized policy prediction vector. :

[0032] in, For the strategy prediction head weight matrix, It is the bias vector; This indicates a gradient stopping operation, which blocks the interference of the classification task gradient on the policy prediction head, thus achieving decoupled training for the two prediction tasks. The five dimensions correspond to five types of GPU optimization strategies: memory merging, warp reduction, block partitioning, shared memory, and pipelined. Each dimension is a binary output indicating whether the strategy is applicable to the current loop.

[0033] Step 2: Determine whether the loop can be parallelized based on the parallelism type prediction result; for loops predicted to be serial, return directly to the original C code without parallelization conversion; for loops predicted to be independent parallel or reduced parallel, proceed to the next step. In one implementation, the parallelism type prediction result of the loop is read. ;like If steps 3 and 4 are skipped, the original C code is returned directly as output without any parallelization conversion, thus avoiding data races introduced by incorrectly parallelizing non-parallel loops; if If (independent parallelism or reduction parallelism) occurs, proceed to step 3 to construct structured hints and generate CUDA code; where... Indicates independent parallelism. Indicates reduction parallelism, Indicates serial.

[0034] Step 3: Convert the parallelism type prediction results into parallelism labels in natural language form, convert the activated policy dimensions in the five-dimensional optimization policy prediction vector into specific optimization instruction sets, and concatenate them in the order of task description, source C code, parallelism labels, and optimization instruction sets to construct structured hints; In one implementation, the parallelism type prediction result is... Parallelism labels converted to natural language form Independent parallelism describes the analysis conclusions of each iteration being executed independently, while reduction parallelism describes the parallelization method of the reduction operation. The parallelism label is generated by a predefined template mapping function. When the parallelism type is independent parallelism, it generates "each iteration of this loop is independent of each other, there is no cross-iteration data dependency, and it can be executed in parallel safely"; when the parallelism type is reduction parallelism, it generates "this loop contains reduction operations, and the results can be merged through parallel reduction strategies"; the predefined template mapping function is a natural language mapping rule designed independently for the semantic characteristics of loop parallelism.

[0035] when When operating in independent parallelism (IND), the activation state of the predicted vector is further refined into the following three sub-rules based on the five-dimensional optimization strategy: Sub-rule IND-1 (Memory Merge Mode): When and When generating the statement, "Each iteration of this loop is independent of the others, there is no cross-iteration data dependency, and it can be safely executed in parallel; the thread memory access mode is suitable for memory merging optimization, requiring adjacent threads to access contiguous global memory addresses to fully utilize memory bandwidth"; Sub-rule IND-2 (Shared Memory Cache Mode): When and When generating the statement, "Each iteration of this loop is independent of the others, there is no cross-iteration data dependency, and it can be safely executed in parallel; there are high-frequency repeated memory accesses, so it is required to cache frequently accessed data blocks in shared memory to reduce the number of global memory accesses and improve data reuse efficiency." Sub-rule IND-3 (Basic Independent Parallel Mode): When and At that time, it generates "each iteration of this loop is independent of each other, there is no cross-iteration data dependency, and it can be safely executed in parallel; each iteration can be directly mapped to an independent CUDA thread for parallel execution"; Sub-rule IND-4 (Memory Merging and Shared Memory Joint Optimization Mode): When and At that time, it was generated that "each iteration of the loop is independent of each other, there is no cross-iteration data dependency, and it can be safely executed in parallel; at the same time, there is a need for memory merging and shared memory optimization, requiring adjacent threads to access global memory at consecutive addresses and to cache frequently accessed data blocks in shared memory, thereby improving memory access efficiency through the collaboration of two types of optimization"; when For Reduction Parallelism (RED), the activation states of the predicted vectors are further refined into the following three sub-rules based on the five-dimensional optimization strategy: Sub-rule RED-1 (Warp-level reduction mode): when When generating the statement, "This loop contains a reduction operation, the reduction scale is suitable for Warp-level parallel processing, and it is required to use Warp-level primitives to complete the reduction within the thread bundle, efficiently merge the local results of each thread within the Warp, and avoid the performance overhead of global memory atomic operations." Sub-rule RED-2 (block reduction mode): when and When the loop contains a reduction operation, it can be processed by a block-based parallel reduction strategy. It requires dividing the data into data blocks suitable for GPU caching. Each thread block first completes local reduction, and then the results of each block are merged into the final result. Sub-rule RED-3 (basic reduction mode): When o_2=0 and o_3=0, generate "This loop contains a reduction operation. Each iteration performs cumulative updates on the shared variable. It is required that each thread completes the local reduction through a thread-private accumulator before merging, so as to avoid direct competition for writing to the shared variable by multiple threads". The design of the predefined template mapping function is based on the following: different combinations of parallelism subtypes and optimization strategies correspond to different CUDA implementation constraints. Fine-grained semantic description can precisely limit the generation space of large language models to the corresponding parallelization mode and optimization implementation range, avoiding ambiguity between multiple feasible implementation schemes, thereby improving the relevance and accuracy of the generated code; the mapping rules are linked with the activation state of the five-dimensional optimization strategy prediction vector to ensure that the parallelism label and the optimization instruction set are consistent at the semantic level.

[0036] In one implementation, the five-dimensional optimization strategy prediction vector is traversed. For each dimension, corresponding optimization instructions are generated for the policy dimension with an activation value of 1, forming an optimization instruction set. ;in, The five dimensions correspond to memory merging, Warp reduction, chunking, shared memory, and pipeline strategies, respectively; according to task description Source C code Parallelism label Optimize instruction set By sequentially piecing together the information, a complete structured hint can be constructed:

[0037] in This indicates a sequential concatenation operation.

[0038] The structured prompts constrain the generation space of the large language model within a defined scope of parallel semantics, allowing the large language model to focus on the code implementation at the grammatical level without having to autonomously infer optimization strategies.

[0039] In one implementation, the correspondence between the five-dimensional optimization strategy vector and the optimization instructions is as follows: when The system generates a memory merge instruction, requiring threads to access global memory at consecutive addresses. when Warp reduction instructions are generated at that time, requiring the use of warp-level primitives to complete the reduction operation; when The system generates block instructions that require the computation task to be broken down into data blocks suitable for GPU caching. when The system generates shared memory instructions that require frequently accessed data to be cached in shared memory. when The pipeline instructions are generated in real time, requiring overlapping data transmission and computation operations.

[0040] Step 4: Input the structured prompts into the large language model, and use the large language model as a syntax constraint executor to generate the target CUDA code.

[0041] In one implementation, it is based on structured prompts. The large language model is configured as a syntax constraint executor. This configuration is based on the observation that, without imposing parallelism constraints, the large language model exhibits two typical failure modes in the task of parallelizing loop code: First, forcibly generating CUDA parallel code for non-parallel loops introduces cross-iteration data races, leading to incorrect execution results; second, lacking targeted optimization for CUDA code that can be generated in parallel loops, it only performs mechanical translation at the syntax level without utilizing the characteristics of the GPU architecture, resulting in poor actual acceleration. This invention eliminates the first type of failure by explicitly injecting parallelism inference results into the hint construction, using parallelism labels to eliminate the second type of failure, and optimizing the instruction set. The specific configuration process is as follows: based on the task description... Define the target scenario and output specifications for code generation, using parallelism tags. As a semantic boundary constraint, the parallel semantic scope of the generated code is limited to optimize the instruction set. As a specific implementation requirement for the various GPU optimization strategies specified by the canonical constraints, the above constraints are injected into the generation context of the large language model through the sequential concatenation of four-element structured prompts to generate the target CUDA code: ; in, This represents the generated CUDA code. This represents the large language model generation function after structured suggestion configuration. This indicates a sequential concatenation operation; the large language model, acting as a syntax constraint executor, does not need to independently determine the parallelizability and optimization strategy of the loop, but is only responsible for converting the structured semantic constraints into code implementations that conform to the CUDA syntax specification; the generated CUDA code contains GPU-specific optimization implementations corresponding to the optimization strategy, including thread mapping, memory access optimization, computational partitioning, etc.; for loops predicted to be serial, the original C code has already been returned directly in step 2 and will not proceed to this step.

[0042] The invention will be further verified through experiments in the following sections.

[0043] To verify the effectiveness of the GPU code generation strategy driven by parallelism inference constraints proposed in this invention, experiments were conducted on an end-to-end code generation evaluation dataset containing 79 loop samples. The dataset covers three types of loop code: Polybench benchmark set (30 samples), Rodinia heterogeneous computing benchmark set (19 samples), and non-parallel loop set (30 samples). The evaluation metrics include four items: compile rate (CR), execution rate (ER), accuracy (Co), and speedup (Fast).

[0044] Six methods were selected as baselines for comparison: PPCG (polyhedral compiler), CodeRosetta (neural translation method), BabelTower (neural translation method), LASSI (automatic parallelization tool based on static analysis), Claude direct generation (direct generation of CUDA code from a large language model), and Claude detection-before-generation (generation of CUDA code from a large language model combined with parallel detection). The results of the effectiveness test are shown in Table 1.

[0045] Table 1

[0046] As can be seen from Table 1, this invention achieves optimal results in all four metrics. Compared with existing optimal baseline methods: (1) Compared with Claude's detection-then-generate method, the compilation rate of this invention is improved by 7.6 percentage points (0.899 vs 0.823), the execution rate is improved by 6.3 percentage points (0.886 vs 0.823), the accuracy is improved by 11.4 percentage points (0.861 vs 0.747), and the acceleration rate is improved by 10.1 percentage points (0.810 vs 0.709). The improvement comes from the fact that this invention injects the parallel inference results and the five-dimensional optimization strategy prediction vector into the prompt construction at the same time, rather than just injecting the parallel detection results, so that the large language model generates code under the dual constraints of semantic boundary constraints and implementation specification constraints.

[0047] (2) In terms of non-parallel loop processing, the present invention correctly processes 26 non-parallel loops (out of a total of 30), which is better than the 24 loops generated by Claude after detection and the 18 loops generated by LASSI; the results verify that the design of directly returning the original C code to the serial loop in step 2 of the present invention effectively eliminates the problem of incorrect parallelization.

[0048] (3) On the Rodinia heterogeneous computing benchmark set, the present invention correctly processed 17 samples, which is better than all the comparison methods; the results verify the effectiveness of the five-dimensional optimization strategy prediction vector and optimization instruction set mechanism of the present invention for complex heterogeneous computing scenarios.

[0049] (4) Compared with the PPCG method based on compiler transformation, the present invention processes 25 samples on the Polybench benchmark set (28 for PPCG), but processes 17 samples on the Rodinia set (0 for PPCG); the results show that the coverage of the present invention is significantly better than the compiler method that is only applicable to affine loops.

[0050] (5) Compared with the neural translation methods CodeRosetta and BabelTower, the accuracy of this invention (0.861) is 78.5 percentage points and 82.3 percentage points higher, respectively. The results verify that the design idea of ​​explicitly decoupling parallel inference from code generation and constraining the generation of large language models with neural network inference results has significant advantages over end-to-end neural translation methods.

[0051] In summary, the experimental results fully verify the comprehensive superiority of the proposed method in terms of compilation rate, execution rate, accuracy and speedup, and prove the effectiveness of the parallel inference constraint mechanism in improving the quality of GPU code generation.

[0052] This invention provides a GPU code strategy-driven generation method and system based on parallelism inference constraints. It collects cross-iteration memory access address features of each variable node by calling a loop parallelism inference module and using GDB dynamic instrumentation. A spatiotemporal program graph is constructed from the input loop code, and a spatiotemporal graph convolutional network is applied for joint modeling. Simultaneously, it captures the spatial structure dependency and cross-iteration temporal evolution rules of the program, obtaining the parallelism type prediction result. With the five-dimensional optimization strategy prediction vector This explicitly decouples parallelism inference from code generation; The serial loop directly returns to the original C code, eliminating the first type of failure introduced by data races in existing technologies where large language models forcibly parallelize non-parallel loops; for Parallelizable loops based on structured hints Configure large language models as grammar constraint enforcers, with parallelism labels. As a semantic boundary constraint, to optimize the instruction set As a constraint to implement the specification, it eliminates the second type of failure in existing technologies, which is caused by the lack of runtime memory access information in large language models, leading to misjudgment of optimization strategies. This allows large language models to focus on the code implementation at the syntactic level without having to undertake semantic inference tasks, significantly improving the accuracy and execution performance of generated code. It can be widely applied in the fields of GPU migration of high-performance computing programs, compiler optimization, and heterogeneous computing.

[0053] It should be understood that the embodiments described above are only some, not all, of the embodiments of the present invention. Furthermore, the technical features of the various embodiments or individual embodiments provided by the present invention can be arbitrarily combined to form feasible technical solutions. Such combinations are not constrained by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0054] It should be understood that the above description of the preferred embodiments is quite detailed, but it should not be considered as a limitation on the scope of protection of this invention. Those skilled in the art, under the guidance of this invention, can make substitutions or modifications without departing from the scope of protection of the claims of this invention, and all such substitutions or modifications fall within the scope of protection of this invention. The scope of protection of this invention should be determined by the appended claims.

Claims

1. A GPU code generation method driven by a strategy based on parallel inference constraints, characterized in that, Includes the following steps: Step 1: Receive the serial C / C++ loop code to be converted, analyze the loop code, and obtain the prediction result of the loop's parallelism type and the prediction vector of the five-dimensional optimization strategy; Step 2: Determine whether the loop can be parallelized based on the parallelism type prediction result; for loops predicted to be serial, return directly to the original C code without parallelization conversion; for loops predicted to be independent parallel or reduced parallel, proceed to the next step. Step 3: Convert the parallelism type prediction results into parallelism labels in natural language form, convert the activated policy dimensions in the five-dimensional optimization policy prediction vector into specific optimization instruction sets, and construct structured hints by concatenating them in the order of task description, source C code, parallelism labels, and optimization instruction sets. Step 4: Input the structured prompts into the large language model, and use the large language model as a syntax constraint executor to generate the target CUDA code.

2. The GPU code strategy-driven generation method based on parallelism inference constraints according to claim 1, characterized in that: In step 1, the loop parallelism inference module is invoked to perform static and dynamic joint analysis on the loop code. The loop parallelism inference module first collects the cross-iteration memory access address features of each variable node through GDB dynamic instrumentation, and constructs a spatiotemporal program graph containing spatial and temporal edges. Then, it performs joint modeling through spatiotemporal graph convolution and spatiotemporal attention pooling to obtain a global spatiotemporal representation. Finally, it obtains the loop parallelism type prediction result and the five-dimensional optimization strategy prediction vector. The parallelism type prediction result includes three categories: independent parallelism, reduction parallelism, and serial parallelism. The five-dimensional optimization strategy prediction vector corresponds to five types of GPU optimization strategies: memory merging, warp reduction, block partitioning, shared memory, and pipelined optimization. Each dimension is a binary output indicating whether the strategy is applicable to the current loop.

3. The GPU code strategy-driven generation method based on parallelism inference constraints according to claim 2, characterized in that: The method involves dynamically instrumenting GDB to collect cross-iteration memory access address features of each variable node and constructing a spatiotemporal program graph containing spatial and temporal edges. The specific implementation process is as follows: First, a lightweight parser is used to parse the loop code, generating a static program graph. This static program graph contains four types of nodes: statement nodes, variable nodes, constant nodes, and control nodes, as well as three types of directed edges: syntactic edges, typed data dependency edges, and control flow edges. Control nodes are inserted at loop exit points and branch confluence points. Typed data dependency edges include three types: write-before-read dependency edges, read-before-write dependency edges, and write-before-write dependency edges. Each of these three types of dependency edges uses an independent learnable weight matrix to differentiate the impact of different data dependencies on parallelism assessment. At the same time, the loop code is executed through GDB. Dynamic instrumentation is performed in the next iteration. The preset number of iterations; in the first iteration... In each iteration, the actual memory access address of each variable node within the loop body is recorded sequentially, forming the... The dynamic features of nodes in each iteration form a node feature matrix. ,in The total number of nodes. Let R be the feature dimension and R be the real number field. ; will the first The static graph structure and dynamic node feature matrix of the next iteration Combining, constructing the first The feature-rich program graph corresponding to the next iteration ;in For a set of nodes, Let be a set of spatial edges containing three types of directed edges. A node feature matrix containing dynamic address characteristics; in the spatial edge set Introducing time edge sets based on this Connect adjacent iterations and The corresponding instances of the same variable node enable the loop parallelism inference module to perceive the cross-iteration change pattern of memory access addresses of each variable in the temporal dimension; constructing a complete spatiotemporal program graph: ； in express The set of all node instances in the next iteration It is the union of the spatial edge and the temporal edge. This is the sequence of feature matrices for each iteration node.

4. The GPU code strategy-driven generation method based on parallelism inference constraints according to claim 2, characterized in that: The method involves joint modeling using spatiotemporal graph convolution and spatiotemporal attention pooling to obtain a global spatiotemporal representation; the specific implementation process is as follows: First, the spatiotemporal program diagram Spatiotemporal graph convolution operations are applied to propagate node features along both spatial and temporal edges at each layer; this is done for a set of spatial edge types that includes five categories: syntactic edges, RAW edges, WAR edges, WAW edges, and control flow edges. and time edge type Each uses an independent learnable weight matrix To transmit messages, ;node In the The layer update rules are as follows: ； in, For nodes In the Layer embedding representation; For nodes In edge type The set of neighboring nodes; For the iteration to which the corresponding neighbor node belongs, perform spatial edge... Regarding the time edge ; edge type In the The learnable weight matrix of the layer; It is a non-linear activation function; Normalized coefficients; The spatiotemporal embedding of each node is obtained after convolution of the layer spatiotemporal graph. This enables joint modeling of spatial structure dependence and cross-iterational temporal evolution patterns; Subsequently, spatiotemporal attention pooling is performed to embed all nodes of the spatiotemporal graph convolution output. Simultaneously calculate attention weights in both spatial and temporal dimensions: in, For learnable attention vectors, For learnable bias scalars, The node embedding dimension is used, and sigmoid() is the activation function. Weighted summation yields the global spatiotemporal representation of the loop: ； in, For the first The global spatiotemporal representation vector of each loop, denominator This is the normalization coefficient.

5. The GPU code strategy-driven generation method based on parallelism inference constraints according to claim 2, characterized in that: The prediction results of the parallelism type of the obtained loop and the prediction vector of the five-dimensional optimization strategy are used for global spatiotemporal representation. The parallelism type prediction result is output after parallelism classification head and softmax activation. : ； in, This is the class head weight matrix. The bias vector is the output dimension 3, corresponding to three categories: independent parallelism, reduced parallelism, and serial parallelism. R is the real number field. Embed dimensions for nodes; Global spacetime representation Gradient isolation operation The policy prediction head and sigmoid activation then output a five-dimensional optimized policy prediction vector. : in, For the strategy prediction head weight matrix, It is the bias vector; This indicates a gradient stopping operation, which blocks the interference of the classification task gradient on the policy prediction head, thus achieving decoupled training for the two prediction tasks. The five dimensions correspond to five types of GPU optimization strategies: memory merging, warp reduction, block partitioning, shared memory, and pipelined. Each dimension is a binary output indicating whether the strategy is applicable to the current loop.

6. The GPU code strategy-driven generation method based on parallelism inference constraints according to claim 1, characterized in that: In step 3, the parallelism type prediction results are... Parallelism labels converted to natural language form Independent parallelism describes the analysis conclusions of each iteration being executed independently, while reduction parallelism describes the parallelization method of the reduction operation. The parallelism label is generated by a predefined template mapping function. When the parallelism type is independent parallelism, it generates "each iteration of this loop is independent of each other, there is no cross-iteration data dependency, and it can be executed in parallel safely"; when the parallelism type is reduction parallelism, it generates "this loop contains reduction operations, and the results can be merged through a parallel reduction strategy". The predefined template mapping function is a natural language mapping rule designed independently to address the semantic characteristics of loop parallelism; The natural language mapping rules include: when When operating independently and in parallel, the activation states of the predicted vectors are further refined into the following three sub-rules based on the five-dimensional optimization strategy: Sub-rule IND-1 is the memory merge mode; when and When generating: Each iteration of this loop is independent of the others, there is no cross-iteration data dependency, and it can be safely executed in parallel; the thread memory access mode is suitable for memory merging optimization, requiring adjacent threads to access contiguous global memory addresses to make full use of memory bandwidth; Sub-rule IND-2 is for shared memory caching mode; when and At that time, the loop is generated as follows: each iteration is independent of the others, there is no cross-iteration data dependency, and it can be safely executed in parallel; there are high-frequency repeated memory accesses, so it is required to cache frequently accessed data blocks in shared memory to reduce the number of global memory accesses and improve data reuse efficiency. Sub-rule IND-3 is the basic independent parallel mode; when and At that time, the loop is generated as follows: each iteration is independent of the others, there is no cross-iteration data dependency, and it can be safely executed in parallel; each iteration can be directly mapped to an independent CUDA thread for parallel execution; Sub-rule IND-4 is a joint optimization mode for memory merging and shared memory; when and At that time, the loop is generated as follows: each iteration is independent of the others, there is no cross-iteration data dependency, and it can be safely executed in parallel; at the same time, there is a need for memory merging and shared memory optimization, requiring adjacent threads to access global memory at consecutive addresses, and to cache frequently accessed data blocks in shared memory, thereby improving memory access efficiency through the collaboration of two types of optimizations; when For reduction in parallel processing, the activation states of the predicted vectors are further refined into the following three sub-rules based on the five-dimensional optimization strategy: Sub-rule RED-1 is a Warp-level reduction pattern; when When generating: This loop contains reduction operations, the reduction scale is suitable for Warp-level parallel processing, and Warp-level primitives are required to complete the reduction within the thread bundle, so as to efficiently merge the local results of each thread within the Warp and avoid the performance overhead of global memory atomic operations. Sub-rule RED-2 is the block reduction mode; when and When generating: This loop contains reduction operations, which can be processed by a block-based parallel reduction strategy. It requires dividing the data into data blocks suitable for GPU caching. Each thread block first completes local reduction, and then the results of each block are merged into the final result. Subrule RED-3 is the basic reduction pattern; when o_2=0 and o_3=0, it generates: This loop contains reduction operations, and each iteration performs cumulative updates on the shared variables. It requires that each thread completes its local reduction through a thread-private accumulator before merging, to avoid direct competition for writing to shared variables by multiple threads.

7. The GPU code strategy-driven generation method based on parallelism inference constraints according to claim 1, characterized in that: In step 3, the five-dimensional optimization strategy prediction vector is traversed. For each dimension, corresponding optimization instructions are generated for the policy dimension with an activation value of 1, forming an optimization instruction set. ;in, The five dimensions correspond to memory merging, Warp reduction, chunking, shared memory, and pipeline strategies, respectively; according to task description Source C code Parallelism label Optimize instruction set By sequentially piecing together the information, a complete structured hint can be constructed: in This indicates a sequential concatenation operation.

8. The GPU code policy-driven generation method based on parallelism inference constraints according to claim 7, characterized in that, The correspondence between the five-dimensional optimization strategy vector and the optimization instructions is as follows: when The system generates a memory merge instruction, requiring threads to access global memory at consecutive addresses. when Warp reduction instructions are generated at that time, requiring the use of warp-level primitives to complete the reduction operation; when The system generates block instructions that require the computation task to be broken down into data blocks suitable for GPU caching. when The system generates shared memory instructions that require frequently accessed data to be cached in shared memory. when The pipeline instructions are generated in real time, requiring overlapping data transmission and computation operations.

9. The GPU code strategy-driven generation method based on parallelism inference constraints according to claim 1, characterized in that: In step 4, the structured hints will be... Input a large language model and generate the target CUDA code: ； in, This indicates the generated CUDA code. This represents the generation function of a large language model.

10. A GPU code policy-driven generation system based on parallel inference constraints, characterized in that, include: One or more processors; A storage device for storing one or more programs, which, when executed by one or more processors, cause the one or more processors to implement the GPU code policy-driven generation method based on parallelism inference constraints as described in any one of claims 1 to 9.

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