Programmable CTT structure and threshold voltage rapid stabilization method

Abstract

The invention provides a programmable CTT structure and a threshold voltage rapid stabilization method. The programmable CTT structure comprises a packaging substrate; the drain electrode and the source electrode are arranged at the two ends of the same side of the packaging substrate respectively; the substrate is arranged on one side, far away from the drain electrode, of the packaging substrate; the high-dielectric-constant insulating layer is arranged on one side, far away from the substrate, of the packaging substrate, and the connecting part of the high-dielectric-constant insulating layer and the packaging substrate is located between the drain electrode and the source electrode; and the grid electrode is arranged on one side, far away from the packaging substrate, of the high-dielectric-constant insulating layer. Through the structure and the method, the problem that a threshold voltage stabilization scheme of an existing CTT needs a long time is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a programmable CTT structure and a threshold voltage fast stabilization method. Background Art

[0002] In the field of modern microelectronics, programmable charge transfer transistor (PCTT), as an innovative semiconductor device, is gradually showing its great potential in frontier fields such as dynamic circuit configuration, low-power electronic system design and neuromorphic computing. The core advantage of PCTT lies in its unique charge transfer mechanism, which allows the internal charge distribution to be dynamically adjusted through external programming signals, thereby changing the conductive properties of the device, especially its threshold voltage (Vth), which provides unprecedented possibilities for circuit flexibility and versatility.

[0003] However, a key technical challenge facing PCTT in practical applications is the stability of the threshold voltage. Specifically, when PCTT undergoes the programming process, its threshold voltage will increase significantly. This phenomenon is mainly attributed to the effective injection and capture of charges during the programming process, which changes the potential distribution in the channel region of the device. This change is crucial to achieving specific circuit functions, but it also introduces a complex dynamic process: the threshold voltage is not immediately stable in the initial stage after programming, but will experience a period of decay.

[0004] The reasons for this decay phenomenon are multifaceted and complex, including but not limited to: the trapped charges generated during the programming process are gradually released over time, resulting in redistribution of the potential in the channel region; changes in interface states, that is, the conversion of charge states at the interface between the semiconductor and the insulating layer. The instability of these interface states will also affect the threshold voltage; and the release process of internal stress of the device. Under the combined effect of these factors, the threshold voltage of PCTT takes a relatively long time to gradually stabilize after programming. Summary of the invention

[0005] The present application provides a programmable CTT structure and a threshold voltage fast stabilization method to solve the problem that the threshold voltage stabilization solution of the existing CTT requires a long time.

[0006] In a first aspect, the present application provides a programmable CTT structure, the structure comprising:

[0007] Package substrate;

[0008] A drain electrode and a source electrode, wherein the drain electrode and the source electrode are respectively built at two ends of the same side of the packaging substrate;

[0009] A substrate, the substrate being arranged on a side of the packaging substrate away from the drain;

[0010] A high dielectric constant insulating layer, wherein the high dielectric constant insulating layer is arranged on a side of the packaging substrate away from the substrate, and a portion where the high dielectric constant insulating layer is connected to the packaging substrate is located between the drain and the source;

[0011] A gate is disposed on a side of the high dielectric constant insulating layer away from the packaging substrate.

[0012] Preferably, the high dielectric constant insulating layer comprises:

[0013] A shallow well region, wherein the shallow well region is connected to the packaging substrate;

[0014] A deep well region is arranged on a side of the shallow well region away from the packaging substrate.

[0015] Preferably, the drain is connected to an external power supply.

[0016] In a second aspect, the present application further provides a method for rapid stabilization of threshold voltage based on a programmable CTT structure, the method comprising:

[0017] When CTT is programmed, electrons are captured from the package substrate into a high-dielectric-constant insulating layer;

[0018] When the CTT completes programming, some electrons are attracted from the high dielectric constant insulating layer to the packaging substrate.

[0019] Preferably, the method further comprises:

[0020] When CTT is programmed, electrons are captured from the package substrate into shallow well regions and deep well regions;

[0021] When the CTT completes programming, electrons are attracted from the shallow well region into the packaging substrate.

[0022] Preferably, the method further comprises:

[0023] When CTT is programmed, electrons form an electron flow from the source to the drain, and the electrons in the electron flow are attracted from the package substrate to the shallow well region and the deep well region through the gate;

[0024] When the CTT completes programming, electrons form a reverse electron flow between the high dielectric constant insulating layer and the packaging substrate, and the electrons in the shallow well region are attracted to the packaging substrate by a light erase operation.

[0025] Preferably, when the CTT is programmed, the source and substrate are grounded;

[0026] The drain is connected to an external power supply, and a first positive pulse voltage is applied to the gate; the voltage of the external power supply is 0.9V.

[0027] Preferably, the method further comprises:

[0028] When the CTT completes programming, the source and the gate are grounded;

[0029] The drain is connected to the external power source, and a second forward pulse voltage is applied to the substrate.

[0030] Preferably, the voltage magnitude of the second forward pulse voltage is smaller than the voltage magnitude of the first forward pulse voltage.

[0031] Preferably, the light erase operation includes using the second forward pulse voltage to attract the reverse electron flow at the substrate to attract the electrons in the shallow well region into the packaging substrate.

[0032] As can be seen from the above content, the present application provides a programmable CTT structure and a threshold voltage fast stabilization method, the programmable CTT structure includes a package substrate; a drain and a source, the drain and the source are respectively built-in at the two ends of the same side of the package substrate; a substrate, the substrate is arranged on the side of the package substrate away from the drain; a high dielectric constant insulating layer, the high dielectric constant insulating layer is arranged on the side of the package substrate away from the substrate, and the part where the high dielectric constant insulating layer is connected to the package substrate is located between the drain and the source; the gate, the gate is arranged on the side of the high dielectric constant insulating layer away from the package substrate. The present application solves the problem that the threshold voltage stabilization scheme of the existing CTT takes a long time through the above structure and method. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] Figure 1 A schematic diagram of a programmable CTT structure during programming in this application;

[0035] Figure 2 A schematic diagram of a programmable CTT structure of the present application when programming is completed;

[0036] Figure 3 A schematic diagram of a programmable CTT structure of the present application during conventional threshold voltage stabilization;

[0037] Figure 4A schematic diagram of a programmable CTT structure in this application when performing rapid stabilization of threshold voltage;

[0038] Figure 5 The present invention discloses a flow chart of a method for fast stabilizing a threshold voltage based on a programmable CTT structure. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their ordinary and common meanings.

[0041] The terms "first", "second", "third", etc. in the specification and claims of this application and the above drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise noted. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances.

[0042] Figure 1 This is a schematic diagram of a programmable CTT structure during programming in the present application.

[0043] See also Figure 1 It can be seen that this embodiment provides a programmable CTT structure, which includes:

[0044] The package substrate 100 is specifically an important component of semiconductor packaging technology in this embodiment. It is used to carry the chip and provide functions such as electrical connection, protection, support and heat dissipation. The package substrate 100 is generally a technical branch of PCB printed circuit boards, but has higher precision, density and performance requirements. It can provide electrical connection and physical support between the chip and the PCB motherboard, and is an important component material of the semiconductor package.

[0045] The packaging substrate 100 needs to meet the following conditions:

[0046] Since a programmable CTT may include a large number of programmable elements and complex circuit connections, its packaging substrate 100 needs to have the characteristics of high density and high precision to support a large number of electrical connections and signal transmissions.

[0047] The programmable CTT may generate high heat during operation, so the packaging substrate 100 needs to have good heat dissipation performance to ensure stable operation of the chip and extend its service life.

[0048] The packaging substrate 100 needs to be able to withstand various environmental conditions and stress changes to ensure the reliability and stability of the programmable CTT in various application scenarios.

[0049] The package substrate 100 needs to match the electrical characteristics and physical dimensions of the programmable CTT to ensure that they can be properly connected and work together.

[0050] The structure also includes:

[0051] The drain 200 and the source 300 are respectively built at two ends of the same side of the package substrate 100. Specifically, the source 300 is an electrode that provides carriers (electrons or holes); the drain 200 is an electrode that collects carriers in the transistor. When the transistor is working, the carriers flow from the source 300 to the drain 200 to form a current.

[0052] Among them, in CTT, although its special feature is the charge trapping ability of the gate dielectric, the basic functions of the drain 200 and the source 300 are similar to those in other transistors. When the CTT is used as a switch or amplifier, the source 300 provides carriers and the drain 200 collects carriers to form a current path.

[0053] The structure also includes:

[0054] The substrate 400 is disposed on a side of the packaging substrate 100 away from the drain 200 . Specifically, in this embodiment, the substrate 400 provides stable support for other layers of the transistor to ensure the structural integrity and stability of the entire transistor.

[0055] In the charge trapping transistor, the substrate 400 is one of the channels for charge transfer. When the control gate applies voltage, electrons are injected into the charge trapping layer through the substrate 400. The interface quality between the substrate 400 and the tunneling layer has an important influence on the transfer and capture efficiency of the charge. A high-quality interface can reduce the scattering and leakage of the charge and improve the performance of the transistor.

[0056] For example, taking the SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) type charge trapping transistor as an example, its structure consists of a silicon substrate, a tunneling oxide layer, a silicon nitride trapping layer, a blocking oxide layer and a metal control gate. In this structure, the silicon substrate, as one of the channels for charge transfer, forms a high-quality interface with the tunneling oxide layer, ensuring that the charge can be effectively injected into the silicon nitride trapping layer and captured. At the same time, the doping concentration and thermal stability of the silicon substrate also have an important impact on the performance of the SONOS transistor.

[0057] The structure also includes:

[0058] The high dielectric constant insulating layer 500 is disposed on the side of the package substrate 100 away from the substrate 400, and the portion where the high dielectric constant insulating layer 500 is connected to the package substrate 100 is located between the drain 200 and the source 300. Specifically, in this embodiment, the high dielectric constant insulating layer 500 refers to an insulating material layer with a relatively high dielectric constant value (εr). These materials include hafnium dioxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), and silicate compounds.

[0059] Among them, at the same physical thickness, high dielectric constant materials can provide higher capacitance values, which helps to reduce the size of transistors and improve integration. Since a thicker insulating layer can be used to achieve the same capacitance value, the leakage current of the gate circuit will be significantly reduced, improving the energy efficiency and stability of the device. The high dielectric constant insulating layer 500 helps to solve the technical problems brought by traditional silicon dioxide gate materials, such as unstable threshold voltage (Vt), decreased carrier channel mobility, and reduced device reliability.

[0060] The structure also includes:

[0061] The gate 600 is arranged on a side of the high dielectric constant insulating layer 500 away from the packaging substrate 100. Specifically, in the present embodiment, the gate 600 is an electrode in the transistor. In the present embodiment, the gate 600 is located above the packaging substrate 100 and is isolated from the packaging substrate 100 by an insulating layer (such as silicon dioxide). The main function of the gate 600 is to form an electric field on the surface of the packaging substrate 100 by applying a voltage, thereby controlling the flow of charge carriers (such as electrons and holes) in the packaging substrate 100. In the charge trapping transistor, the gate 600 is also responsible for trapping charges in the high dielectric constant insulating layer 500 to achieve information storage.

[0062] Wherein, the high dielectric constant insulating layer 500 comprises:

[0063] A shallow well region 510, wherein the shallow well region 510 is connected to the packaging substrate 100;

[0064] The deep well region 520 is disposed on a side of the shallow well region 510 away from the packaging substrate 100 .

[0065] Specifically, in this embodiment, the gate 600 is used to capture charges in the shallow well region 510 and the deep well region 520 .

[0066] The drain electrode 200 is connected to an external power source 700 .

[0067] Exemplarily, programmable CTT has the following application scope and advantages:

[0068] The core of programmable CTT lies in its powerful configuration capabilities. Users or developers can easily adjust the layout, size, shape, color and response logic of the touch area through a graphical interface or programming interface (API). This flexibility enables the interface design to closely fit product features and user needs, achieving true personalized customization.

[0069] In order to simplify the development process and improve efficiency, programmable CTT adopts a modular design concept. The system has built-in multiple predefined functional modules, such as sliders, knobs, switches, gesture recognition, etc. These modules can be dragged and dropped onto the interface like building blocks, and their properties and behaviors can be quickly configured. This design approach not only reduces the difficulty of development, but also speeds up the time to market.

[0070] Programmable CTT integrates advanced touch recognition algorithms and can accurately identify user touch operations, including single-point touch, multi-point touch, pressure sensing, and complex gesture recognition. At the same time, the system also provides a variety of feedback mechanisms, such as tactile vibration, sound prompts, and visual animations, to enhance the user's operating experience and immersion.

[0071] To further enhance the user experience, programmable CTT supports automatic adjustment of interface layout and interaction mode according to the current state of the application or changes in the external environment. For example, in night mode, the system automatically reduces the interface brightness and adjusts the color scheme to reduce eye stimulation; when a change in user identity is detected, the interface will also be adjusted accordingly to display personalized content and services.

[0072] Programmable CTT also has powerful remote update and maintenance capabilities. Through cloud services, manufacturers can easily push new interface configurations or function upgrades to users without requiring users to perform any physical operations. This capability not only reduces maintenance costs, but also speeds up product iteration, allowing electronic products to continue to remain competitive.

[0073] Figure 5 The present invention discloses a flow chart of a method for fast stabilizing a threshold voltage based on a programmable CTT structure.

[0074] See also Figure 5 It can be seen that, further, this embodiment also provides a threshold voltage fast stabilization method based on a programmable CTT structure, the method comprising:

[0075] S1, when CTT is programmed, electrons are captured from the packaging substrate into the high dielectric constant insulating layer. Specifically, in this embodiment, when CTT is programmed, electrons need to be captured from the packaging substrate and the captured electrons are transferred to the high dielectric constant insulating layer.

[0076] When the CTT is programmed, electrons form an electron flow between the source and the drain, and the gate attracts the electrons in the electron flow from the package substrate to the shallow well region and the deep well region. Therefore, electrons are attracted in both the shallow well region and the deep well region of the high dielectric constant insulating layer.

[0077] For example, a charge trap transistor (CTT) device is programmed. The specific steps are as follows: a positive pulse voltage (e.g., peak value 2V, frequency 1kHz, duty cycle 50%, duration 800ms) is applied to the gate, the drain is connected to 0.9V, and the source and substrate are grounded. Under this condition, some electrons in the electron flow from the source to the drain will be attracted by the gate and captured in the deep well and shallow well regions in the high dielectric constant insulating layer, thereby increasing the threshold voltage of the CTT device (e.g., 50mV).

[0078] When the CTT is programmed, the various components in the programmable CTT refer to Figure 2 .

[0079] When CTT completes programming, the drain is connected to an external power supply, the substrate, source and gate need to be grounded respectively, and a first positive pulse voltage is applied to the gate; the voltage of the external power supply is 0.9V.

[0080] It should be noted that when CTT completes programming, the charges in the high dielectric constant insulating layer are separated from the insulating layer and return to the channel of the transistor, causing the threshold voltage to decay, such as Figure 2 This process will continue for a long time until the electrons in the high dielectric constant insulating layer no longer leave the insulating layer. At this time, the threshold voltage of the transistor is in a stable state.

[0081] In order to stabilize the threshold voltage when CTT completes programming, conventional technology proposes the following solution. Figure 3 , specifically including:

[0082] The source and the gate are grounded, the drain is still connected to the external power supply, and a positive pulse voltage equal to the first positive pulse voltage is input to the substrate end, thereby erasing the CTT device.

[0083] Exemplarily, by applying a positive pulse voltage (e.g., peak-to-peak 2V, frequency 1kHz, duty cycle 50% square wave, duration 800ms) to the substrate, the drain is connected to VDD, the source and the gate are grounded. Since the potential of the substrate is higher than the potential of the gate, the charges previously trapped in the deep well and shallow well regions in the insulating layer are attracted out, thereby reducing the threshold voltage of the CTT device.

[0084] However, although erasing a CTT device can reduce the threshold voltage of the CTT device, it still takes a long time.

[0085] Figure 4 This is a schematic diagram of a programmable CTT structure in the present application when performing rapid stabilization of threshold voltage.

[0086] See also Figure 4 It can be seen that, further, the method also includes:

[0087] S2, when CTT completes programming, attracting some electrons from the high dielectric constant insulating layer to the packaging substrate. Specifically, in this embodiment, based on Figure 2 As can be seen from the above description of when CTT completes programming, since the decay time of the threshold voltage is relatively long when CTT completes programming, this embodiment provides a method to shorten the decay time of the threshold voltage when CTT completes programming.

[0088] Among them, this embodiment adopts a solution of attracting part of the electrons in the high dielectric constant insulating layer into the packaging substrate to shorten the decay time of the threshold voltage when the CTT completes programming.

[0089] The step S2 can be understood as attracting electrons from the shallow well region into the packaging substrate when the CTT completes programming; specifically, when the CTT completes programming, electrons form a reverse electron flow between the high dielectric constant insulating layer and the packaging substrate, and a light erase operation is used to attract electrons in the shallow well region into the packaging substrate.

[0090] Among them, the light erase operation is to apply a second forward pulse voltage at the substrate, and the voltage of the second forward pulse voltage must be smaller than the voltage of the first forward pulse voltage; wherein, the light erase operation includes using the second forward pulse voltage to attract the reverse electron flow at the substrate, and attracting the electrons in the shallow well area into the packaging substrate; thereby, only the electrons in the shallow well area can be attracted out, and the electrons in the deep well area will not be attracted; since the light erase operation proposed in this embodiment is to attract only the electrons in the shallow well area, this avoids attracting the electrons in the deep well area which is more difficult to attract, thereby allowing the peak voltage of CTT to quickly stabilize.

[0091] For example, in order to accelerate the process of charges in the shallow well region escaping from the insulating layer and returning to the transistor channel, we propose a light erase operation. This operation is similar to normal erase, but the operating voltage is much lower than the conventional erase voltage. The lower operating voltage only affects the charges in the shallow well region to escaping from the insulating layer, without interfering with the charges in the deep well region. Therefore, the light erase operation can stabilize the threshold voltage of the CTT in a short time.

[0092] Exemplarily, the voltage of the second forward pulse voltage may be 0.9V.

[0093] This embodiment has the following advantages:

[0094] The light erase operation enables the threshold voltage of the programmable CTT to quickly stabilize after programming. This technology can quickly calibrate the circuit with offset voltage without waiting for a long time to determine whether the calibration is successful. In addition, since the threshold voltage stabilizes quickly, this method can also improve the accuracy of offset voltage calibration.

[0095] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the general concept of this application and do not constitute a limitation on the protection scope of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without creative work belong to the protection scope of this application.

Claims

1. A programmable CTT structure, characterized in that: The CTT structure includes: A packaging substrate (100); A drain electrode (200) and a source electrode (300), wherein the drain electrode (200) and the source electrode (300) are respectively built at two ends of the same side of the packaging substrate (100); A substrate (400), the substrate (400) being arranged on a side of the packaging substrate (100) away from the drain (200); A high dielectric constant insulating layer (500), the high dielectric constant insulating layer (500) being arranged on a side of the packaging substrate (100) away from the substrate (400), and a portion where the high dielectric constant insulating layer (500) is connected to the packaging substrate (100) is located between the drain electrode (200) and the source electrode (300); A gate (600) is arranged on a side of the high dielectric constant insulating layer (500) away from the packaging substrate (100).

2. A programmable CTT structure according to claim 1, characterized in that: The high dielectric constant insulating layer (500) comprises: A shallow well region (510), the shallow well region (510) being connected to the packaging substrate (100); A deep well region (520), wherein the deep well region (520) is arranged on a side of the shallow well region (510) away from the packaging substrate (100).

3. A programmable CTT structure according to claim 1, characterized in that: The drain electrode (200) is connected to an external power source (700).

4. A method for rapid stabilization of threshold voltage based on a programmable CTT structure, characterized in that: The method is performed based on the programmable CTT structure according to any one of claims 1 to 3, and the method comprises: When CTT is programmed, electrons are captured from the package substrate into a high-dielectric-constant insulating layer; When the CTT completes programming, some electrons are attracted from the high dielectric constant insulating layer to the packaging substrate.

5. The method for rapid stabilization of threshold voltage based on programmable CTT structure according to claim 4, characterized in that: The method further comprises: When CTT is programmed, electrons are captured from the package substrate into shallow well regions and deep well regions; When the CTT completes programming, electrons are attracted from the shallow well region into the packaging substrate.

6. The method for rapid stabilization of threshold voltage based on programmable CTT structure according to claim 5, characterized in that: The method further comprises: When CTT is programmed, electrons form an electron flow from the source to the drain, and the electrons in the electron flow are attracted from the package substrate to the shallow well region and the deep well region through the gate; When the CTT completes programming, electrons form a reverse electron flow between the high dielectric constant insulating layer and the packaging substrate, and the electrons in the shallow well region are attracted to the packaging substrate by a light erase operation.

7. The method for rapid stabilization of threshold voltage based on programmable CTT structure according to claim 6, characterized in that: The method further comprises: When the CTT is programmed, the source and the substrate are grounded; The drain is connected to an external power supply, and a first positive pulse voltage is applied to the gate; the voltage of the external power supply is 0.9V.

8. The method for rapid stabilization of threshold voltage based on programmable CTT structure according to claim 7, characterized in that: The method further comprises: When the CTT completes programming, the source and the gate are grounded; The drain is connected to the external power source, and a second forward pulse voltage is applied to the substrate.

9. The method for rapid stabilization of threshold voltage based on programmable CTT structure according to claim 8, characterized in that: The voltage magnitude of the second forward pulse voltage is smaller than the voltage magnitude of the first forward pulse voltage.

10. The method for rapid stabilization of threshold voltage based on programmable CTT structure according to claim 9, characterized in that: The light erase operation includes attracting the reverse electron flow at the substrate using the second forward pulse voltage to attract electrons in the shallow well region into the packaging substrate.

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