Double-loop phase-locked low-phase-noise reference local oscillator circuit structure

Abstract

The invention relates to a double-loop phase-locked low-phase-noise reference local oscillator circuit structure which comprises a first phase-locked loop, a first signal processing unit, a power distribution circuit, a second phase-locked loop, a second signal processing unit and a frequency multiplication unit. The output end of the first phase-locked loop is connected with the input end of the first signal processing unit, the output end of the first signal processing unit is connected with the input end of the power distribution circuit, the output end of the power distribution circuit is connected with the input end of the second phase-locked loop, and the output end of the second signal processing unit outputs local oscillator signals through the frequency multiplication unit in sequence. By adopting the double-loop phase-locked low-phase-noise reference local oscillator circuit structure, various reference local oscillator signals can be output at the same time to be provided for the whole system to use through the circuit structure of the multi-path phase-locked loop. By changing the second phase-locked loop, better phase noise than broadband VCO and DDS can be obtained.

Description

Technical Field

[0001] The invention relates to the field of frequency synthesis, in particular to the field of reference local oscillator signals, and specifically refers to a dual-loop phase-locked low phase noise reference local oscillator circuit structure. Background Art

[0002] With the continuous development of electronic technology, the reference local oscillator signal of a single frequency point can no longer meet the needs of increasingly complex electronic systems. In addition, higher requirements are also put forward for the phase noise, spurious and other indicators of the reference local oscillator signal. There are two traditional ways to generate reference local oscillators: direct digital synthesis (DDS) and phase-locked loop (PLL). The first is to perform frequency synthesis through direct digital synthesis to generate the required local oscillator frequency. This method can achieve multi-frequency output and even broadband output. However, the disadvantage is that there are a lot of difficult-to-handle spurious in the generated signal, and it is impossible to obtain very good phase noise. The second is to use phase-locked loop frequency synthesis. The reference signal obtained in this way can achieve low phase noise and low spurious. However, the frequency range of the loop VCO is narrow and cannot meet the requirements of multiple reference frequencies with large differences. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a dual-loop phase-locked low phase noise reference local oscillator circuit structure that meets the requirements of a wide frequency range, good phase noise, and a relatively wide range of applications.

[0004] In order to achieve the above object, the dual-loop phase-locked low phase noise reference local oscillator circuit structure of the present invention is as follows:

[0005] The dual-loop phase-locked low phase noise reference local oscillator circuit structure has the following main features: the system includes a first phase-locked loop, a first signal processing unit, a power distribution circuit, a second phase-locked loop, a second signal processing unit and a frequency multiplication unit; the input end of the first phase-locked loop receives a reference clock signal; the output end of the first phase-locked loop is connected to the input end of the first signal processing unit; the output end of the first signal processing unit is connected to the input end of the power distribution circuit; the output end of the power distribution circuit is connected to the input end of the second phase-locked loop; the output end of the second phase-locked loop is connected to the input end of the second signal processing unit; and the output end of the second signal processing unit outputs the local oscillator signal through the frequency multiplication unit in turn.

[0006] Preferably, the first phase-locked loop includes a first phase detector, a first loop filter, a first voltage-controlled crystal oscillator and a first power divider. The first phase detector, the first loop filter, the first voltage-controlled crystal oscillator and the first power divider are connected in sequence. The input end of the first phase detector receives a reference clock signal, and performs a phase comparison with a feedback signal generated by the power divider of the first power divider. The phase difference between the reference clock signal and the feedback signal is output through a charge pump of the first phase detector, and enters the first voltage-controlled crystal oscillator after low-pass filtering through the first loop filter, and is used as a tuning voltage to adjust the output frequency of the first voltage-controlled crystal oscillator. The first voltage-controlled crystal oscillator outputs a 200MHz signal as a first reference local oscillator signal and outputs it to the first signal processing unit.

[0007] Preferably, the first signal processing unit performs bandpass filtering and signal loss compensation on the first reference local oscillator signal, adjusts the power and spurious of the first reference local oscillator signal, and outputs the first reference local oscillator signal to the power distribution circuit.

[0008] Preferably, the power distribution circuit divides the first reference local oscillator signal into multiple signals, and the multiple signals enter the corresponding number of second phase-locked loops respectively.

[0009] Preferably, the second phase-locked loop includes a second phase detector, a second loop filter, a second voltage-controlled oscillator and a second power divider, and the second phase detector, the second loop filter, the second voltage-controlled oscillator and the second power divider are connected in sequence. The second phase detector compares the phase of the A-channel signal and the feedback signal divided by the second power divider, and filters the result through the second loop filter as a tuning voltage input to the second voltage-controlled oscillator to control the output signal frequency. The second voltage-controlled oscillator outputs a second reference local oscillator signal to the second signal processing unit.

[0010] Preferably, the second signal processing unit filters and compensates for signal loss on the second reference local oscillator signal, adjusts the power and spurious of the second reference local oscillator signal, and outputs the second reference local oscillator signal to multiple frequency multiplication units.

[0011] Preferably, the frequency multiplication unit includes a frequency multiplier and a third signal processing unit. The input end of the frequency multiplier is connected to the second signal processing unit, and the third signal processing unit is connected to the frequency multiplier. The second reference local oscillator signal is multiplied to the required frequency, and the local oscillator signal is finally output after signal processing.

[0012] The dual-loop phase-locked low phase noise reference local oscillator circuit structure of the present invention is adopted. Since the second-stage phase-locked loop generates the reference local oscillator signal through a broadband VCO, a wider local oscillator frequency range can be obtained. Through the circuit structure of the multi-channel phase-locked loop, multiple reference local oscillator signals can be output simultaneously for use by the overall system. Compared with the narrowband VCXO, the broadband VCO has the problem of poor phase noise. By changing the second phase-locked loop, the main phase noise of the output signal will depend on the phase noise of the first reference local oscillator signal. Therefore, better phase noise can be obtained than that of broadband VCO and DDS. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of the dual-loop phase-locked low phase noise reference local oscillator circuit structure of the present invention.

[0014] Figure 2 It is a schematic diagram of the first phase-locked loop, the first signal processing unit and the power distribution circuit of the dual-loop phase-locked low phase noise reference local oscillator circuit structure of the present invention.

[0015] Figure 3 The present invention is a schematic circuit diagram of a second phase-locked loop, a second signal processing unit and a frequency multiplication unit of a dual-loop phase-locked low phase noise reference local oscillator circuit structure. DETAILED DESCRIPTION

[0016] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0017] The dual-loop phase-locked low phase noise reference local oscillator circuit structure of the present invention includes a first phase-locked loop, a first signal processing unit, a power distribution circuit, a second phase-locked loop, a second signal processing unit and a frequency multiplication unit. The input end of the first phase-locked loop receives a reference clock signal, the output end of the first phase-locked loop is connected to the input end of the first signal processing unit, the output end of the first signal processing unit is connected to the input end of the power distribution circuit, the output end of the power distribution circuit is connected to the input end of the second phase-locked loop, the output end of the second phase-locked loop is connected to the input end of the second signal processing unit, and the output end of the second signal processing unit outputs a local oscillator signal through the frequency multiplication unit in turn.

[0018] As a preferred embodiment of the present invention, the first phase-locked loop includes a first phase detector, a first loop filter, a first voltage-controlled crystal oscillator and a first power divider. The first phase detector, the first loop filter, the first voltage-controlled crystal oscillator and the first power divider are connected in sequence. The input end of the first phase detector receives a reference clock signal, and performs a phase comparison with a feedback signal generated by the power divider of the first power divider. The phase difference between the reference clock signal and the feedback signal is output through a charge pump of the first phase detector, and enters the first voltage-controlled crystal oscillator after low-pass filtering through the first loop filter. The first voltage-controlled crystal oscillator is used as a tuning voltage to adjust the output frequency of the first voltage-controlled crystal oscillator. The first voltage-controlled crystal oscillator outputs a 200MHz signal as a first reference local oscillator signal and outputs it to the first signal processing unit.

[0019] As a preferred embodiment of the present invention, the first signal processing unit performs bandpass filtering and signal loss compensation on the first reference local oscillator signal, adjusts the power and spurious of the first reference local oscillator signal, and outputs the first reference local oscillator signal to the power distribution circuit.

[0020] As a preferred embodiment of the present invention, the power distribution circuit divides the first reference local oscillator signal into multiple signals, and the multiple signals enter the corresponding number of second phase-locked loops respectively.

[0021] As a preferred embodiment of the present invention, the second phase-locked loop includes a second phase detector, a second loop filter, a second voltage-controlled oscillator and a second power divider. The second phase detector, the second loop filter, the second voltage-controlled oscillator and the second power divider are connected in sequence. The second phase detector compares the phase of the A-channel signal and the feedback signal divided by the second power divider, and filters the result through the second loop filter as a tuning voltage input to the second voltage-controlled oscillator to control the output signal frequency. The second voltage-controlled oscillator outputs a second reference local oscillator signal to the second signal processing unit.

[0022] As a preferred embodiment of the present invention, the second signal processing unit filters and compensates for signal loss of the second reference local oscillator signal, adjusts the power and spurious of the second reference local oscillator signal, and outputs the second reference local oscillator signal to multiple frequency multiplication units.

[0023] As a preferred embodiment of the present invention, the frequency multiplication unit includes a frequency multiplier and a third signal processing unit. The input end of the frequency multiplier is connected to the second signal processing unit, and the third signal processing unit is connected to the frequency multiplier. The second reference local oscillator signal is multiplied to the required frequency, and the local oscillator signal is finally output after signal processing.

[0024] In a specific implementation of the present invention, a low phase noise reference local oscillator circuit structure is provided for an electronic system requiring a multi-frequency reference signal.

[0025] The circuit structure of the present invention comprises:

[0026] Multiple channels, at least two channels of reference local oscillator output circuits with different frequencies.

[0027] A first phase-locked loop, a first signal processing unit, a power distribution circuit, a second phase-locked loop, a second signal processing unit, a frequency multiplier, and a third signal processing unit.

[0028] The reference clock signal enters from the input end of the first phase-locked loop, the output end of the first phase-locked loop is connected to the input end of the first signal processing unit, the output end of the first signal processing unit is connected to the input end of the power distribution circuit, the output end of the power distribution circuit is connected to the input end of the second phase-locked loop, and the output end of the second phase-locked loop is connected to the input end of the second signal processing unit. The output end of the second signal processing unit sequentially outputs the local oscillator signal through the frequency multiplication unit.

[0029] The first phase-locked loop includes a first phase detector, a first loop filter, a first voltage-controlled crystal oscillator (VCXO) and a first power divider. The reference clock signal enters the first phase detector, and after phase comparison with the feedback signal generated by the first power divider, the phase difference between the reference clock signal and the feedback signal is output through the charge pump of the first phase detector, and after low-pass filtering through the first loop filter, enters the first voltage-controlled crystal oscillator as a tuning voltage to adjust the output frequency of the first voltage-controlled crystal oscillator, and finally the first voltage-controlled crystal oscillator outputs a 200MHz signal as a first reference local oscillator signal to the first signal processing unit.

[0030] The first signal processing unit is used to perform bandpass filtering and signal loss compensation on the first reference local oscillator signal, adjust the power and spurious of the first reference local oscillator signal to the required level, and then output the first reference local oscillator signal to the power distribution circuit.

[0031] The power distribution circuit divides the first reference local oscillator signal into multiple signals, taking the two-way power division as an example, the first reference local oscillator signal is divided into A-way signal and B-way signal. The circuit structures of A-way and B-way are the same except for the frequency, taking A-way as an example. The A-way signal enters the second phase-locked loop.

[0032] The second phase-locked loop is composed of a second phase detector, a second loop filter, a second voltage-controlled oscillator (VCO) and a second power divider. The second phase detector compares the phase of the A-channel signal and the feedback signal separated by the second power divider, filters the result through the second loop filter and inputs it as a tuning voltage to the second voltage-controlled oscillator to control the output signal frequency. The second voltage-controlled oscillator outputs a second reference local oscillator signal to the second signal processing unit.

[0033] The second signal processing unit filters and compensates for signal loss on the second reference local oscillator signal, and then outputs the second reference local oscillator signal to the frequency multiplication unit.

[0034] The frequency multiplication unit is composed of a frequency multiplier and a third signal processing unit, which multiplies the second reference local oscillator signal to a required frequency, and finally outputs the local oscillator signal after signal processing.

[0035] In the embodiments of the present invention, Figure 1 As shown, in this embodiment, the circuit simultaneously outputs 4 reference local oscillators of different frequencies.

[0036] The power distribution circuit divides the first reference local oscillator signal into four signals, namely, A, B, C and D signals. The four circuit structures have the same principle except for the frequency, and the four signals enter four second phase-locked loops respectively.

[0037] The second phase-locked loop is composed of a second phase detector, a second loop filter, a second voltage-controlled oscillator (VCO) and a second power divider. The second phase detector compares the phase of the second reference frequency signal and the feedback signal divided by the second power divider, and filters the result through the second loop filter as a tuning voltage input to the second voltage-controlled oscillator to control the output signal frequency. The four second voltage-controlled oscillators respectively output second reference local oscillator signals of frequencies A, B, C, and D to the corresponding second signal processing units.

[0038] The four-way second signal processing unit filters and compensates for signal loss on the second reference local oscillator signal, adjusts the power and spurious of the second reference local oscillator signal to the required level, and then outputs the four-way second reference local oscillator signal to four frequency multiplication units respectively.

[0039] The frequency multiplication unit is composed of a frequency multiplier and a third signal processing unit, which multiplies the second reference local oscillator signal to the required frequency, and finally outputs four local oscillator signals A, B, C, and D after signal processing.

[0040] This design has 4 reference local oscillator outputs with different frequencies. The number of channels can be increased or decreased as needed. And the single channel can be turned on or off by controlling the channel power switch, so the idle channel can be turned off to reduce system power consumption.

[0041] This design uses dual-loop phase-locking, with the first phase-locked loop providing a low phase-noise local signal, and multiple second phase-locked loops to achieve multi-frequency reference local oscillator outputs, thereby meeting system requirements for a large number of reference local oscillator frequency types and high phase noise requirements.

[0042] The specific implementation scheme of this embodiment can refer to the relevant description in the above embodiment, which will not be repeated here.

[0043] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0044] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0045] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0046] The dual-loop phase-locked low phase noise reference local oscillator circuit structure of the present invention is adopted. Since the second-stage phase-locked loop generates the reference local oscillator signal through a broadband VCO, a wider local oscillator frequency range can be obtained. Through the circuit structure of the multi-channel phase-locked loop, multiple reference local oscillator signals can be output simultaneously for use by the overall system. Compared with the narrowband VCXO, the broadband VCO has the problem of poor phase noise. By changing the second phase-locked loop, the main phase noise of the output signal will depend on the phase noise of the first reference local oscillator signal. Therefore, better phase noise can be obtained than that of broadband VCO and DDS.

[0047] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A dual-loop phase-locked low phase noise reference local oscillator circuit structure, characterized in that: The system includes a first phase-locked loop, a first signal processing unit, a power distribution circuit, a second phase-locked loop, a second signal processing unit and a frequency multiplication unit. The input end of the first phase-locked loop receives a reference clock signal, the output end of the first phase-locked loop is connected to the input end of the first signal processing unit, the output end of the first signal processing unit is connected to the input end of the power distribution circuit, the output end of the power distribution circuit is connected to the input end of the second phase-locked loop, the output end of the second phase-locked loop is connected to the input end of the second signal processing unit, and the output end of the second signal processing unit outputs a local oscillator signal through the frequency multiplication unit in turn.

2. The dual-loop phase-locked low phase noise reference local oscillator circuit structure according to claim 1, characterized in that: The first phase-locked loop includes a first phase detector, a first loop filter, a first voltage-controlled crystal oscillator and a first power divider. The first phase detector, the first loop filter, the first voltage-controlled crystal oscillator and the first power divider are connected in sequence. The input end of the first phase detector receives a reference clock signal, and compares the phase with the feedback signal generated by the power division of the first power divider. The phase difference between the reference clock signal and the feedback signal is output through the charge pump of the first phase detector, and enters the first voltage-controlled crystal oscillator after low-pass filtering through the first loop filter. The first voltage-controlled crystal oscillator is used as a tuning voltage to adjust the output frequency of the first voltage-controlled crystal oscillator. The first voltage-controlled crystal oscillator outputs a 200MHz signal as a first reference local oscillator signal and outputs it to the first signal processing unit.

3. The dual-loop phase-locked low phase noise reference local oscillator circuit structure according to claim 1, characterized in that: The first signal processing unit performs bandpass filtering and signal loss compensation on the first reference local oscillator signal, adjusts the power and spurious of the first reference local oscillator signal, and outputs the first reference local oscillator signal to the power distribution circuit.

4. The dual-loop phase-locked low phase noise reference local oscillator circuit structure according to claim 1, characterized in that: The power distribution circuit divides the first reference local oscillator signal into multiple signals, and the multiple signals enter the corresponding number of second phase-locked loops respectively.

5. The dual-loop phase-locked low phase noise reference local oscillator circuit structure according to claim 1, characterized in that: The second phase-locked loop includes a second phase detector, a second loop filter, a second voltage-controlled oscillator and a second power divider. The second phase detector, the second loop filter, the second voltage-controlled oscillator and the second power divider are connected in sequence. The second phase detector compares the phase of the A-channel signal and the feedback signal separated by the second power divider, and filters the result through the second loop filter as a tuning voltage input to the second voltage-controlled oscillator to control the output signal frequency. The second voltage-controlled oscillator outputs a second reference local oscillator signal to the second signal processing unit.

6. The dual-loop phase-locked low phase noise reference local oscillator circuit structure according to claim 1, characterized in that: The second signal processing unit filters and compensates for signal loss on the second reference local oscillator signal, adjusts the power and spurious of the second reference local oscillator signal, and outputs the second reference local oscillator signal to multiple frequency multiplication units.

7. The dual-loop phase-locked low phase noise reference local oscillator circuit structure according to claim 1, characterized in that: The frequency multiplication unit includes a frequency multiplier and a third signal processing unit. The input end of the frequency multiplier is connected to the second signal processing unit, and the third signal processing unit is connected to the frequency multiplier. The second reference local oscillator signal is multiplied to the required frequency, and the local oscillator signal is finally output after signal processing.

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