A scanning driving circuit, a display panel and a driving method thereof, and a display device

Abstract

Embodiments of the present disclosure provide a scan driving circuit, a display panel and a driving method thereof, and a display device. The scan driving circuit comprises a driving signal generation module and a signal output control module. The driving signal generation module is coupled with an input signal terminal, a clock signal terminal and a first output signal terminal respectively. The driving signal generation module is configured to provide a signal of the clock signal terminal to the first output signal terminal under the control of the input signal terminal. The signal output control module is coupled with a trigger signal terminal, a first power supply terminal, the first output signal terminal and a second output signal terminal respectively. The first output signal terminal provides a first signal to the second output signal terminal. The signal output control module is configured to provide a second signal to the second output signal terminal from the first power supply terminal under the control of the trigger signal terminal to pull down the first signal. The technical solution of the present disclosure can control the output signal of the second output signal terminal of the scan driving circuit, realize row-by-row frequency division display in the same frame, and reduce power consumption.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display devices, and in particular, to a scan driving circuit, a display panel and a driving method thereof, and a display device. BACKGROUND

[0002] At present, a display panel works according to a set frequency, and the frequency of a display area of the display panel is fixed in a frame, which causes power consumption loss of the display panel. SUMMARY

[0003] Embodiments of the present disclosure provide a scan driving circuit, a display panel and a driving method thereof, and a display device to solve or alleviate one or more technical problems in the prior art.

[0004] As a first aspect of the embodiments of the present disclosure, a scan driving circuit is provided, which includes a driving signal generation module and a signal output control module. The driving signal generation module is coupled with an input signal terminal, a clock signal terminal and a first output signal terminal respectively. The driving signal generation module is configured to provide a signal of the clock signal terminal to the first output signal terminal under the control of the input signal terminal. The signal output control module is coupled with a trigger signal terminal, a first power supply terminal, the first output signal terminal and a second output signal terminal respectively. The signal output control module is configured to provide a signal of the first power supply terminal to the second output signal terminal to control the voltage of the signal of the first output signal terminal, or provide a signal of the first output signal terminal to the second output signal terminal under the control of the trigger signal terminal.

[0005] In some possible implementation manners, the signal output control module includes a first control transistor and a second control transistor. A gate of the first control transistor is coupled with the first output signal terminal. A first pole of the first control transistor is coupled with the first output signal terminal. A second pole of the second control transistor is coupled with the first power supply terminal. A gate of the second control transistor is coupled with the trigger signal terminal. The second output signal terminal is coupled with a second pole of the first control transistor. The second output signal terminal is coupled with a first pole of the second control transistor.

[0006] In some possible implementation manners, the second signal is a constant voltage signal, and the first signal is a pulse signal.

[0007] In some possible implementation manners, the driving signal generation module includes a pull-up module, an output module, a first reset module, a pull-down module, a noise elimination module, a second reset module, a reset control module and a third reset module.

[0008] The pull-up module is coupled with the input signal terminal, a second power supply terminal and a pull-up node respectively. The pull-up module is configured to provide a signal of the second power supply terminal to the pull-up node under the control of the input signal terminal.

[0009] The output module is coupled with the clock signal end, the pull-up node and the first output signal end respectively, and is configured to provide a signal of the clock signal end to the first output signal end under control of the pull-up node;

[0010] The first reset module is coupled with the reset signal end, the third power supply end and the pull-up node respectively, and is configured to provide a signal of the third power supply end to the pull-up node under control of the reset signal end

[0011] The pull-down module is coupled with the fourth power supply end, the pull-up node and the control node respectively, and is configured to provide a signal of the fourth power supply end to the pull-down node and the control node under control of the pull-up node;

[0012] The noise elimination module is coupled with the first control power supply end, the control node and the pull-down node respectively, and is configured to provide a signal of the first control power supply end to the control node under control of the first control power supply end, and provide a signal of the first control power supply end to the pull-down node under control of the control node;

[0013] The second reset module is coupled with the pull-down node, the fourth power supply end and the first output signal end respectively, and is configured to provide a signal of the fourth power supply end to the first output signal end under control of the pull-down node;

[0014] The reset control module is coupled with the pull-down node, the fourth power supply end and the pull-up node respectively, and is configured to provide a signal of the fourth power supply end to the pull-up node under control of the pull-down node;

[0015] The frame reset module is coupled with the fourth power supply end, the first output signal end and the second control power supply end respectively, and is configured to provide a signal of the fourth power supply end to the first output signal end under control of the second control power supply end.

[0016] In some possible implementation manners, at least one of the following is included:

[0017] The pull-up module includes a first transistor, a gate of the first transistor is coupled with the input signal end, a first pole of the first transistor is coupled with the second power supply end, and a second pole of the first transistor is coupled with the pull-up node;

[0018] The output module includes a third transistor and a storage capacitor, a gate of the third transistor is coupled with the pull-up node, a first pole of the third transistor is coupled with the clock signal end, a second pole of the third transistor is coupled with the first output signal end, a first plate of the storage capacitor is coupled with the pull-up node, and a second plate of the storage capacitor is coupled with the first output signal end;

[0019] The first reset module includes a second transistor, a gate of the second transistor is coupled with the reset signal end, a first pole of the second transistor is coupled with the third power supply end, and a second pole of the second transistor is coupled with the pull-up node;

[0020] The pull-down module includes a sixth transistor and an eighth transistor, wherein the gate of the sixth transistor is coupled to the pull-up node, the first electrode of the sixth transistor is coupled to the pull-down node, the second electrode of the sixth transistor is coupled to the fourth power supply terminal, the gate of the eighth transistor is coupled to the pull-up node, the first electrode of the eighth transistor is coupled to the control node, and the second electrode of the eighth transistor is coupled to the fourth power supply terminal;

[0021] The noise reduction module includes a fifth transistor and a ninth transistor, wherein the gate of the ninth transistor is coupled to the first control power supply terminal, the first electrode of the ninth transistor is respectively coupled to the first control power supply terminal, the second electrode of the ninth transistor is coupled to the control node, the gate of the fifth transistor is coupled to the control node, the first electrode of the fifth transistor is coupled to the first control power supply terminal, and the second electrode of the fifth transistor is coupled to the pull-down node;

[0022] The second reset module includes an eleventh transistor, a gate of the eleventh transistor is coupled to the pull-down node, a first electrode of the eleventh transistor is coupled to the fourth power supply terminal, and a second electrode of the eleventh transistor is coupled to the first output signal terminal;

[0023] The reset control module includes a tenth transistor, a gate of the tenth transistor is coupled to the pull-down node, a first electrode of the tenth transistor is coupled to the fourth power supply terminal, and a second electrode of the tenth transistor is coupled to the pull-up node;

[0024] The frame reset module includes a seventh transistor, a gate of the seventh transistor is coupled to the second control power terminal, a first electrode of the seventh transistor is coupled to the fourth power terminal, and a second electrode of the seventh transistor is coupled to the first output signal terminal.

[0025] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display panel, including a gate signal generating module, including multiple cascaded gate driving circuits, and the gate driving circuit is a scan driving circuit of any disclosed embodiment of the present disclosure.

[0026] In some possible embodiments, the display panel includes a first display area and a second display area, the first display area includes N gate lines, the N gate lines are correspondingly connected to N gate drive circuits, the second display area includes M gate lines, the M gate lines are correspondingly connected to M gate drive circuits, M and N are positive integers greater than 0, the voltage value of the signal of the gate drive circuit corresponding to the first display area is a first voltage, the voltage value of the signal of the gate drive circuit corresponding to the second display area is a second voltage, and the first voltage is less than the second voltage.

[0027] In some possible implementations, the display panel further includes a data chip. When the data chip is turned on, it transmits data signals to the corresponding rows of the second display area. When the data chip is turned off, it transmits data signals to the corresponding rows of the first display area.

[0028] As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a method for driving a display panel, which is applied to the display panel of any embodiment of the present disclosure, and the method includes:

[0029] The trigger signal terminal provides a trigger signal to control the first output signal terminal to provide a signal to the second output signal terminal, or controls the first power supply terminal to provide a signal to the second output signal terminal to control the voltage of the signal at the first output signal terminal.

[0030] In some possible implementations, the method further includes:

[0031] The trigger signal terminal of the gate driving circuit corresponding to the first display area provides a first trigger signal, controls the first power supply terminal to provide a signal to the second output signal terminal to control the voltage of the signal at the first output signal terminal;

[0032] The trigger signal terminal of the gate driving circuit corresponding to the second display area provides a second trigger signal to control the first output signal terminal to provide a signal to the second output signal terminal.

[0033] In some possible implementations, the method further includes:

[0034] The data chip controls the data signal to be transmitted to the corresponding row of the second display area, and the data chip controls the data signal to stop being transmitted to the corresponding row of the first display area.

[0035] As a fourth aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device, comprising the display panel of any embodiment of the present disclosure.

[0036] The technical solution of the embodiment of the present disclosure can achieve the following beneficial effects: the output signal of the second output signal terminal of the scan driving circuit can be controlled to realize line-by-line and frequency-by-frequency display within the same frame, thereby reducing power consumption.

[0037] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0039] Figure 1 Schematic diagram of the structure of the scan driving circuit according to an embodiment of the present disclosure;

[0040] Figure 2 A schematic diagram of a scan driving circuit structure of an embodiment of the present disclosure;

[0041] Figure 3 A schematic diagram of a scan driving circuit of an embodiment of the present disclosure;

[0042] Figure 4 A timing diagram of a driving signal generation module of an embodiment of the present disclosure;

[0043] Figure 5 A schematic diagram of a gate signal generation module of an embodiment of the present disclosure;

[0044] Figure 6 A schematic diagram of a display area of a display panel of an embodiment of the present disclosure;

[0045] Figure 7 A timing diagram of a display panel of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] In the following, only certain exemplary embodiments are simply described. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and the description are considered to be exemplary in nature rather than limiting.

[0047] The transistors employed in all embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics, and the transistors employed in embodiments of the present disclosure are mainly switching transistors according to their roles in the circuit. Since the source and the drain of the switching transistor employed here are symmetrical, the source and the drain can be interchangeable. In embodiments of the present disclosure, the source (source electrode) is referred to as the first pole, and the drain (drain electrode) is referred to as the second pole, or the drain can be referred to as the first pole, and the source is referred to as the second pole. According to the configuration in the drawings, the middle end of the transistor is referred to as the gate (also referred to as the gate electrode), the signal input end is referred to as the source, and the signal output end is referred to as the drain.

[0048] The switching transistor employed in embodiments of the present disclosure can be a P-type switching transistor or an N-type switching transistor. The P-type switching transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level. The N-type switching transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level. In addition, a plurality of signals in each embodiment of the present disclosure correspond to a first potential and a second potential. The first potential and the second potential only represent two different potential states of the signal, and do not represent that the first potential or the second potential has a specific value throughout the text. Embodiments of the present disclosure are described by taking the first potential as an effective potential as an example.

[0049] The coupling may include direct physical contact between the two ends or indirect connection between the two ends (eg, connection between the two ends via a signal line). The embodiment of the present disclosure does not limit the coupling method between the two ends.

[0050] At present, the display panel uses a high frequency to ensure the image quality for dynamic images, and a low frequency to reduce power consumption for static images or slow dynamic images. This can reduce the power consumption of the display panel by switching the frequency between different frames. Since the gate drive circuit of the display panel outputs line by line, the frequency and duty cycle of the output signal are determined by the clock signal and cannot be adjusted within a frame. Therefore, when a frame of display includes a static display area and a dynamic display area, since the display panel of the related art cannot allocate different frequencies according to different rows within a frame, this results in the need to use high frequencies for both the static display area and the dynamic display area, resulting in power consumption loss of the display panel. It should be noted that the static display area is a static picture or a slow dynamic picture, and the dynamic display area is a dynamic picture.

[0051] In order to solve the power consumption loss problem in the related art, an embodiment of the present disclosure provides a scan driving circuit. The technical solution of the present disclosure is described in detail below through embodiments.

[0052] Figure 1 FIG. 1 is a schematic diagram of the structure of the scan drive circuit according to an embodiment of the present disclosure. Figure 1 As shown, the scan driving circuit according to the embodiment of the present disclosure may include a driving signal generating module 10 and a signal output control module 20 .

[0053] In one embodiment, Figure 1 As shown, the driving signal generating module 10 is coupled to the input signal terminal INPUT, the clock signal terminal CLK and the first output signal terminal OUTPUT_1 respectively. The driving signal generating module 10 is configured to provide the signal of the clock signal terminal CLK to the first output signal terminal OUTPUT_1 under the control of the input signal terminal INPUT.

[0054] In one embodiment, Figure 1 As shown, the signal output control module 20 is coupled to the trigger signal terminal Vf, the first power terminal VGL_1, the first output signal terminal OUTPUT_1, and the second output signal terminal OUTPUT_2, respectively. The first output signal terminal OUTPUT_1 provides a first signal to the second output signal terminal OUTPUT_2. The signal output control module 20 is configured such that, under the control of the trigger signal terminal Vf, the first power terminal VGL_1 provides a second signal to the second output signal terminal OUTPUT_2 to pull down the first signal.

[0055] It should be noted that in the display panel, the second output signal terminal OUTPUT_2 of the scan driving circuit can be connected with the gate line of the display panel, so as to provide the gate driving signal to the gate line.

[0056] The scan driving circuit of the embodiment of the present disclosure, under the control of the trigger signal terminal Vf, the first power supply terminal VGL_1 provides the second signal to the second output signal terminal OUTPUT_2, and the second signal can adjust the first signal output by the first output signal terminal OUTPUT_1 to the second output signal terminal OUTPUT_2. In this way, the scan driving circuit can be controlled to output the signal of the first output signal terminal OUTPUT_1 adjusted according to the first power supply terminal VGL_1 according to the requirements of the display area of the display panel, so as to realize that the second output signal terminal provides different driving signals in different display areas in a frame of picture.

[0057] The scan driving circuit of the embodiment of the present disclosure applied to the display panel can provide different driving signals to the dynamic display area and the static display area in a frame of picture of the display panel respectively, so as to reduce the power consumption of the static display area in the related art, and further reduce the power consumption of the display panel.

[0058] Exemplarily, the signal of the first power supply terminal VGL_1 is a low-level signal, and under the control of the trigger signal terminal Vf, the first power supply terminal VGL_1 provides the second signal as a low-level signal to the second output signal terminal OUTPUT_2, and the second signal can pull down the level of the first output signal terminal OUTPUT_1 transmitted to the second output signal terminal OUTPUT_2. The trigger signal terminal Vf controls the first power supply terminal VGL_1 not to provide the second signal to the second output signal terminal OUTPUT_2, and the first output signal terminal OUTPUT_1 maintains normal output, so that the level of the first output signal terminal OUTPUT_1 can be pulled down by the first power supply terminal VGL_1 in the static display area through the control of the trigger signal terminal, and the first output signal terminal OUTPUT_1 normally outputs to the second output signal terminal OUTPUT_2 in the dynamic display area, so as to reduce the power consumption.

[0059] Figure 2 The structure diagram of the scan driving circuit of the embodiment of the present disclosure is shown in FIG. 1, Figure 3 The structure diagram of the scan driving circuit of the embodiment of the present disclosure is shown in FIG. 1, Figure 3As shown, the signal output control module 20 comprises a first control transistor M12 and a second control transistor M13. The gate of the first control transistor M12 is coupled with the first output signal terminal OUTPUT_1, the first pole of the first control transistor M12 is coupled with the first output signal terminal OUTPUT_1, and the second pole of the first control transistor M12 is coupled with the second output signal terminal OUTPUT_2. The second pole of the second control transistor M13 is coupled with the first power supply terminal VGL_1, the gate of the second control transistor M13 is coupled with the trigger signal terminal Vf, and the first pole of the second control transistor M13 is coupled with the second output signal terminal OUTPUT_2.

[0060] The signal of the first output signal terminal OUTPUT_1 is connected with the gate and the first pole of the first control transistor M12, and the signal of the first output signal terminal OUTPUT_1 is a pulse signal. When the signal of the first output signal terminal OUTPUT_1 is a first potential, the first control transistor M12 is turned on, and when the signal of the first output signal terminal OUTPUT_1 is a second potential, the first control transistor M12 is turned off. When the trigger signal terminal Vf is a high-level signal, the second control transistor M13 is turned on, and the first power supply terminal VGL_1 provides a second signal to the second output signal terminal OUTPUT_2. When the trigger signal terminal Vf is a low-level signal, the second control transistor M13 is turned off, and the first power supply terminal VGL_1 does not provide the second signal to the second output signal terminal OUTPUT_2.

[0061] The first power supply terminal VGL_1 is a low-level signal. When the trigger signal terminal Vf is a high-level signal, the second control transistor M13 is turned on, and the second signal can pull down the potential of the second output signal terminal OUTPUT_2. The gate of the transistor in the display area is a low potential, the transistor is turned off, and the pixel enters a holding state. When the trigger signal terminal Vf is a low-level signal, the second control transistor M13 is turned off, and the second output signal terminal OUTPUT_2 maintains the normal potential of the first output signal terminal OUTPUT_1, and the display area displays normally.

[0062] Exemplarily, the first control transistor M12 can be a P-type switching transistor, and the second control transistor M13 can be an N-type switching transistor. Alternatively, the first control transistor M12 can be an N-type switching transistor, and the second control transistor M13 can be a P-type switching transistor. The first control transistor M12 and the second control transistor M13 can both be P-type switching transistors or N-type switching transistors.

[0063] Exemplarily, the second control transistor M13 is an N-type switch transistor. When the trigger signal end Vf is a high potential signal, the second control transistor M13 is turned on, and the second output signal end OUTPUT_2 is pulled low to the low level of the first power supply end VGL_1, so that the gate line corresponding to the display area of the display panel is at a low level, and the display panel enters a holding state. When the trigger signal end Vf is a low level signal, the second control transistor M13 is turned off, and the second output signal end OUTPUT_2 normally outputs the signal of the first output signal end OUTPUT_1, and the display area is in a normal refreshable state.

[0064] In an embodiment, the signal of the first power supply end VGL_1 is a constant voltage signal, and the signal of the first output signal end OUTPUT_1 is a pulse signal. The second signal provided by the first power supply end VGL_1 to the second output signal end OUTPUT_2 is a constant voltage signal, and the signal transmitted by the first output signal end OUTPUT_1 to the second output signal end OUTPUT_2 is a pulse signal. The first power supply end VGL_1 can pull the signal of the first output signal end OUTPUT_1 low, so as to realize frequency and row division display for the static display area and the dynamic display area, and reduce power consumption.

[0065] Exemplarily, the signal of the first power supply end VGL_1 is a low level signal. It should be noted that the voltage of the first output signal end OUTPUT_1 is a pulse voltage, the first output signal end OUTPUT_1 includes a first voltage signal and a second voltage signal, the voltage value of the first voltage signal is greater than the voltage value of the second voltage signal, the signal of the first power supply end VGL_1 is a third voltage signal, the voltage value of the third voltage signal can be greater than or equal to the voltage value of the first voltage signal, the direction of the third voltage signal is opposite to the direction of the first voltage signal, and the specific voltage value of the signal of the first power supply end VGL_1 can be set according to actual needs. The first power supply end VGL_1 can pull the level of the second output signal end low, so that the gate of the corresponding display area is at a low level, and the pixel enters a holding state, so that the display area can be kept in a static picture, and power consumption is reduced.

[0066] Reference Figure 2 In an embodiment, the driving signal generation module 10 at least includes a pull-up module 11, an output module 12, a first reset module 13, a pull-down module 14, a noise elimination module 15, a second reset module 16, a reset control module 17, and a frame reset module 18.

[0067] In an embodiment, as shown in Figure 2 The pull-up module 11 is coupled with the input signal end INPUT, the second power supply end VDD, and the pull-up node PU. The pull-up module 11 is configured to provide the signal of the second power supply end VDD to the pull-up node PU under the control of the input signal end INPUT.

[0068] In one embodiment, as shown in FIG. 1, the output module 12 is coupled with the clock signal terminal CLK, the pull-up node PU and the first output signal terminal OUTPUT_1, respectively. The output module 12 is configured to provide the signal of the clock signal terminal CLK to the first output signal terminal OUTPUT_1 under the control of the pull-up node PU. Figure 2

[0069] In one embodiment, as shown in FIG. 1, the first reset module 13 is coupled with the reset signal terminal RST, the third power supply terminal VSS and the pull-up node PU, respectively. The first reset module 13 is configured to provide the signal of the third power supply terminal VSS to the pull-up node PU under the control of the reset signal terminal RST. Figure 2

[0070] In one embodiment, as shown in FIG. 1, the pull-down module 14 is coupled with the fourth power supply terminal VGL_2, the pull-up node PU and the control node PD_CN, respectively. The pull-down module 14 is configured to provide the signal of the fourth power supply terminal VGL_2 to the pull-down node PD and the control node PD_CN under the control of the pull-up node PU. Figure 2

[0071] In one embodiment, as shown in FIG. 1, the noise release module 15 is coupled with the first control power supply terminal VGH, the control node PD_CN and the pull-down node PD, respectively. The noise release module 15 is configured to provide the signal of the first control power supply terminal VGH to the control node PD_CN under the control of the first control power supply terminal VGH, and to provide the signal of the first control power supply terminal VGH to the pull-down node PD under the control of the control node PD_CN. Figure 2

[0072] In one embodiment, as shown in FIG. 1, the second reset module 16 is coupled with the pull-down node PD, the fourth power supply terminal VGL_2 and the first output signal terminal OUTPUT_1, respectively. The second reset module 16 is configured to provide the signal of the fourth power supply terminal VGL_2 to the first output signal terminal OUTPUT_1 under the control of the pull-down node PD. Figure 2

[0073] In one embodiment, as shown in FIG. 1, the reset control module 17 is coupled with the pull-down node PD, the fourth power supply terminal VGL_2 and the pull-up node PU, respectively. The reset control module 17 is configured to provide the signal of the fourth power supply terminal VGL_2 to the pull-up node PU under the control of the pull-down node PD. Figure 2

[0074] In one embodiment, as shown in FIG. 1, the reset control module 17 is coupled with the pull-down node PD, the fourth power supply terminal VGL_2 and the pull-up node PU, respectively. The reset control module 17 is configured to provide the signal of the fourth power supply terminal VGL_2 to the pull-up node PU under the control of the pull-down node PD. Figure 2 ​​​​​​As shown, the frame reset module 18 is coupled to the fourth power terminal VGL_2 and the first output signal terminal OUTPUT_1 respectively. The third reset module 18 is configured to provide a signal of the fourth power terminal VGL_2 to the first output signal terminal OUTPUT_1 under the control of the fourth power terminal VGL_2.

[0075] When the scan drive circuit of the disclosed embodiment is applied to a display panel, the second output signal terminal OUTPUT_2 can be connected to the gate line so as to provide a gate drive signal to the gate line. In a frame, the scan drive circuit may include a driving phase and a reset phase. In the driving phase, the pull-up module 11, under the control of the input signal terminal INPUT, provides a signal of the second power supply terminal VDD to the pull-up node PU. At this time, the voltage of the pull-up stage PU is identical to the voltage of the second power supply terminal VDD. The output module 12, under the control of the pull-up node PU, provides a signal of the clock signal terminal CLK to the first output signal terminal OUTPUT_1. When the first output signal terminal OUTPUT_1 provides a signal to the second output signal terminal OUTPUT_2, the second output signal terminal OUTPUT_2 provides a gate signal to the gate line, drives the corresponding row pixel display. During the reset phase, the first reset module 13, under the control of the reset signal terminal RST, provides a signal from the third power supply terminal VSS to the pull-up node PU. At this point, the voltage at the pull-up node PU is the same as the voltage at the third power supply terminal VSS. The output module 12 is turned off, and no signal is output from the first output signal terminal OUTPUT_1. The corresponding row of pixels does not display. The second power supply terminal VDD is a high-level signal, and the third power supply terminal VSS is a low-level signal. During the reset phase, the pull-up node PU maintains the signal from the third power supply terminal VSS.

[0076] In one embodiment, Figure 3 As shown, the pull-up module 11 may include a first transistor M1. The gate of the first transistor M1 is coupled to the input signal terminal INPUT, the first electrode of the first transistor M1 is coupled to the second power supply terminal VDD, and the second electrode of the first transistor M1 is coupled to the pull-up node PU. Therefore, when the input signal terminal INPUT is a valid level signal, the first transistor M1, under the control of the valid level signal of the input signal terminal INPUT, provides the signal of the second power supply terminal VDD to the pull-up node PU, thereby pulling up the pull-up node PU.

[0077] In one embodiment, Figure 3As shown, the output module 12 can include a third transistor M3 and a storage capacitor C. The gate of the third transistor M3 is coupled with the pull-up node PU, the first pole of the third transistor M3 is coupled with the clock signal end CLK, and the second pole of the third transistor M3 is coupled with the first output signal end OUTPUT_1. The first plate of the storage capacitor C is coupled with the pull-up node PU, and the second plate of the storage capacitor C is coupled with the first output signal end OUTPUT_1. Thus, when the pull-up node PU is the active level signal, the third transistor M3 provides the signal of the clock signal end CLK to the first output signal end OUTPUT_1 under the control of the active level signal of the pull-up node PU, so that the first output signal end OUTPUT_1 outputs the driving signal.

[0078] In an embodiment, the second power supply end VDD can be a high level signal. The third power supply end VSS can be a low level signal, the fourth power supply end VGL_2 can be a low level signal, and the first control power supply end VGH can be a high level signal.

[0079] It should be noted that although the second power supply end VDD is a high level signal and the first control power supply end VGH is a high level signal, it does not mean that the voltage of the second power supply end VDD is the same as the voltage of the first control power supply end VGH. The voltage of the second power supply end VDD can be the same as or different from the voltage of the first control power supply end VGH, and the specific voltage value of the second power supply end VDD and the specific voltage value of the first control power supply end VGH can be set as needed. Similarly, although the fourth power supply end VGL_2 is a low level signal and the third power supply end VSS is a low level signal, it does not mean that the voltage of the fourth power supply end VGL_2 is the same as the voltage of the third power supply end VSS. The voltage of the fourth power supply end VGL_2 can be the same as or different from the voltage of the third power supply end VSS, and the specific voltage value of the fourth power supply end VGL_2 and the specific voltage value of the third power supply end VSS can be set as needed.

[0080] In an embodiment, as shown in FIG. 1, Figure 3 The first reset module 13 can include a second transistor M2. The gate of the second transistor M2 is coupled with the reset signal end RST, the first pole of the second transistor M2 is coupled with the third power supply end VSS, and the second pole of the second transistor M2 is coupled with the pull-up node PU. Thus, when the reset signal end RST is the active level signal, the second transistor M2 provides the signal of the third power supply end VSS to the pull-up node PU under the control of the active level signal of the reset signal end RST, so that the pull-up node PU is reset.

[0081] In an embodiment, as shown in FIG. 1, Figure 3As shown, the pull-down module 14 can include a sixth transistor M6 and an eighth transistor M8. The gate of the sixth transistor M6 is coupled with the pull-up node PU, the first pole of the sixth transistor M6 is coupled with the pull-down node PD, and the second pole of the sixth transistor M6 is coupled with the fourth power supply end VGL_2. The gate of the eighth transistor M8 is coupled with the pull-up node PU, the first pole of the eighth transistor M8 is coupled with the control node PD_CN, and the second pole of the eighth transistor M8 is coupled with the fourth power supply end VGL_2. Thus, when the pull-up node PU is an active level signal, the sixth transistor M6 provides the signal of the fourth power supply end VGL_2 to the pull-down node PD under the control of the active level signal of the pull-up node PU, and pulls down the pull-down node PD. The eighth transistor M8 provides the signal of the fourth power supply end VGL_2 to the control node PD_CN under the control of the active level signal of the pull-up node PU, and pulls down the control node PD_CN.

[0082] Exemplarily, the sixth transistor M6 and the eighth transistor M8 can be of the same type. For example, the sixth transistor M6 and the eighth transistor M8 can both be NMOS.

[0083] In an embodiment, as shown in FIG. 1, the pull-down module 14 can include a sixth transistor M6 and an eighth transistor M8. Figure 3 As shown, the noise release module 15 includes a fifth transistor M5 and a ninth transistor M9. The gate of the ninth transistor M9 is coupled with the first control power supply end VGH, the first pole of the ninth transistor M9 is coupled with the first control power supply end VGH, and the second pole of the ninth transistor M9 is coupled with the control node PD_CN. Thus, when the first control power supply end VGH is an active level, the ninth transistor M9 can provide the signal of the first control power supply end VGH to the control node PD_CN under the control of the active level of the first control power supply end VGH.

[0084] The gate of the fifth transistor M5 is coupled with the control node PD_CN, the first pole of the fifth transistor M5 is coupled with the first control power supply end VGH, and the second pole of the fifth transistor M5 is coupled with the pull-down node PD. When the signal of the control node PD_CN is an active level, the fifth transistor M5 can provide the signal of the first control power supply end VGH to the pull-down node PD under the control of the active level of the control node PD_CN.

[0085] Exemplarily, the fifth transistor M5 and the ninth transistor M9 can be of the same type. For example, the fifth transistor M5 and the ninth transistor M9 can both be NMOS. It should be noted that, Figure 3 Exemplarily, the circuit structure of the noise release module 15 is shown in the figure, but the noise release module 15 is not limited to the structure in the figure, and the noise release module can adopt other circuits as long as the function of the noise release module 15 can be realized.

[0086] In an embodiment, as shown in FIG. 1, the pull-down module 14 can include a sixth transistor M6 and an eighth transistor M8. Figure 3As shown, the second reset module 16 includes an eleventh transistor M11. The gate of the eleventh transistor M11 is coupled with the pull-down node PD, the first pole of the eleventh transistor M11 is coupled with the fourth power supply end VGL_2, and the second pole of the eleventh transistor M11 is coupled with the first output signal end OUTPUT_1. Thus, when the pull-down node PD is an effective level signal, the eleventh transistor M11 is controlled by the effective level signal of the pull-down node PD to provide the signal of the fourth power supply end VGL_2 to the first output signal end OUTPUT_1, so as to reset the first output signal end OUTPUT_1 and make the first output signal end OUTPUT_1 have no signal output.

[0087] In an embodiment, as shown in Figure 3 As shown, the reset control module 17 includes a tenth transistor M10. The gate of the tenth transistor M10 is coupled with the pull-down node PD, the first pole of the tenth transistor M10 is coupled with the fourth power supply end VGL_2, and the second pole of the tenth transistor M10 is coupled with the pull-up node PU. Thus, when the pull-down node PD is an effective level signal, the tenth transistor M10 is controlled by the effective level signal of the pull-down node PD to provide the signal of the fourth power supply end VGL_2 to the pull-up node PU, so as to make the pull-up node PU maintain a reset state.

[0088] In an embodiment, as shown in Figure 3 As shown, the frame reset module 18 includes a seventh transistor M7. The gate of the seventh transistor M7 is coupled with the fourth power supply end VGL_2, the first pole of the seventh transistor M7 is coupled with the fourth power supply end VGL_2, and the second pole of the seventh transistor M7 is coupled with the first output signal end OUTPUT_1. When the fourth power supply end VGL_2 is an effective level signal, the seventh transistor M7 is turned on to provide the signal of the fourth power supply end VGL_2 to the first output signal end OUTPUT_1. In the display stage of a frame of image, the fourth power supply end VGL_2 provides an ineffective level signal, and in the blank stage between two adjacent frames of image, the second control power supply end provides an effective level signal. For example, in the display stage of the Nth frame of image, the second control power supply end provides an ineffective level signal, and the seventh transistor M7 is turned off. After the Nth frame of image and before the N+1th frame of image, the second control power supply end provides an effective level signal, the seventh transistor M7 is turned on to provide the signal of the fourth power supply end VGL_2 to the first output signal end OUTPUT_1, so as to reset, that is, to realize frame reset, and avoid affecting the next frame of image.

[0089] Figure 3The circuit structure of the pull-up module 11, the output module 12, the first reset module 13, the pull-down module 14, the noise elimination module 15, the second reset module 16, the reset control module 17 and the frame reset module 18 is exemplarily shown in the figure, and it can be understood that the pull-up module 11, the output module 12, the first reset module 13, the pull-down module 14, the noise elimination module 15, the second reset module 16, the reset control module 17 and the frame reset module 18 are not limited to Figure 3 The circuit structure shown in the figure can be replaced by other circuit structures as long as the functions thereof can be realized.

[0090] Exemplarily, Figure 4 The transistors in the scan driving circuit shown in the figure are all NMOS transistors. In the case that the transistors in the scan driving circuit are all NMOS transistors, the active level signals of the transistors are high level signals.

[0091] It should be noted that the types of the transistors in the scan driving circuit in the embodiments of the present disclosure are not limited in actual use. The transistors can be set as NMOS transistors or PMOS transistors according to the needs, and the signals of the input signal end INPUT, the first power supply end VGL_1, the second power supply end VDD, the third power supply end and the second control power supply end are set correspondingly. In the case that the transistors in the scan driving circuit are PMOS transistors, the active level signals of the transistors are low level signals.

[0092] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display panel, comprising a gate signal generation module, comprising a plurality of cascaded gate driving circuits, and the gate driving circuit is the scan driving circuit of any of the embodiments of the present disclosure.

[0093] Exemplarily, the display panel comprises a display area and a frame area, and the gate driving circuit is located in the frame area.

[0094] Figure 4 The schematic diagram of the gate signal generation module of the embodiments of the present disclosure is shown in the figure. As Figure 6As shown, the gate signal generation module includes n cascaded gate drive circuits. The input signal end INPUT of the first stage gate drive circuit is coupled with the control signal end STV, the input signal end INPUT of the i-th stage gate drive circuit is coupled with the first output signal end OUTPUT_1 of the (i-1)-th stage gate drive circuit, and the reset signal end RST of the i-th stage gate drive circuit is coupled with the first output signal end OUTPUT_1 of the (i+1)-th stage. In this way, different gate drive circuits output driving signals according to the display of the display area, so as to realize the distribution of frequency according to different lines in a frame. For example, the second output signal end OUTPUT_2 of the first stage gate drive circuit to the m-th stage gate drive circuit outputs the signal after the first power end is pulled down, and the second output signal end OUTPUT_2 of the (m+1)-th stage gate drive circuit to the n-th stage gate drive circuit normally outputs the signal of the first output signal end OUTPUT_1.

[0095] The display panel of the embodiment of the present disclosure can realize that, in a frame, when the display area of the display panel is a static picture or a slow dynamic picture, the signal of the first power end VGL_1 is provided to the second output signal end OUTPUT_2 to pull down the potential of the second output signal end OUTPUT_2, and when the display area of the display panel is a dynamic picture, the signal of the first output signal end OUTPUT_1 is normally provided to the second output signal end OUTPUT_2, so as to reduce power consumption and improve product competitiveness.

[0096] Exemplarily, the display panel can be an organic light-emitting diode display panel (OLED), or the display panel can also be a liquid crystal display panel (LCD).

[0097] In an embodiment, the display panel 100 includes a first display area 110 and a second display area 120. The first display area 110 includes N gate lines, and the N gate lines are connected with N gate drive circuits correspondingly. The second display area 120 includes M gate lines, and the M gate lines are connected with M gate drive circuits correspondingly. M and N are positive integers greater than 0. The voltage value of the signal of the gate drive circuit corresponding to the first display area 110 is a first voltage, the voltage value of the signal of the gate drive circuit corresponding to the second display area 120 is a second voltage, the first voltage is less than the second voltage, the signal of the gate area circuit corresponding to the second display area is the signal of the first output signal end OUTPUT_1, and the signal of the gate drive circuit corresponding to the first display area 110 is the voltage after the first power end VGL_1_1 is pulled down.

[0098] Figure 6 A schematic diagram of the display area of the display panel of the embodiment of the present disclosure is shown. In an embodiment, as shown in FIG. 1, the display panel includes a first display area 110 and a second display area 120. The first display area 110 includes N gate lines, and the N gate lines are connected with N gate drive circuits correspondingly. The second display area 120 includes M gate lines, and the M gate lines are connected with M gate drive circuits correspondingly. M and N are positive integers greater than 0. The voltage value of the signal of the gate drive circuit corresponding to the first display area 110 is a first voltage, the voltage value of the signal of the gate drive circuit corresponding to the second display area 120 is a second voltage, the first voltage is less than the second voltage, the signal of the gate area circuit corresponding to the second display area is the signal of the first output signal end OUTPUT_1, and the signal of the gate drive circuit corresponding to the first display area 110 is the voltage after the first power end VGL_1_1 is pulled down. Figure 7As shown, the display panel includes a second display area 120 (dynamic display area B) and two first display areas 110 (static display area A and static display area C) on both sides. The first display area 110 keeps the picture unchanged as a static display area, and the second display area 120 refreshes the picture in real time as a dynamic display area. For example, when playing a video or playing a game, a frame of picture can include a middle dynamic picture and upper and lower black frames or normal display static picture on both sides of the middle dynamic picture. The middle dynamic picture is the second display area, and the upper and lower black frames are static display areas. The embodiment of the present disclosure only needs to keep the picture for the static display area, and the pixel can enter the keep state, so that the power consumption of the static display area can be reduced.

[0099] It should be noted that the range of the first display area 110 and the range of the second display area 120 can be adjusted. The first display area 110 and the second display area 120 can adjust the number of corresponding gate lines according to the demand and the display picture, so as to adjust the start row and the end row of the frequency division area. The first display area 110 can be one or more, and the second display area 120 can be one or more. The number of the first display area and the second display area can be equal or unequal.

[0100] In an embodiment, the display panel 100 further includes a data chip. The data chip transmits a data signal DATA to the corresponding row of the second display area 120, and stops transmitting the data signal to the corresponding row of the first display area 110. The data chip can transmit the data signal to the corresponding row of the second display area or stop transmitting the signal to the corresponding row of the first display area 110, so as to further reduce the power consumption.

[0101] Figure 7 The signal timing diagram of the embodiment of the present disclosure is shown. As shown in FIG. 2, the display panel 100 includes a first display area 110 and a second display area 120. The first display area 110 is a static display area, and the second display area 120 is a dynamic display area. Figure 5As shown, in the static display area A and the static display area C, the trigger signal end Vf provides a high level signal, the second control transistor M13 is turned on, the first power supply end VGL_1 provides a second signal, the second signal is a low level signal, the first signal of the first output signal end OUTPUT_1 is pulled low, the second output signal end OUTPUT_2 is pulled low, so that the transistors of the static display area A and the static display area C are turned off, the pixels of the static display area A and the static display area C enter a holding state, the data chip synchronously stops transmitting data signals to the static display area A and the static display area C, the static display area A and the static display area C no longer refresh the picture and enter a holding low frequency state. In the dynamic display area B, the trigger signal end B provides a low level signal, the second control transistor M13 is turned off, the first power supply end VGL_1 does not provide the second signal to the second output signal end OUTPUT_2, the first output signal end OUTPUT_1 normally provides a pulse signal, and the second output signal end OUTPUT_2 outputs the normal signal of the first output signal end OUTPUT_1, the data chip outputs the data signal corresponding to the picture, and the pixel enters a normal refreshable state.

[0102] In the normal display process of the display panel, the trigger signal end Vf provides a low level signal, the second control transistor M13 is turned off, the second output signal end OUTPUT_2 of each gate drive circuit normally outputs the signal of the first output signal end OUTPUT_1, ​ The gate drive circuit shown outputs the gate drive signal row by row. When the first stage gate drive circuit to the mth stage gate drive circuit of the display panel does not need to be refreshed, the trigger signal end Vf provides a high level signal, the second control transistor M13 is turned on, the second output signal end OUTPUT_2 of the corresponding row of the gate drive circuit outputs the signal pulled low by the first power supply end, the m+1th stage gate drive circuit to the nth stage gate drive circuit of the display panel is normally refreshed, the trigger signal end Vf provides a low level signal, the second control transistor is turned off, and the second output signal end normally outputs the signal of the first output signal end OUTPUT_1, so that the static display area and the dynamic display area can be controlled by frequency and row division, and the power consumption is reduced.

[0103] The data chip controls the data signal output of the first stage gate drive circuit to the mth stage gate drive circuit of the display panel corresponding to the row, and the data chip controls the normal output of the data signal of the m+1th stage gate drive circuit to the nth stage gate drive circuit of the display panel corresponding to the row, so as to further reduce the power consumption.

[0104] As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a driving method of a display panel, applied to the display panel of any one of the embodiments of the present disclosure, and the method comprises:

[0105] The first output signal end OUTPUT_1 provides the first signal to the second output signal end OUTPUT_2, the trigger signal end Vf provides the trigger signal, the first power supply end VGL_1 provides the second signal to the second output signal end OUTPUT_2, and the second signal pulls down the first signal.

[0106] The driving method of the embodiment of the present disclosure can control the first power supply end to provide the second signal to the second output signal end OUTPUT_2 through the trigger signal end to pull down the signal level of the second output signal end OUTPUT_2, so that the signal of the second output signal end OUTPUT_2 in a frame can be adjusted according to the static display area and the dynamic display area, and the power consumption is reduced.

[0107] In an embodiment, the method further comprises:

[0108] The trigger signal end Vf of the gate drive circuit corresponding to the first display area provides the first trigger signal, controls the first power supply end VGL_1 to provide the second signal to the second output signal end OUTPUT_2, the second signal pulls down the first signal, and the output signal of the second output signal end OUTPUT_2 is pulled down.

[0109] The trigger signal end Vf of the gate drive circuit corresponding to the second display area provides the second trigger signal, the second trigger signal controls the first power supply end VGL_1 not to provide the second signal to the second output signal end OUTPUT_2, so that the first output signal end OUTPUT_1 normally provides the signal to the second output signal end OUTPUT_2.

[0110] Exemplarily, the first trigger signal is a high-level signal, the second trigger signal is a low-level signal, and the first power supply end VGL_1 is a low-level signal. The first trigger signal controls the first power supply end to provide the low-level signal to the second output signal end OUTPUT_2 to pull down the level of the second output signal end OUTPUT_2, realizes the frequency division display of the static display area and the dynamic display area in a frame, and reduces the power consumption.

[0111] In an embodiment, the method further comprises:

[0112] The data chip controls the data signal to be transmitted to the corresponding row of the second display area, and controls the data signal to stop being transmitted to the corresponding row of the first display area.

[0113] The data chip can control the data signal to be transmitted to the corresponding row or stop the transmission of the data signal according to the positions of the first display area and the second display area, so as to further reduce the power consumption.

[0114] As a fourth aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device comprising the display panel of any of the embodiments of the present disclosure. The display device provided by the embodiments of the present disclosure can be any product or component with display and touch functions, such as a smart phone, a wearable smart watch, smart glasses, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a vehicle-mounted display, an electronic book, a biometric identification device such as a smart skin device, a soft robot, and a biomedical device.

[0115] The scan driving circuit, the display panel, and the other configurations of the display device of the above embodiments can adopt various technical solutions known to those skilled in the art at present and in the future, which are not described in detail here.

[0116] In the description of the present specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0117] In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise explicitly specified and limited.

[0118] In the present disclosure, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting", "fixing", and the like should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integral; can be mechanical connection, can also be electrical connection, or communication; can be direct connection, or indirect connection through an intermediate medium; can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meanings of the above terms in the present disclosure can be understood according to the specific circumstances.

[0119] In the present disclosure, unless specifically defined otherwise, "on" or "under" of a first feature with respect to a second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Also, "on", "over", and "above" of a first feature with respect to a second feature include that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is horizontally higher than the second feature. "Under", "below", and "underneath" of a first feature with respect to a second feature include that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is horizontally lower than the second feature.

[0120] The above disclosure provides many different embodiments or examples for implementing different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure can repeatedly refer to numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0121] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of various changes or replacements within the technical scope disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A scan driving circuit, characterized in that: include a driving signal generating module, coupled to the input signal terminal, the clock signal terminal and the first output signal terminal respectively, wherein the driving signal generating module is configured to provide the signal of the clock signal terminal to the first output signal terminal under the control of the input signal terminal; as well as a signal output control module, coupled to the trigger signal terminal, the first power terminal, the first output signal terminal, and the second output signal terminal, respectively; the first output signal terminal provides a first signal to the second output signal terminal; and the signal output control module is configured such that, under the control of the trigger signal terminal, the first power terminal provides a second signal to the second output signal terminal to pull down the first signal; The signal output control module includes a first control transistor and a second control transistor, the gate of the first control transistor is coupled to the first output signal terminal, the first electrode of the first control transistor is coupled to the first output signal terminal, the second electrode of the second control transistor is coupled to the first power supply terminal, the gate of the second control transistor is coupled to the trigger signal terminal, the second output signal terminal is coupled to the second electrode of the first control transistor, and the second output signal terminal is coupled to the first electrode of the second control transistor.

2. The scanning driving circuit according to claim 1, wherein: The second signal is a constant voltage signal, and the first signal is a pulse signal.

3. The scanning driving circuit according to claim 1, wherein: The driving signal generating module includes a pull-up module, an output module, a first reset module, a pull-down module, a noise reduction module, a second reset module, a reset control module and a third reset module; The pull-up module is coupled to the input signal terminal, the second power terminal and the pull-up node respectively, and is configured to provide the signal of the second power terminal to the pull-up node under the control of the input signal terminal; The output module is coupled to the clock signal terminal, the pull-up node and the first output signal terminal respectively, and is configured to provide the signal of the clock signal terminal to the first output signal terminal under the control of the pull-up node; The first reset module is coupled to the reset signal terminal, the third power terminal and the pull-up node respectively, and is configured to provide the signal of the third power terminal to the pull-up node under the control of the reset signal terminal. The pull-down module is coupled to the fourth power terminal, the pull-up node and the control node respectively, and is configured to provide the signal of the fourth power terminal to the pull-down node and the control node under the control of the pull-up node; a noise reduction module, coupled to the first control power supply terminal, the control node, and the pull-down node, respectively, and configured to provide a signal of the first control power supply terminal to the control node under the control of the first control power supply terminal, and to provide a signal of the first control power supply terminal to the pull-down node under the control of the control node; a second reset module, coupled to the pull-down node, the fourth power supply terminal, and the first output signal terminal, respectively, and configured to provide a signal from the fourth power supply terminal to the first output signal terminal under the control of the pull-down node; a reset control module, coupled to the pull-down node, the fourth power supply terminal, and the pull-up node, respectively, and configured to provide a signal from the fourth power supply terminal to the pull-up node under the control of the pull-down node; The frame reset module is coupled to the fourth power supply terminal, the first output signal terminal, and the second control power supply terminal respectively, and is configured to provide the signal of the fourth power supply terminal to the first output signal terminal under the control of the second control power supply terminal.

4. The scanning driving circuit according to claim 3, wherein: Include at least one of the following: The pull-up module includes a first transistor, a gate of the first transistor is coupled to the input signal terminal, a first electrode of the first transistor is coupled to the second power supply terminal, and a second electrode of the first transistor is coupled to the pull-up node; The output module includes a third transistor and a storage capacitor, the gate of the third transistor is coupled to the pull-up node, the first electrode of the third transistor is coupled to the clock signal terminal, the second electrode of the third transistor is coupled to the first output signal terminal, the first plate of the storage capacitor is coupled to the pull-up node, and the second plate of the storage capacitor is coupled to the first output signal terminal; The first reset module includes a second transistor, a gate of the second transistor is coupled to the reset signal terminal, a first electrode of the second transistor is coupled to the third power supply terminal, and a second electrode of the second transistor is coupled to the pull-up node; The pull-down module includes a sixth transistor and an eighth transistor, wherein a gate of the sixth transistor is coupled to the pull-up node, a first electrode of the sixth transistor is coupled to the pull-down node, a second electrode of the sixth transistor is coupled to the fourth power supply terminal, a gate of the eighth transistor is coupled to the pull-up node, a first electrode of the eighth transistor is coupled to the control node, and a second electrode of the eighth transistor is coupled to the fourth power supply terminal; The noise reduction module includes a fifth transistor and a ninth transistor, wherein the gate of the ninth transistor is coupled to the first control power supply terminal, the first electrode of each of the ninth transistors is coupled to the first control power supply terminal, the second electrode of the ninth transistor is coupled to the control node, the gate of the fifth transistor is coupled to the control node, the first electrode of the fifth transistor is coupled to the first control power supply terminal, and the second electrode of the fifth transistor is coupled to the pull-down node; The second reset module includes an eleventh transistor, a gate of the eleventh transistor is coupled to the pull-down node, a first electrode of the eleventh transistor is coupled to the fourth power supply terminal, and a second electrode of the eleventh transistor is coupled to the first output signal terminal; The reset control module includes a tenth transistor, a gate of the tenth transistor is coupled to the pull-down node, a first electrode of the tenth transistor is coupled to the fourth power supply terminal, and a second electrode of the tenth transistor is coupled to the pull-up node; The frame reset module includes a seventh transistor, a gate of the seventh transistor is coupled to the second control power supply terminal, a first electrode of the seventh transistor is coupled to the fourth power supply terminal, and a second electrode of the seventh transistor is coupled to the first output signal terminal.

5. A display panel, characterized in that: include: The gate signal generating module includes a plurality of cascaded gate driving circuits, wherein the gate driving circuit is the scanning driving circuit according to any one of claims 1 to 4.

6. The display panel according to claim 5, wherein: The display panel includes a first display area and a second display area, the first display area includes N gate lines, and the N gate lines are correspondingly connected to N gate drive circuits, the second display area includes M gate lines, and the M gate lines are correspondingly connected to M gate drive circuits, M and N are positive integers greater than 0, the voltage value of the signal of the gate drive circuit corresponding to the first display area is a first voltage, the voltage value of the signal of the gate drive circuit corresponding to the second display area is a second voltage, and the first voltage is less than the second voltage.

7. The display panel according to claim 6, wherein: The display panel further includes a data chip. When the data chip is turned on, it transmits data signals to the corresponding rows of the second display area. When the data chip is turned off, it transmits data signals to the corresponding rows of the first display area.

8. A method for driving a display panel, applied to the display panel according to any one of claims 5 to 7, characterized in that: The method comprises: The first output signal terminal provides a first signal to the second output signal terminal; The trigger signal terminal provides a trigger signal to control the first power supply terminal to provide a second signal to the second output signal terminal to pull down the first signal.

9. The method for driving a display panel according to claim 8, wherein: The method further comprises: The trigger signal terminal of the gate driving circuit corresponding to the first display area provides a first trigger signal, and controls the first power supply terminal to provide a second signal to the second output signal terminal to pull down the first signal; The trigger signal terminal of the gate driving circuit corresponding to the second display area provides a second trigger signal, and the first power supply terminal is closed to provide a second signal to the second output signal terminal.

10. The method for driving a display panel according to claim 9, wherein: The method further comprises: The data chip controls the data signal to be transmitted to the corresponding row of the second display area, and the data chip controls the data signal to stop being transmitted to the corresponding row of the first display area.

11. A display device, characterized in that: Comprising the display panel according to any one of claims 5 to 7.

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