Display panel and display device

Abstract

The invention provides a display panel and a display device, and relates to the technical field of display, a pixel driving circuit comprises a driving transistor, a first reset module and a data writing module, a grid electrode of the driving transistor is connected with a first node, a first pole is connected with a second node, and a second pole is connected with a third node; two ends of the first reset module are respectively connected with a first reset signal line and a first node, and a control end is connected with a first scanning line; two ends of the data write-in module are respectively connected with a data signal line and a second node, and a control end is connected with a second scanning line; the display area comprises a first display area and a second display area which are arranged in the first direction, and the first display area is located between the second display area and the binding area; in each pixel driving circuit, a first capacitor is formed between the first node and the second scanning line; the capacitance value of the first capacitor in the pixel driving circuit corresponding to the first display area is smaller than the capacitance value of the first capacitor in the pixel driving circuit corresponding to the second display area, so that the display uniformity is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable tool for people today.

[0003] At present, how to improve the uniformity of display brightness of display products to improve display effects has become one of the technical problems that need to be solved urgently. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a display device.

[0005] In a first aspect, the present disclosure provides a display panel, comprising a display area and a binding area located at one side of the display area along a first direction, wherein the display area comprises a plurality of light-emitting elements and a pixel driving circuit connected to the light-emitting elements;

[0006] The pixel driving circuit comprises a driving transistor, a first reset module and a data writing module, wherein the gate of the driving transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the third node; the two ends of the first reset module are respectively connected to the first reset signal line and the first node, and the control end is connected to the first scan line; the two ends of the data writing module are respectively connected to the data signal line and the second node, and the control end is connected to the second scan line; the third node is used to be electrically connected to the light emitting element;

[0007] The display area includes a first display area and a second display area arranged along the first direction, and the first display area is located between the second display area and the binding area; in each of the pixel driving circuits, a first capacitor is formed between the first node and the second scanning line; the capacitance of the first capacitor in the pixel driving circuit corresponding to the first display area is smaller than the capacitance of the first capacitor in the pixel driving circuit corresponding to the second display area.

[0008] In a second aspect, the present disclosure provides another display panel, comprising a display area and a binding area located on one side of the display area along a first direction, wherein the display area comprises a plurality of light-emitting elements and a pixel driving circuit connected to the light-emitting elements; the pixel driving circuit comprises a driving transistor, a first reset module and a data writing module, wherein a gate of the driving transistor is connected to a first node, a first electrode is connected to a second node, and a second electrode is connected to a third node; two ends of the first reset module are respectively connected to a first reset signal line and the first node, and a control end is connected to a first scan line; two ends of the data writing module are respectively connected to a data signal line and the second node, and a control end is connected to a second scan line; the third node is used to be electrically connected to the light-emitting element;

[0009] The display area includes a first display area and a second display area arranged along the first direction, and the first display area is located between the second display area and the binding area; in the pixel driving circuit of the first display area, a shielding part is arranged on the side of the first node toward the second scanning line along a direction parallel to the light emitting surface of the display panel, and the shielding part receives a fixed potential signal.

[0010] In a third aspect, the present disclosure provides a display device, comprising the display panel described in any one of the first aspect and the second aspect of the present disclosure.

[0011] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0012] In the display panel and display device provided by the present disclosure, in each pixel driving circuit, a first capacitor is formed between the first node and the second scanning line. Since the first node and the second scanning line are adjacent, the first capacitor can be regarded as a coupling capacitor between the two. The above-mentioned first capacitors of the first display area and the second display area are designed differently, so that the capacitance of the first capacitor in the pixel driving circuit corresponding to the first display area is less than the capacitance of the first capacitor in the pixel driving circuit corresponding to the second display area. In this way, it is equivalent to reducing the coupling capacitance between the second scanning line and the first node in the first display area, so that the coupling effect of the signal jump on the second scanning line in the first display area on the first node is reduced, and the situation of the dim brightness of the first display area is improved, so that the potential of the first node in the first display area after being affected by the coupling capacitor is consistent or nearly consistent, thereby reducing the problem of large difference in display brightness between the first display area and the second display area due to inconsistent potential of the first node, so it is beneficial to improve the uniformity of the overall display brightness of the display panel and improve the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0014] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0015] Figure 1 Shown is a schematic plan view of a display panel provided by an embodiment of the present disclosure;

[0016] Figure 2 Shown is a connection diagram of a pixel driving circuit and a light emitting element in a display panel;

[0017] Figure 3 Shown with Figure 2 A driving timing diagram corresponding to the pixel driving circuit in;

[0018] Figure 4 Shown is a schematic diagram of connection between a scan line and a gate drive circuit;

[0019] Figure 5 A schematic diagram of a layout of a pixel driving circuit provided in an embodiment of the present disclosure is shown;

[0020] Figure 6 The figure shows a film layer structure diagram of a display panel provided by an embodiment of the present disclosure;

[0021] Figure 7 FIG. 2 is another schematic diagram of a layout of a pixel driving circuit provided in an embodiment of the present disclosure;

[0022] Figure 8 FIG. 2 is another schematic diagram of a layout of a pixel driving circuit provided in an embodiment of the present disclosure;

[0023] Fig. 9 FIG. 2 is another schematic diagram of a layout of a pixel driving circuit provided in an embodiment of the present disclosure;

[0024] Fig.10 FIG. 2 is another schematic diagram of a layout of a pixel driving circuit provided in an embodiment of the present disclosure;

[0025] Fig.11 FIG. 2 is another schematic diagram of a layout of a pixel driving circuit provided in an embodiment of the present disclosure;

[0026] Fig.12 Another connection diagram of a pixel driving circuit and a light emitting element in a display panel is shown;

[0027] Fig.13 Shown is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0029] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0030] Figure 1 FIG. 1 is a schematic plan view of a display panel provided by an embodiment of the present disclosure. Figure 2 FIG. 1 is a schematic diagram showing a connection between a pixel driving circuit 10 and a light emitting element 30 in a display panel. Figure 3 Shown with Figure 2 A driving timing diagram corresponding to the pixel driving circuit 10, Figure 4 The figure shows a connection diagram of the scanning line and the gate driving circuit. It should be noted that the embodiment of the present disclosure is only illustrated by taking the transistors in the pixel driving circuit 10 as P-type transistors as an example. The effective level signal when the P-row transistors are turned on is a low-level signal, and the cut-off signal is a high-level signal, but the present disclosure is not limited to this. In some other embodiments of the present disclosure, the transistors in the pixel driving circuit 10 can also all be embodied as N-type transistors, or as a combination of P-type transistors and N-type transistors, and the present disclosure does not specifically limit this. The effective level signal when the N-type transistors are turned on is a high-level signal, and the cut-off signal is a low-level signal.

[0031] Please refer to Figures 1 to 4The embodiment of the present disclosure provides a display panel, including a display area A1 and a binding area A2 located at one side of the display area along a first direction D1, wherein the display area A1 includes a plurality of light emitting elements 30 and a pixel driving circuit 10 connected to the light emitting elements 30; the pixel driving circuit 10 includes a driving transistor DT, a first reset module 71 (taking the transistor T1 as an example for explanation) and a data writing module 72 (taking the transistor T5 as an example for explanation), wherein the gate of the driving transistor DT is connected to the first node N1, the first electrode is connected to the second node N2, and the second electrode is connected to the third node N3; the two ends of the first reset module 71 are respectively connected to the first reset signal line Vref1 and the first node N1, and the control end is connected to the first scan line S1; the two ends of the data writing module 72 are respectively connected to the data signal line DL and the second node N2, and the control end is connected to the second scan line S2; the third node N3 is used to be electrically connected to the light emitting element 30. The display area A1 of the display panel includes a first display area A11 and a second display area A12 arranged along the first direction D1, and the first display area A11 is located between the second display area A12 and the binding area A2.

[0032] Optionally, the pixel driving circuit 10 further includes a first light emitting control module 73 (using a transistor T3 as an example for explanation) and a second light emitting control module 74 (using a transistor T4 as an example for explanation), the first light emitting control module 73 is connected between the first power signal terminal PVDD and the second node N2, the second light emitting control module 74 is connected between the third node N3 and the light emitting element 30, and the control ends of the first light emitting control module 73 and the second light emitting control module 74 are connected to the light emitting control signal line EM. Optionally, the pixel driving circuit 10 further includes a threshold compensation module 75 (using a transistor T6 as an example for explanation), the threshold compensation module 75 is connected between the first node N1 and the third node N3, and the control end of the threshold compensation module 75 is connected to the second scan line S2.

[0033] The working process of the pixel driving circuit 10 includes:

[0034] First reset stage: the first scan line S1 provides a valid level signal to the first reset module 71, the first reset module 71 is turned on, and the reset signal on the first reset signal line Vref1 is transmitted to the first node N1 to reset the first node N1.

[0035] Data writing and threshold compensation stage: the second scan line S2 provides a valid level signal to the data writing module 72 and the threshold compensation module 75, the data writing module 72 and the threshold compensation module 75 are turned on, the data signal on the data signal line DL is transmitted to the second node N2, and the gate of the driving transistor DT is threshold compensated through the threshold compensation module 75.

[0036] Light-emitting stage: the light-emitting control signal line EM sends a valid level signal to the first light-emitting control module 73 and the second light-emitting control module 74 to control the first light-emitting control module 73 and the second light-emitting control module 74 to be turned on, and the signal of the first power signal terminal PVDD is transmitted to the driving transistor DT to form a current that drives the light-emitting element 30 to emit light.

[0037] In the above pixel driving circuit 10, the stability of the potential of the gate of the driving transistor DT (corresponding to the first node N1 in the figure) directly affects the magnitude of the driving current formed in the light emitting stage. Figure 3 In the driving timing shown, after the data writing is completed, the potential on the second scan line S2 jumps from a low level to a high level. If the second scan line S2 is close to the first node N1, the change of the signal on the second scan line S2 will be coupled to the first node N1, causing the potential of the first node N1 to change, affecting the magnitude of the driving current. If the number of pixel driving circuits 10 connected to each second scan line S2 in the display panel is consistent, the load of the second scan line S2 is consistent or nearly consistent, and the coupling effect of the second scan line S2 on the first node N1 will also be consistent. At this time, the overall display brightness of the display panel will also be consistent.

[0038] However, for Figure 4 In the structure shown, the load of the second scan line S2 is not uniform. Figure 4 In an optional embodiment of the present disclosure, the display panel includes M pixel driving circuit rows H; the display panel includes N cascaded gate driving circuits (respectively Scan1~Scan(n)), N=M+s; the first scanning line S1 corresponding to the pixel driving circuit 10 located in the mth row is electrically connected to the gate driving circuit of the mth level, and the second scanning line S2 corresponding to the pixel driving circuit 10 located in the mth row is electrically connected to the gate driving circuit of the m+sth level; wherein, 1≤m≤M, s≥2, and this embodiment is described by taking s=7 as an example, but is not limited thereto. The row of pixel driving circuits 10 connected to the gate driving circuits of the M+1th to M+sth levels (corresponding to Scan(n-13) to Scan(n-7) in the figure) is located in the first display area A11. Figure 4Taking the structure shown as an example, the first scan line S1 corresponding to the pixel driving circuit 10 of the first row is connected to the gate driving circuit Scan1 of the first level, and the second scan line S2 corresponding to the pixel driving circuit 10 of the first row is connected to the gate driving circuit Scan8 of the eighth level. That is to say, after resetting the first node N1 of the pixel driving circuit 10 of the first row, data is written again after an interval of 8 scan lines, which is beneficial to increase the time for resetting the first node N1 and restore the potential of the first node N1 to the initial state. For the pixel driving circuit 10 of the second row, the first scan line S1 is connected to the gate driving circuit Scan2 of the second level, and the second scan line S2 is connected to the gate driving circuit Scan9 of the ninth level, and so on. In this way, when there are M rows of pixel driving circuits 10 in the display panel, it will be necessary to design M+7 levels of gate driving circuits in the display panel. The first M levels of gate driving circuits (Scan1 to Scan(n-12)) will be connected to two rows of pixel driving circuits 10, and for the last 7 levels of gate driving circuits (Scan(n-13) to Scan(n-7)), each gate driving circuit will only be connected to 1 row of pixel driving circuits, and provide control signals to the second scan lines S2 corresponding to 1 row of pixel driving circuits. The 7 rows of pixel driving circuits connected to the last 7 levels of gate driving circuits are located in the first display area A11. In this way, the second scan lines S2 in the first display area A11 are electrically connected to only one row of pixel driving circuits 10, and the second scan lines S2 in the second display area A12 are electrically connected to two rows of pixel driving circuits 10. That is to say, the loads of the second scan lines S2 in the first display area A11 and the second display area A12 are different. When data writing is completed and the signal on the second scan line S2 jumps to a high level, due to the different loads, the load of the second scan line S2 in the first display area A11 is smaller, and the coupling effect of the signal jump of the second scan line S2 in the first display area A11 and the second display area A12 on the first node N1 will be different. After being coupled by the signal on the second scan line S2, the pull-up amplitude of the first node N1 in the first display area A11 will be larger, so that the potentials of the first nodes N1 in the first display area A11 and the second display area A12 after being coupled are different, resulting in different display brightness of the first display area A11 and the second display area A12, and the problem that the brightness of the first display area A11 is darker than that of the second display area A12 will occur.

[0039] To solve the above technical problems, the present disclosure provides two improved solutions:

[0040] The first improvement scheme is: in each pixel driving circuit 10, a first capacitor is formed between the first node N1 and the second scanning line S2. Since the first node N1 and the second scanning line S2 are adjacent, the first capacitor can be regarded as a coupling capacitor between the two. The first improvement scheme provided by this embodiment is essentially to differentiate the first capacitors of the first display area A11 and the second display area A12, so that the capacitance of the first capacitor in the pixel driving circuit 10 corresponding to the first display area A11 is smaller than the capacitance of the first capacitor in the pixel driving circuit 10 corresponding to the second display area A12. In this way, the coupling capacitance between the second scan line S2 and the first node N1 in the first display area A11 is reduced, so that the coupling effect of the signal jump on the second scan line S2 in the first display area A11 on the first node N1 is reduced, and the dark brightness of the first display area A11 is improved, so that the potential of the first node N1 in the first display area A11 is consistent or nearly consistent after being affected by the coupling capacitance, thereby reducing the problem of large difference in display brightness between the first display area A11 and the second display area A12 due to inconsistent potential of the first node N1, so it is beneficial to improve the overall display brightness uniformity of the display panel and improve the display effect.

[0041] On the basis of the first solution, in order to realize the differentiated design of the first capacitor corresponding to the first display area A11 and the second display area A12, please refer to Figure 5 , Figure 5 A schematic diagram of a layout of a pixel driving circuit 10 provided in an embodiment of the present disclosure is shown. Figure 6 The figure shows a film layer structure diagram of the display panel provided by the embodiment of the present disclosure. Optionally, in the pixel driving circuit 10 of the first display area A11, a shielding part 90 is provided on the side of the first node N1 toward the second scan line S2 in a direction parallel to the light emitting surface of the display panel, and the shielding part 90 receives a fixed potential signal. In this embodiment, the shielding part 90 for receiving the fixed potential signal is introduced in the area between the first node N1 and the second scan line S2. When the signal on the second scan line S2 jumps, due to the existence of the shielding part 90, the shielding part 90 will be able to reduce the influence of the above-mentioned jump signal on the first node N1, thereby reducing the coupling capacitance between the second scan line S2 and the first node N1 in the first display area A11, so as to achieve that the capacitance of the first capacitor in the pixel driving circuit 10 corresponding to the first display area A11 is smaller than the capacitance of the first capacitor in the pixel driving circuit 10 corresponding to the second display area A12, so as to reduce the display brightness difference between the first display area A11 and the second display area A12.

[0042] The second solution is: in the pixel driving circuit 10 of the first display area A11, a shielding part 90 is provided on the side of the first node N1 toward the second scan line S2 in a direction parallel to the light emitting surface of the display panel, and the shielding part 90 receives a fixed potential signal. Figure 5 and Figure 6 , and combined with Figures 1 to 4 In this embodiment, a shielding portion 90 for receiving a fixed potential signal is introduced in the region between the first node N1 and the second scan line S2. When the signal on the second scan line S2 jumps, due to the existence of the shielding portion 90, the shielding portion 90 can reduce the influence of the above-mentioned jumping signal on the first node N1 in the first display area A11, thereby reducing the coupling capacitance between the second scan line S2 in the first display area A11 and the first node N1, which is conducive to improving the problem that the second scan line S2 in the first display area A11 has a smaller load after the data is written. , the coupling influence on the first node N1 when the signal jumps, which is beneficial to balancing the difference in the influence of the second scan line S2 on the first node N1 in the first display area A11 and the second display area A12, and is beneficial to balancing the potential of the first node N1 after the signal of the second scan line S2 affects the first node N1 after the data writing is completed. When the potential of the first node N1 is close in the light-emitting stage, the driving current provided to the light-emitting element 30 will also be close, so it is beneficial to improve the display brightness uniformity of the first display area A11 and the second display area A12, and is beneficial to improve the overall display effect of the display panel.

[0043] The first and second schemes mentioned above will be further explained as follows. It should be noted that the following embodiments are applicable to both the first and second schemes mentioned above, and can be regarded as a further expansion of the first scheme mentioned above, or as a further expansion of the second scheme mentioned above, and the similarities will not be described separately.

[0044] Please refer to Figure 6 , Figure 6The film structure of the display panel is schematically illustrated. Optionally, the display panel provided in the embodiment of the present disclosure includes a substrate 00, a driving layer 40, and a display layer 10, wherein the display layer 10 includes a pixel definition layer 19, and the pixel definition layer 19 defines a plurality of pixel openings; the light-emitting material layer 302 is at least located in the pixel opening, and along the direction perpendicular to the substrate 00, the anode 301 and the cathode 303 are respectively located on both sides of the light-emitting material layer 302, and the anode 301 is located on the side of the cathode 303 facing the substrate 00. Optionally, an encapsulation layer 50 is further provided on the side of the cathode 303 away from the anode 301, and optionally, the encapsulation layer 50 includes a first inorganic layer 51, an organic layer 52, and a second organic layer 53 that are stacked. The pixel driving circuit mentioned in the above embodiment is located in the driving layer 40, and the pixel driving circuit includes a plurality of transistors T. Optionally, in the driving layer 40, the gate of the transistor is provided in the first metal layer M1, and the source and drain of the transistor are provided in the second metal layer M2. The array substrate 10 also includes a semiconductor layer poly disposed on the side of the first metal layer M1 facing the substrate 00 and an auxiliary metal layer M0 disposed on the side of the semiconductor layer poly facing the substrate 00. It should be noted that the display panel may include a transistor with a dual-gate structure. In this case, one of the gates of the transistor may be located in the first metal layer M1, and the other gate may be located in the auxiliary metal layer M0. In a direction perpendicular to the plane where the substrate 00 is located, the first metal layer M1 and the auxiliary metal layer M0 both overlap with the semiconductor layer poly. The auxiliary metal layer M0 also has a light shielding function to prevent light from affecting the semiconductor layer poly. Optionally, a capacitor metal layer Mc is further included between the first metal layer M1 and the second metal layer M2. The capacitor metal layer Mc can form a capacitor structure with the second metal layer M2. Optionally, a third metal layer M3 is also included on the side of the second metal layer M2 facing away from the substrate 00. Another metal layer may be provided on the side of the third metal layer m3 facing away from the substrate according to actual needs. The present disclosure does not specifically limit this. Each metal layer may be used for the layout of signal lines. Optionally, please combine Figure 5 The first scan line S1 and the second scan line S2 are located in the first metal layer M1, the first reset signal line Vref1 and the second reset signal line Vref2 are located in the capacitor metal layer Mc, the data signal line DL and the first power signal line PVDD are located in the second metal layer M2, but the embodiment of the present disclosure is not limited to this.

[0045] Please continue to refer to Figure 5 and Figure 6In an optional embodiment of the present disclosure, the gate of the driving transistor DT is electrically connected to the first node N1 through a first connecting portion L1, and the first connecting portion L1 and the second scanning line S2 are arranged in different layers. This embodiment is described by taking the first connecting portion L1 located in the third metal layer M3 and the second scanning line S2 located in the first metal layer M1 as an example, but is not limited to this. Along the second direction D2, the first connecting portion L1 overlaps with the second scanning line S2 to form a first overlapping area, and the second direction D2 is perpendicular to the plane where the light emitting surface of the display panel is located; in the first display area A11, the shielding portion 90 includes a first shielding portion 91, and along the second direction D2, the first shielding portion 91 overlaps with the first overlapping area, and at least part of the first shielding portion 91 is located between the first connecting portion L1 and the second scanning line S2. Optionally, the first shielding portion 91 is located in the capacitor metal layer Mc.

[0046] Since the first connection portion L1 is used to connect the gate of the driving transistor and the first node N1, the potential of the gate of the driving transistor DT, the potential of the first connection portion L1, and the potential of the first node N1 are equal. When the first connection portion L1 and the second scan line S2 are located in different film layers and overlap to form a first overlapping region, due to the presence of the coupling capacitor in the first overlapping region, when a signal jump occurs in the second scan line S2, the changed signal will be coupled to the first connection portion L1, affecting the potential of the first connection portion L1, and further affecting the potential of the first node N1. Therefore, when the first shielding portion 91 is introduced into the first display area A11 of the display panel and the first shielding portion 91 overlaps with the first overlapping area, the first shielding portion 91 can at least partially shield the jump signal of the second scan line S2, thereby avoiding or reducing the influence of the jump signal on the potential on the first connecting portion L1, and further avoiding or reducing the influence of the jump signal on the potential on the first node N1, that is, reducing the influence of the second scan line S2 in the first display area A11 on the potential of the first node N1, reducing the difference in influence of the second scan line S2 on the first node N1 in the first display area A11 and the second display area A12, so that the potential difference of the first node N1 in the first display area A11 and the second display area A12 during the light-emitting stage can be reduced, which is beneficial to reducing the display brightness difference between the first display area A11 and the second display area A12, and is beneficial to improving the display brightness uniformity of the first display area A11 and the second display area A12.

[0047] Figure 7 FIG. 1 is another schematic diagram of the layout of the pixel driving circuit 10 provided in the embodiment of the present disclosure. Figure 7In an optional embodiment of the present disclosure, the second scan line S2 includes a main body 81, the main body 81 extends along a third direction D3, and the main body 81 and the first node N1 are arranged along the first direction D1, the third direction D3 intersects with the first direction D1 and is parallel to the plane where the light emitting surface of the display panel is located; in the first display area A11, the shielding portion 90 includes a second shielding portion 92, and along the first direction D1, the second shielding portion 92 is located between the first node N1 and the main body 81 of the second scan line S2.

[0048] This embodiment shows another setting method of the shielding portion 90 in the first display area A11. When the main portion 81 of the second scan line S2 and the first node N1 are arranged along the first direction D1, it is equivalent to that the first node N1 is located on one side of the main portion 81 of the second scan line S2 along the first direction D1. At this time, there will be a lateral coupling capacitor between the main portion 81 of the second scan line S2 and the first node N1. When the signal on the second scan line S2 jumps after the data writing stage, the potential of the first node N1 will change accordingly due to the influence of the lateral coupling capacitor. When the embodiment of the present disclosure introduces the second shielding portion 92 on one side of the main portion 81 of the second scan line S2 along the first direction D1 toward the first node N1, the second shielding portion 92 is located between the first node N1 and the main portion 81. In this way, the second shielding portion 92 can be used to isolate the jump signal on the main portion 81 to a certain extent, thereby reducing the influence of the jump signal of the main portion 81 of the second scan line S2 in the first display area A11 on the potential of the first node N1, which is also beneficial to reducing the difference in the influence of the second scan line S2 on the first node N1 in the first display area A11 and the second display area A12, and is also beneficial to improving the display brightness uniformity of the first display area A11 and the second display area A12.

[0049] Figure 8 FIG. 1 is another schematic diagram of the layout of the pixel driving circuit 10 provided in the embodiment of the present disclosure. The present embodiment shows a solution in which the shielding portion 90 in the first display area A11 includes a first shielding portion 91 and a second shielding portion 92. Please refer to FIG. Figure 8 In an optional embodiment of the present disclosure, when the shielding portion 90 includes a first shielding portion 91 and a second shielding portion 92 , the first shielding portion 91 and the second shielding portion 92 are electrically connected and located on the same layer.

[0050] Specifically, in this embodiment, when the first shielding part 91 and the second shielding part 92 are arranged in the same layer and electrically connected, the first shielding part 91 and the second shielding part 92 can be manufactured in the same manufacturing process, and there is no need to introduce different manufacturing processes for the first shielding part 91 and the second shielding part 92, respectively, which is conducive to simplifying the manufacturing process of the shielding part 90, and further to simplifying the overall manufacturing process of the display panel, and improving production efficiency. In addition, when the first shielding part 91 and the second shielding part 92 are electrically connected in the same film layer, the shielding area of ​​the shielding part 90 can be increased, the shielding effect of the shielding part 90 can be improved, and the influence of the second scanning line S2 in the first display area A11 on the potential of the first node N1 can be reduced.

[0051] The above embodiment shows a scheme of introducing the shielding portion 90 between the first node N1 and the main portion 81 of the second scan line S2. In some other embodiments of the present disclosure, the shielding portion 90 may also be introduced between the first node N1 and the extension portion 82 of the second scan line S2. For example, please refer to Fig. 9 and Fig.10 , Fig. 9 and Fig.10 Shown respectively are another layout schematic diagram of the pixel driving circuit 10 provided in the embodiment of the present disclosure. This embodiment describes a scheme of introducing a third shielding portion 93 in the first display area A11. In an optional implementation of the present disclosure, the second scan line S2 includes a main body portion 81 and an extension portion 82 connected to the main body portion 81, the main body portion 81 extends along a third direction D3, the third direction D3 intersects with the first direction D1 and is parallel to the plane where the light emitting surface of the display panel is located; the extension portion 82 extends along the first direction D1 and is located on the side of the main body portion 81 facing the first node N1; the main body portion 81 and the first node N1 are arranged along the first direction D1, and the extension portion 82 and the first node N1 are arranged along the third direction D3. The shielding portion 90 includes a third shielding portion 93, please refer to Fig. 9 , along the third direction D3, the third shielding portion 93 is located between the first node N1 and the extension portion 82; at this time, the third shielding portion 93 can be embodied as a long strip structure arranged between the extension portion 82 and the first node N1 arranged along the third direction D3. By introducing this form of the third shielding portion 93, it is possible to shield the influence of at least part of the jumping signal on the extension portion 82 on the first node N1, thereby also helping to reduce the difference in the influence of the second scanning line S2 of the first display area A11 and the second display area A12 on the potential of the first node N1, and helping to improve the display brightness uniformity of the first display area A11 and the second display area A12.

[0052] Please refer to Fig.10The third shielding portion 93 includes a first sub-portion 931 and a second sub-portion 932 that are electrically connected. Along the third direction D3, the first sub-portion 931 is located between the first node N1 and the extension portion 82. Along the first direction D1, the second sub-portion 932 is located between the first node N1 and the main body portion 81. This embodiment describes another feasible structure of the third shielding portion 93. In this embodiment, the extension portion 82 and the main body portion 81 form a vertical corner structure, and the first node N1 is located on one side of the opening of the corner structure. The third shielding portion 93 can be regarded as an L-shaped structure arranged between the corner structure and the first node N1 along the shape of the corner structure, wherein the first sub-portion 931 can shield the influence of the extension portion 82 on the first node N1, and the second sub-portion 932 can shield the influence of the main body portion 81 on the first node N1. Through the combined structure of the first sub-portion 931 and the second sub-portion 932, the shielding range of the shielding portion 90 is increased, so it is more conducive to reducing the influence of the second scan line S2 in the first display area A11 on the potential of the first node N1, and is therefore more conducive to improving the display brightness difference between the first display area A11 and the second display area A12. It should be noted that Fig.10 The embodiment shows a solution of disposing the first sub-portion 931 and the second sub-portion 932 in the auxiliary metal layer M0 of the display panel, but is not limited thereto. In some other embodiments of the present disclosure, the first sub-portion 931 and the second sub-portion 932 may also be located in other metal layers.

[0053] It should be noted that the several embodiments of the first shielding portion 91, the second shielding portion 92 and the third shielding portion 93 mentioned in the aforementioned embodiments can be arbitrarily combined. For example, the first shielding portion 91 in the first display area A11 can be combined with the second shielding portion 92, or with the third shielding portion 93, or a combination of the three, or the three can exist separately in an area corresponding to a pixel in the first display area A11. The present disclosure does not make specific limitations on this.

[0054] Fig.11 Another layout schematic diagram of the pixel driving circuit 10 provided in an embodiment of the present disclosure is shown. In an optional implementation manner of the present disclosure, the second scan line S2 includes a main body portion 81 and an extension portion 82 connected to the main body portion 81, the main body portion 81 extends along a third direction D3, the third direction D3 intersects with the first direction D1 and is parallel to the plane where the light emitting surface of the display panel is located; the extension portion 82 extends along the first direction D1 and is located on the side of the main body portion 81 facing the first node N1; the main body portion 81 and the first node N1 are arranged along the first direction D1, and the extension portion 82 and the first node N1 are arranged along the third direction D3; the shielding portion 90 includes a fourth shielding portion 94, and the fourth shielding portion 94 overlaps with the extension portion 82 along the second direction, and the second direction is perpendicular to the plane where the light emitting surface of the display panel is located.

[0055] This embodiment describes another feasible structure of the shielding portion 90, specifically, a fourth shielding portion 94 is introduced into the upper film layer or the lower film layer of the extension portion 82 in the second scan line S2, so that the fourth shielding portion 94 overlaps with the extension portion 82 of the second scan line S2. Since the fourth shielding portion 94 receives a fixed potential signal, when the fourth shielding portion 94 overlaps with the extension portion 82, it is also beneficial to reduce the signal influence of the second scan line S2 on the first node N1, so as to reduce the difference in the influence of the second scan line S2 on the first node N1 in the first display area A11 and the second display area A12, which is also beneficial to improve the display brightness uniformity of the first display area A11 and the second display area A12.

[0056] It should be noted that the first shielding portion 91, the second shielding portion 92, the third shielding portion 93 and the fourth shielding portion 94 in the above embodiment may exist separately in the pixel driving circuit 10 of the first display area A11, or may be combined in any two, or in any three, or all four may exist simultaneously in the same pixel driving circuit 10 of the first display area A11, and may be arranged according to actual needs, and the present disclosure does not make specific limitations on this.

[0057] Please continue to refer to Figure 2 In an optional embodiment of the present disclosure, the pixel driving circuit 10 includes a second reset module 76 (taking the transistor T2 as an example for explanation), two ends of the second reset module 76 are respectively connected to the second reset signal line Vref2 and the fourth node N4, and the fourth node N4 is connected to the anode of the light emitting element 30; please combine Fig.11 The second reset signal line Vref2 includes a main line 70 extending along a third direction D3 and a connecting line 71 extending along the first direction D1, the main line 70 and the connecting line 71 are electrically connected, and the third direction D3 intersects with the first direction D1; the display panel includes a plurality of pixel driving circuits 10 arranged along the first direction D1, and in the second reset signal lines Vref2 corresponding to two adjacent pixel driving circuits 10 along the first direction D1, the two main lines 70 are electrically connected through the connecting line 71; the fourth shielding portion 94 is electrically connected to the connecting line 71.

[0058] This embodiment shows a scheme of reusing the film layer of the connecting line 71 in the second reset signal line Vref2 as the fourth shielding part 94. Specifically, the second reset signal line Vref2 is a signal line that provides a reset signal to the second reset module 76 in the pixel driving circuit 10. When the second reset module 76 is turned on, the reset signal will be able to be transmitted to the anode of the light-emitting element 30 to reset the anode of the light-emitting element 30. Since the reset signal on the second reset signal line Vref2 is a global signal, that is, the signal for resetting the light-emitting elements 30 in different regions is the same, in the embodiment of the present disclosure, the second reset signal line Vref2 includes a main line 71 and a connecting line 71 that extend in different directions and are electrically connected, which is equivalent to setting the second reset signal line Vref2 to a mesh structure, which is conducive to reducing the overall impedance of the second reset signal line Vref2, reducing the voltage drop of the reset signal in different regions, and facilitating the uniformity of resetting the light-emitting elements 30 in different regions. When the fourth shielding portion 94 is introduced into the first display area A11, the embodiment of the present disclosure connects the fourth shielding portion 94 to the connecting line 71 in the second reset signal line Vref2, which is equivalent to extending from the connecting line 71 along the third direction D3. At this time, the fourth shielding portion 94 can be manufactured in the same manufacturing process as the connecting line 71, and there is no need to introduce another manufacturing process for the fourth shielding portion 94. The reset signal on the connecting line 71 can be reused, which is beneficial to simplify the manufacturing process of the display panel and improve production efficiency.

[0059] Please refer to Figure 2 , Figures 5 to 11 In an optional embodiment of the present disclosure, the display panel includes a fixed potential signal line (subsequent embodiments will describe the feasible fixed potential signal line), and the shielding portion 90 is electrically connected to the fixed potential signal line. When the shielding portion 90 is connected to the existing fixed potential signal line in the display panel, there is no need to introduce a new signal line for the shielding portion 90 to provide a fixed potential signal to the shielding portion 90. The method of providing a fixed potential to the shielding portion 90 by using the existing fixed potential signal line is conducive to simplifying the overall design of the display panel when the shielding portion 90 is introduced into the display panel, so it is conducive to improving the production efficiency of the display panel.

[0060] The scheme of using the fixed potential signal in the display panel to provide the shielding portion 90 with the fixed potential signal will be described in detail below.

[0061] Fig.12 FIG. 1 is another schematic diagram showing another connection between the pixel driving circuit 10 and the light emitting element 30 in the display panel. Figure 2 The difference is that a bias module is introduced into the pixel driving circuit 10, please refer to Figure 2 and Fig.12In an optional embodiment of the present disclosure, the pixel driving circuit 10 includes a second reset module 76 and a bias module 77, the two ends of the second reset module 76 are respectively connected to the second reset signal line Vref2 and the fourth node N4, and the fourth node N4 is connected to the anode of the light-emitting element 30; the two ends of the bias module 77 are respectively connected to the bias signal line DVH and the second node N2, or the two ends of the bias module 77 are respectively connected to the bias signal line DVH and the third node N3; the figure takes the bias module 77 connecting the third node N3 as an example for explanation, and the present disclosure does not specifically limit this. The display panel also includes a power signal line, and the fixed potential signal line includes one of the power signal line, the first reset signal line Vref1, the second reset signal line Vref2 and the bias signal line DVH, and the shielding portion 90 and the fixed potential signal line electrically connected thereto are arranged on the same layer.

[0062] For the pixel driving circuit 10, the signal lines connected thereto and capable of sending fixed potential signals include a first reset signal line Vref1 for transmitting a reset signal to the first reset module 71, a second reset signal line Vref2 for transmitting a reset signal to the second reset module 76, power signal lines PVDD and PVEE required for light emission, and a bias signal line DVH for providing a bias potential signal to the bias module 77, wherein the power signal line further includes a positive power signal line PVDD and a negative power signal line PVEE. When the shielding part 90 is introduced into the first display area A11, the shielding part 90 can be electrically connected to any of the above-mentioned fixed potential signal lines, and the corresponding fixed potential signal is used as a shielding signal provided to the shielding part 90. Fig.10 and Fig.11 The embodiment shown shows a scheme of electrically connecting the shielding portion 90 to the second reset signal line Vref2. Figure 7 and Figure 8 The illustrated embodiment shows a scheme of electrically connecting the shielding portion 90 to the power signal line PVDD. In some other embodiments of the present disclosure, the shielding portion 90 may also be electrically connected to the bias signal line DVH. When actually connected, the shielding portion 90 and the corresponding fixed potential signal line may be arranged on the same layer, which is equivalent to forming a portion of the extension portion 82 as the shielding portion 90 on the basis of the original fixed potential signal line. The shielding portion 90 and the fixed potential signal line do not need to be connected through a via, and can be manufactured in the same process as the corresponding fixed potential signal line, which is beneficial to simplify the overall manufacturing process of the display panel.

[0063] Please refer to Figure 1In an optional embodiment of the present disclosure, the first display area A11 includes a first sub-area A01 and a second sub-area A02 arranged along a first direction D1, the first sub-area A01 is located between the second sub-area A02 and the binding area A2, and a projection area of ​​the shielding portion 90 corresponding to the pixel driving circuit 10 in the first sub-area A01 on the plane where the light emitting surface of the display panel is located is greater than a projection area of ​​the shielding portion 90 corresponding to the pixel driving circuit 10 in the second sub-area A02 on the plane where the light emitting surface of the display panel is located. The first sub-area A01 in the first display area A11 can be regarded as an area closer to the binding area A2, and the second sub-area A02 is farther away from the binding area A2 than the first sub-area A01. Therefore, the voltage drop on the second scan line S2 in the first sub-area A01 is smaller than the voltage drop on the second scan line S2 in the second sub-area A02. When a signal jump occurs, the signal influence of the second scan line S2 in the first sub-area A01 on the first node N1 will be greater than the signal influence of the second scan line S2 in the second sub-area A02 on the first node N1. Therefore, in the embodiment of the present disclosure, the first sub-area A01 and the second scan line S2 in the first sub-area A01 are connected to the first node N1. The area of ​​the shielding portion 90 introduced in the second sub-area A02 is designed differently, so that the area of ​​the shielding portion 90 in the first sub-area A01 is larger than the area of ​​the shielding portion 90 in the second sub-area A02, thereby reducing the influence of the second scan line S2 in the first sub-area A01 on the first node N1, balancing the difference in the influence of the second scan line S2 on the potential of the first node N1 in the first sub-area A01 and the second sub-area A02, thereby facilitating the improvement of the display brightness uniformity of the first sub-area A01 and the second sub-area A02, and further facilitating the improvement of the overall display brightness uniformity of the display panel. When the shielding portion 90 in the second sub-area A02 and the first sub-area A01 are designed differently, the shielding portion 90 in the first sub-area A01 can be, for example, Figure 8 The structure shown in FIG. 1 (the area of ​​the shielding portion 90 is larger), the shielding portion 90 in the second sub-area A02 may be formed as follows: Figure 7 It should be noted that the first sub-area A01 and the second sub-area A02 in the figure are only for illustration and do not limit the number of pixel circuit rows actually included in the first sub-area A01 and the second sub-area A02.

[0064] Based on the same inventive concept, the present disclosure further provides a display device 200, Fig.13 FIG. 2 is a schematic diagram of a structure of a display device 200 provided in an embodiment of the present disclosure. Fig.13, the display device 200 includes the display panel 100 in any of the above embodiments. The display device 200 provided in the embodiment of the present disclosure may be any electronic device with a display function, such as a tablet computer with touch and display functions, a display cabinet display product, a television, or a vehicle-mounted display device. The display device 200 provided in the embodiment of the present disclosure has the beneficial effects of the display panel 100 provided in the embodiment of the present disclosure. For details, please refer to the specific description of the display panel 100 in the above embodiments, which will not be repeated in this embodiment.

[0065] Understandably, Fig.13 The display device is illustrated only in a rectangular structure. In some other embodiments of the present disclosure, the display device 200 may also be embodied as a circle, a rounded rectangle, an ellipse, or any other feasible shape, and the present disclosure does not specifically limit this.

[0066] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0067] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: It comprises a display area and a binding area located at one side of the display area along a first direction, wherein the display area comprises a plurality of light-emitting elements and a pixel driving circuit connected to the light-emitting elements; The pixel driving circuit comprises a driving transistor, a first reset module and a data writing module, wherein the gate of the driving transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the third node; the two ends of the first reset module are respectively connected to the first reset signal line and the first node, and the control end is connected to the first scan line; the two ends of the data writing module are respectively connected to the data signal line and the second node, and the control end is connected to the second scan line; the third node is used to be electrically connected to the light emitting element; The display area includes a first display area and a second display area arranged along the first direction, and the first display area is located between the second display area and the binding area; in each of the pixel driving circuits, a first capacitor is formed between the first node and the second scanning line; the capacitance of the first capacitor in the pixel driving circuit corresponding to the first display area is smaller than the capacitance of the first capacitor in the pixel driving circuit corresponding to the second display area.

2. The display panel according to claim 1, characterized in that: In the pixel driving circuit of the first display area, a shielding portion is provided on the side of the first node toward the second scanning line along a direction parallel to the light emitting surface of the display panel, and the shielding portion receives a fixed potential signal.

3. The display panel according to claim 2, characterized in that: The gate of the driving transistor is electrically connected to the first node via a first connecting portion, the first connecting portion and the second scanning line are arranged in different layers, and along a second direction, the first connecting portion and the second scanning line overlap to form a first overlapping area, and the second direction is perpendicular to the plane where the light emitting surface of the display panel is located; The shielding portion includes a first shielding portion, and along the second direction, the first shielding portion overlaps with the first overlapping region, and at least a portion of the first shielding portion is located between the first connecting portion and the second scanning line.

4. The display panel according to claim 2 or 3, characterized in that: The second scanning line includes a main body portion, the main body portion extends along a third direction, and the main body portion and the first node are arranged along the first direction, and the third direction intersects the first direction and is parallel to a plane where a light emitting surface of the display panel is located; The shielding portion includes a second shielding portion located between the first node and the main portion of the second scan line along the first direction.

5. The display panel according to claim 4, characterized in that: When the shielding portion includes a first shielding portion and a second shielding portion, the first shielding portion and the second shielding portion are electrically connected and located on the same layer.

6. The display panel according to claim 2, characterized in that: The second scanning line includes a main body and an extension portion connected to the main body, the main body extends along a third direction, the third direction intersects with the first direction and is parallel to the plane where the light emitting surface of the display panel is located; the extension portion extends along the first direction and is located on a side of the main body facing the first node; the main body and the first node are arranged along the first direction, and the extension portion and the first node are arranged along the third direction; The shielding portion includes a third shielding portion, and the third shielding portion is located between the first node and the extension portion along the third direction; or the third shielding portion includes an electrically connected first sub-portion and a second sub-portion, and the first sub-portion is located between the first node and the extension portion along the third direction, and the second sub-portion is located between the first node and the main body along the first direction.

7. The display panel according to claim 2, characterized in that: The second scanning line includes a main body and an extension portion connected to the main body, the main body extends along a third direction, the third direction intersects with the first direction and is parallel to the plane where the light emitting surface of the display panel is located; the extension portion extends along the first direction and is located on a side of the main body facing the first node; the main body and the first node are arranged along the first direction, and the extension portion and the first node are arranged along the third direction; The shielding portion includes a fourth shielding portion, and the fourth shielding portion overlaps with the extending portion along a second direction, and the second direction is perpendicular to a plane where the light emitting surface of the display panel is located.

8. The display panel according to claim 7, characterized in that: The pixel driving circuit includes a second reset module, two ends of the second reset module are respectively connected to a second reset signal line and a fourth node, the fourth node is connected to the anode of the light-emitting element; the second reset signal line includes a main line extending along a third direction and a connecting line extending along a first direction, the main line and the connecting line are electrically connected, and the third direction intersects with the first direction; The display panel comprises a plurality of the pixel driving circuits arranged along a first direction, and two of the second reset signal lines corresponding to two adjacent pixel driving circuits along the first direction are electrically connected by the connecting line; The fourth shielding portion is electrically connected to the connecting line.

9. The display panel according to claim 2, characterized in that: The display panel includes a fixed potential signal line, and the shielding portion is electrically connected to the fixed potential signal line.

10. The display panel according to claim 9, characterized in that: The pixel driving circuit comprises a second reset module and a bias module, wherein two ends of the second reset module are respectively connected to a second reset signal line and a fourth node, and the fourth node is connected to the anode of the light-emitting element; two ends of the bias module are respectively connected to a bias signal line and a second node, or two ends of the bias module are respectively connected to a bias signal line and a third node; The display panel also includes a power signal line, the fixed potential signal line includes the power signal line, the first reset signal line, the second reset signal line and one of the bias signal lines, and the shielding portion and the fixed potential signal line electrically connected thereto are arranged on the same layer.

11. The display panel according to claim 2, characterized in that: The first display area includes a first sub-area and a second sub-area arranged along the first direction, the first sub-area is located between the second sub-area and the binding area, and the projection area of ​​the shielding part corresponding to the pixel driving circuit in the first sub-area on the plane where the light emitting surface of the display panel is located is larger than the projection area of ​​the shielding part corresponding to the pixel driving circuit in the second sub-area on the plane where the light emitting surface of the display panel is located.

12. The display panel according to claim 1, characterized in that: The display panel includes M pixel drive circuit rows; the display panel includes N cascaded gate drive circuits, N=M+s; The first scan line corresponding to the pixel driving circuit located in the mth row is electrically connected to the gate driving circuit of the mth level, and the second scan line corresponding to the pixel driving circuit located in the mth row is electrically connected to the gate driving circuit of the m+sth level; wherein 1≤m≤M, s≥2; The pixel driving circuit row connected to the gate driving circuits of the M+1th to M+sth stages is located in the first display area.

13. A display panel, characterized in that: It comprises a display area and a binding area located at one side of the display area along a first direction, wherein the display area comprises a plurality of light-emitting elements and a pixel driving circuit connected to the light-emitting elements; The pixel driving circuit comprises a driving transistor, a first reset module and a data writing module, wherein the gate of the driving transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the third node; the two ends of the first reset module are respectively connected to the first reset signal line and the first node, and the control end is connected to the first scan line; the two ends of the data writing module are respectively connected to the data signal line and the second node, and the control end is connected to the second scan line; the third node is used to be electrically connected to the light emitting element; The display area includes a first display area and a second display area arranged along the first direction, and the first display area is located between the second display area and the binding area; in the pixel driving circuit of the first display area, a shielding part is arranged on the side of the first node toward the second scanning line along a direction parallel to the light emitting surface of the display panel, and the shielding part receives a fixed potential signal.

14. The display panel according to claim 13, characterized in that: The gate of the driving transistor is electrically connected to the first node via a first connecting portion, the first connecting portion and the second scanning line are arranged in different layers, and along a second direction, the first connecting portion and the second scanning line overlap to form a first overlapping area, and the second direction is perpendicular to the plane where the light emitting surface of the display panel is located; The shielding portion includes a first shielding portion, and along the second direction, the first shielding portion overlaps with the first overlapping region, and at least a portion of the first shielding portion is located between the first connecting portion and the second scanning line.

15. The display panel according to claim 13 or 14, characterized in that: The second scanning line includes a main body portion, the main body portion extends along a third direction, and the main body portion and the first node are arranged along the first direction, and the third direction intersects the first direction and is parallel to a plane where a light emitting surface of the display panel is located; The shielding portion includes a second shielding portion, and along the first direction, the second shielding portion is located between the first node and the second scanning line.

16. The display panel according to claim 15, characterized in that: When the shielding portion includes a first shielding portion and a second shielding portion, the first shielding portion and the second shielding portion are electrically connected and located on the same layer.

17. The display panel according to claim 16, characterized in that: The second scanning line includes a main body and an extension portion connected to the main body, the main body extends along a third direction, the third direction intersects with the first direction and is parallel to the plane where the light emitting surface of the display panel is located; the extension portion extends along the first direction and is located on a side of the main body facing the first node; the main body and the first node are arranged along the first direction, and the extension portion and the first node are arranged along the third direction; The shielding portion includes a third shielding portion, and the third shielding portion is located between the first node and the extension portion along the third direction; or the third shielding portion includes an electrically connected first sub-portion and a second sub-portion, and the first sub-portion is located between the first node and the extension portion along the third direction, and the second sub-portion is located between the first node and the main body along the first direction.

18. The display panel according to claim 13, characterized in that: The second scanning line includes a main body and an extension portion connected to the main body, the main body extends along a third direction, the third direction intersects with the first direction and is parallel to the plane where the light emitting surface of the display panel is located; the extension portion extends along the first direction and is located on a side of the main body facing the first node; the main body and the first node are arranged along the first direction, and the extension portion and the first node are arranged along the third direction; The shielding portion includes a fourth shielding portion, and the fourth shielding portion overlaps with the extending portion along a second direction, and the second direction is perpendicular to a plane where the light emitting surface of the display panel is located.

19. A display device, characterized in that: The display panel comprises any one of claims 1 to 18.

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