Package and semiconductor device

Abstract

The invention relates to a package and a semiconductor device. This package is provided with: a base (10) having a mounting region on which a semiconductor chip is mounted; a frame body (12) provided on the base so as to surround the mounting region; a first metal layer (14a) provided on the upper surface of the frame body, the first metal layer having a first portion to which a first bonding wire electrically connecting the semiconductor chip is bonded, a second portion separated from the mounting region with respect to the first portion, and a first connection portion connected to the second portion; the first connecting part is used for connecting the first part with the second part; a first insulating layer (16a) provided on the first connection portion so as to be in contact with the first connection portion, the first insulating layer (16a) traversing the first metal layer; and a first lead (18a) bonded to the second portion.

Description

Technical Field

[0001] The present invention relates to a package and a semiconductor device. Background Art

[0002] It is known that a frame surrounding a semiconductor chip mounted on a base is provided on the base, and a feedthrough for electrically connecting the semiconductor chip to the outside is provided in an opening of the frame on the base (for example, Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-113284

[0006] The structure of the package with feedthrough is complicated and therefore expensive. Therefore, the following structure is considered: a metal layer is provided on the upper surface of the frame, and the bonding wire connected to the semiconductor chip and the lead are bonded on the metal layer. However, the solder etc. of the substrate that mounts the lead to the outside sometimes wets and spreads from the lead to the metal layer and reaches the bonding wire. As a result, undesirable conditions such as the bonding wire breaking may occur. Summary of the invention

[0007] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to suppress defects in bonding wires.

[0008] One embodiment of the present disclosure is a package, which comprises: a base having a mounting area for mounting a semiconductor chip; a frame provided on the base in a manner of surrounding the mounting area; a first metal layer provided on the upper surface of the frame, having a first part, a second part and a first connecting part, wherein the first part is for bonding a first bonding wire for electrically connecting the semiconductor chip, the second part is away from the mounting area relative to the first part, and the first connecting part connects the first part with the second part; a first insulating layer provided on the first connecting part in contact with the first connecting part, crossing the first metal layer; and a first lead bonded to the second part.

[0009] One embodiment of the present disclosure is a package, which comprises: a base having a mounting area for mounting a semiconductor chip; a frame provided on the base in a manner of surrounding the mounting area; a first metal layer provided on the upper surface of the frame, having a first part and a second part, wherein the first part is bonded with a first bonding wire for electrically connecting the semiconductor chip, and the second part is away from the mounting area relative to the first part and is separated from the first part on the upper surface of the frame; a first wiring provided in the frame, electrically connecting the first part and the second part; and a first lead bonded to the second part, the upper surface of the frame being exposed from the first metal layer in a manner of crossing the first metal layer in an area separating the first part from the second part.

[0010] Effects of the Invention

[0011] According to the present disclosure, it is possible to suppress defects in the bonding wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 1 is a top view of the semiconductor device of Example 1.

[0013] Figure 2 yes Figure 1 A-A section view.

[0014] Figure 3 It is a top view showing the semiconductor device of Example 1 mounted in a housing.

[0015] Figure 4 yes Figure 3 A-A section view.

[0016] Figure 5A It is a figure which shows the manufacturing method of the package of Example 1.

[0017] Figure 5B It is a figure which shows the manufacturing method of the package of Example 1.

[0018] Fig. 6A It is a figure which shows the manufacturing method of the package of Example 1.

[0019] Figure 6B It is a figure which shows the manufacturing method of the package of Example 1.

[0020] Fig. 7A It is a figure which shows the manufacturing method of the package of Example 1.

[0021] Figure 7B It is a figure which shows the manufacturing method of the package of Example 1.

[0022] Fig. 8AIt is a figure which shows the manufacturing method of the package of Example 1.

[0023] Figure 8B It is a figure which shows the manufacturing method of the package of Example 1.

[0024] Fig. 9 It is a figure which shows the manufacturing method of the package of Example 1.

[0025] Fig.10 This is an enlarged top view of the semiconductor device of Comparative Example 1.

[0026] Fig.11 yes Fig.10 A-A section view.

[0027] Fig.12 This is an enlarged top view of the semiconductor device of Example 1.

[0028] Fig.13 yes Fig.12 A-A section view.

[0029] Fig.14 It is a top view of the semiconductor device of Example 2.

[0030] Fig.15 yes Fig.14 A-A section view.

[0031] Fig.16 yes Fig.14 B-B section view.

[0032] Fig.17 It is an enlarged cross-sectional view of a semiconductor device of Comparative Example 2.

[0033] Fig.18 This is an enlarged cross-sectional view of the semiconductor device of Example 2.

[0034] Fig.19 It is a top view of the semiconductor device of Example 3.

[0035] Fig. 20 yes Fig.19 A-A section view.

[0036] Fig.21 This is a top view of the semiconductor device of Example 4.

[0037] Fig. 22 yes Fig.21 A-A section view.

[0038] Fig.23 This is an enlarged top view of the semiconductor device of Example 4.

[0039] Fig.24 yes Fig.23 A-A section view.

[0040] Description of reference numerals:

[0041] 10: base;

[0042] 11: Installation area;

[0043] 12: frame;

[0044] 13, 14a, 14b, 35, 61, 64a, 64b: metal layer;

[0045] 15: Multilayer substrate;

[0046] 15a, 15b, 15c, 16a, 16b: insulating layer;

[0047] 18a, 18b: leads;

[0048] 20: semiconductor chips;

[0049] 21, 26, 31: substrate;

[0050] 22, 23, 24, 27, 28, 32, 33: electrodes;

[0051] 34, 36, 37, 39: bonding layer;

[0052] 38: Cover;

[0053] 38a: frame portion;

[0054] 38b: ceiling;

[0055] 40, 42, 44, 46: bonding lines;

[0056] 45: resin sealing member;

[0057] 47: through hole;

[0058] 48a, 48b: metal layer;

[0059] 51a, 51b, 52a, 52b, 53a, 53b: part;

[0060] 55: arrow;

[0061] 58, 63: opening;

[0062] 65: solder layer;

[0063] 66: solder;

[0064] 80, 82, 84: packaging;

[0065] 100 , 102 , 104 , 106 , 110 , 112 : semiconductor devices. DETAILED DESCRIPTION

[0066] [Description of Embodiments of the Present Disclosure]

[0067] First, the contents of the embodiments of the present disclosure will be listed and described.

[0068] (1) One embodiment of the present disclosure is a package, the package comprising: a base having a mounting area for mounting a semiconductor chip; a frame provided on the base so as to surround the mounting area; a first metal layer provided on the upper surface of the frame, having a first portion, a second portion, and a first connection portion, wherein the first portion is bonded to a first bonding wire for electrically connecting the semiconductor chip, the second portion is away from the mounting area relative to the first portion, and the first connection portion connects the first portion to the second portion; a first insulating layer provided on the first connection portion in contact with the first connection portion and crossing the first metal layer; and a first lead bonded to the second portion. Thus, it is possible to prevent solder from spreading to the first portion and causing a defect in the first bonding wire.

[0069] (2) In the above (1), the frame body and the first insulating layer may be mainly composed of ceramics. This can suppress thermal stress.

[0070] (3) In the above (1) or (2), the wettability of the surface of the first insulating layer to the solder may be lower than the wettability of the surface of the first metal layer to the solder. This can prevent the solder from spreading to the surface of the first insulating layer.

[0071] (4) In any one of the above (1) to (3), the package may include: a second metal layer provided on the upper surface of the frame body, having a third portion, a fourth portion, and a second connection portion, wherein the third portion is bonded with a second bonding wire for electrically connecting the semiconductor chip, the fourth portion is away from the mounting area relative to the third portion, and the second connection portion connects the third portion to the fourth portion; a second insulating layer provided on the second connection portion in contact with the second connection portion and crossing the second metal layer; and a second lead bonded to the fourth portion. Thus, it is possible to prevent solder from spreading to the third portion and causing a defect in the second bonding wire.

[0072] (5) One embodiment of the present disclosure is a package, the package comprising: a base having a mounting area for mounting a semiconductor chip; a frame provided on the base so as to surround the mounting area; a first metal layer provided on the upper surface of the frame and having a first portion and a second portion, wherein the first portion is bonded to a first bonding wire for electrically connecting the semiconductor chip, and the second portion is away from the mounting area relative to the first portion and separated from the first portion on the upper surface of the frame; a first wiring provided in the frame and electrically connecting the first portion and the second portion; and a first lead bonded to the second portion, the upper surface of the frame being exposed from the first metal layer in a region separating the first portion from the second portion so as to cross the first metal layer. Thus, it is possible to prevent solder from spreading to the first portion and causing a defect in the first bonding wire.

[0073] (6) In the above (5), the wettability of the surface of the frame to the solder may be lower than the wettability of the surface of the first metal layer to the solder. This can suppress the solder from spreading on the surface of the frame.

[0074] (7) In the above (5) or (6), the package may include: a second metal layer provided on the upper surface of the frame body, having a third portion and a fourth portion, wherein the third portion is bonded with a second bonding wire for electrically connecting the semiconductor chip, and the fourth portion is away from the mounting region relative to the third portion; a second wiring provided in the frame body, electrically connecting the third portion and the fourth portion; and a second lead bonded to the fourth portion, wherein the upper surface of the frame body is exposed from the second metal layer in a manner that crosses the second metal layer in a region separating the third portion from the fourth portion. This can prevent solder from spreading to the third portion and causing a defect in the second bonding wire.

[0075] (8) One embodiment of the present disclosure is a semiconductor device including: the package as described in (1) above; and the semiconductor chip mounted on the base. Thus, the semiconductor chip can be mounted.

[0076] (9) In the above (8), the semiconductor device may include a resin sealant that is bonded to the upper surface of the frame and the upper surface of the first metal layer to seal the semiconductor chip. This can prevent solder from being transferred between the first metal layer and the resin sealant.

[0077] (10) One embodiment of the present disclosure is a semiconductor device, comprising: the package as described in (2) above; the semiconductor chip mounted on the base; and a cover bonded to the upper surface of the frame and the upper surface of the first insulating layer using a resin adhesive to seal the semiconductor chip. Thus, the transfer of solder between the resin adhesive and the first metal layer can be suppressed.

[0078] (11) One embodiment of the present disclosure is a semiconductor device including: the package as described in (5) above; and the semiconductor chip mounted on the base. Thus, the semiconductor chip can be mounted.

[0079] (12) In the above (11), the semiconductor device may include a resin sealant that is bonded to the upper surface of the frame and the upper surface of the first metal layer to seal the semiconductor chip. This can prevent solder from being transferred between the first metal layer and the resin sealant.

[0080] [Details of the embodiments of the present disclosure]

[0081] Hereinafter, specific examples of the package and semiconductor device according to the embodiments of the present disclosure will be described with reference to the drawings. It should be noted that the present disclosure is not limited to these examples, but is indicated by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims.

[0082] [Example 1]

[0083] Figure 1 1 is a top view of the semiconductor device of Example 1. Figure 2 yes Figure 1 The normal direction of the base 10 is defined as the Z direction, the extending direction of the straight line connecting the lead 18a and the lead 18b is defined as the X direction, and the direction orthogonal to the X direction and the Z direction is defined as the Y direction.

[0084] like Figure 1 and Figure 2As shown, in the semiconductor device 100 of the first embodiment, the semiconductor chip 20, the passive element chip 25 and the passive element chip 30 are mounted on the package 80. The package 80 includes a base 10, a frame 12, a metal layer 14a, a metal layer 14b, an insulating layer 16a, an insulating layer 16b, a lead 18a, a lead 18b and a bonding layer 36. A mounting area 11 is provided on the upper surface of the base 10. The mounting area 11 is an area for mounting chips such as the semiconductor chip 20, the passive element chip 25 and the passive element chip 30 (i.e., an area that can be mounted). A reference potential such as a ground potential is supplied to the base 10. A frame 12 is provided on the base 10 so as to surround the mounting area 11. A metal layer 14a and a metal layer 14b are provided on the upper surface of the frame 12. The metal layer 14 a is provided at the center of the frame body 12 on the − direction side in the X direction in the Y direction, and the metal layer 14 b is provided at the center of the frame body 12 on the + direction side in the X direction in the Y direction.

[0085] The metal layer 14a includes portions 51a to 53a arranged in the X direction, and the metal layer 14b includes portions 51b to 53b arranged in the X direction. The portions 51a and 51b are respectively close to the mounting area 11, and the portions 52a and 52b are respectively far from the mounting area 11 relative to the portions 51a and 51b. The portion 53a is sandwiched between the portions 51a and 52a in the X direction. The portion 53b is sandwiched between the portions 51b and 52b in the X direction. The insulating layers 16a and 16b extending in the Y direction are provided on the portions 53a and 53b, respectively.

[0086] The insulating layer 16a crosses the metal layer 14a in the Y direction, dividing the metal layer 14a into a portion 51a and a portion 52a. The insulating layer 16b crosses the metal layer 14b in the Y direction, dividing the metal layer 14b into a portion 51b and a portion 52b. A lead 18a is provided on the portion 52a of the metal layer 14a. A lead 18b is provided on the portion 52b of the metal layer 14b. The conductive bonding layer 36 bonds the metal layer 14a and the metal layer 14b to the lead 18a and the lead 18b, respectively. The metal layer 14a and the lead 18a are electrically connected and short-circuited. The metal layer 14b and the lead 18b are electrically connected and short-circuited. The lead 18a extends from the portion 52a of the metal layer 14a to the - direction in the X direction, and the lead 18b extends from the portion 52b of the metal layer 14b to the + direction in the X direction.

[0087] A passive element chip 25, a semiconductor chip 20, and a passive element chip 30 are mounted in order along the + direction in the X direction in the mounting area 11. The semiconductor chip 20 includes a substrate 21 and electrodes 22 to 24. The substrate 21 is, for example, a semiconductor substrate. The electrodes 22 and 23 are provided on the upper surface of the substrate 21. The electrode 24 is provided on the lower surface of the substrate 21. The passive element chip 25 includes a substrate 26, an electrode 27, and an electrode 28. The substrate 26 is, for example, a dielectric substrate. The electrode 27 is provided on the upper surface of the substrate 26, and the electrode 28 is provided on the lower surface of the substrate 26. The passive element chip 30 includes a substrate 31, an electrode 32, and an electrode 33. The substrate 31 is, for example, a dielectric substrate. The electrode 32 is provided on the upper surface of the substrate 31, and the electrode 33 is provided on the lower surface of the substrate 31. The conductive bonding layer 34 bonds the base 10 to the electrodes 24, 28, and 33. Electrode 24, electrode 28, and electrode 33 are electrically connected to base 10 and short-circuited. Bonding wire 40 electrically connects portion 51a of metal layer 14a to electrode 27. Bonding wire 42 electrically connects electrode 27 to electrode 22. Bonding wire 44 electrically connects electrode 23 to electrode 32. Bonding wire 46 electrically connects electrode 32 to portion 51b of metal layer 14b.

[0088] The base 10 is a conductive plate, such as a copper plate, a metal plate having a laminated structure of a copper layer and a molybdenum layer, or a copper-molybdenum alloy plate. The frame 12 is an insulating layer, such as a ceramic layer. The ceramic layer is an inorganic insulating layer such as a metal oxide or a metal nitride, such as a sintered body with aluminum oxide (such as Al2O3) as the main component. The metal layer 14a and the metal layer 14b are, for example, a single layer, a laminated layer, or an alloy layer of tungsten, platinum, silver, or copper. The insulating layer 16a and the insulating layer 16b are inorganic insulating layers such as ceramics or organic insulating layers such as resins, as an example, a sintered body with aluminum oxide (such as Al2O3) as the main component. The lead 18a and the lead 18b are metal plates such as copper plates, having a plating layer such as a gold layer. The bonding layer 36 is a solder or a metal paste, as an example, a silver-copper alloy. The bonding layer 34 is, for example, a solder or a metal paste, as an example, gold-tin or silver paste.

[0089] The thickness of the base 10 is, for example, 800 μm to 2000 μm. The thickness of the frame 12 is, for example, 500 μm to 1500 μm. The width of the frame 12 is ( Figure 2 The width in the X direction of the insulating layer 16a and the insulating layer 16b is, for example, 600 μm to 2000 μm. The thickness of the metal layer 14a and the metal layer 14b is, for example, 10 μm to 100 μm. The thickness of the lead 18a and the lead 18b is, for example, 50 μm to 200 μm. The thickness of the insulating layer 16a and the insulating layer 16b is, for example, 10 μm to 200 μm. The width ( Figure 2In order to ensure the area of ​​the portion 51a and the portion 51b joined by the bonding wire 40 and the bonding wire 46 and the area of ​​the portion 52a and the portion 52b joined by the lead 18a and the lead 18b, the width of the insulating layer 16a and the insulating layer 16b can be set to be less than or equal to 1 / 3 of the width of the frame 12.

[0090] The semiconductor chip 20 includes, for example, a transistor. The transistor is, for example, a FET (Field Effect Transistor), and as an example, a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or a LDMOS (Laterally Diffused Metal Oxide Semiconductor). The electrode 22, the electrode 23, and the electrode 24 are, for example, connected to the gate, the drain, and the source. The electrode 22 is, for example, an input electrode for inputting a high-frequency signal, and the electrode 23 is, for example, an output electrode for outputting a high-frequency signal. When the semiconductor chip 20 has a GaN HEMT, the substrate 21 is, for example, a silicon carbide substrate or a gallium nitride substrate. The electrodes 22 to 24 are, for example, metal layers such as a gold layer.

[0091] Passive component chip 25 and passive component chip 30 are, for example, capacitors. Substrate 26 and substrate 31 are, for example, dielectric substrates, and as an example, are alumina substrates or high dielectric ceramic substrates having a relative dielectric constant greater than that of alumina substrates. Electrode 27, electrode 28, electrode 32, and electrode 33 are, for example, metal layers such as gold layers. Substrate 26 and electrodes 27 and 28 holding substrate 26 form capacitors. Substrate 31 and electrodes 32 and 33 holding substrate 31 form capacitors. Bonding wires 40, bonding wires 42, bonding wires 44, and bonding wires 46 form inductors. Bonding wires 40, passive component chip 25, and bonding wires 42 form input matching circuits. Bonding wires 44, passive component chip 30, and bonding wires 46 form output matching circuits.

[0092] The high-frequency signal input to the lead 18a is input to the electrode 22 via the input matching circuit. The high-frequency signal amplified by the semiconductor chip 20 is output from the electrode 23 through the output matching circuit and from the lead 18b. When the semiconductor device 100 is used as an amplifier circuit for a mobile communication base station, the frequency of the high-frequency signal is, for example, 0.5 GHz to 10 GHz.

[0093] In the first embodiment, the semiconductor device 100 is described as an example in which the semiconductor chip 20 , the passive element chip 25 , and the passive element chip 30 are mounted in the mounting region 11 . However, as long as the semiconductor chip 20 is provided, the passive element chip 25 and the passive element chip 30 may not be mounted.

[0094] [Installation method of embodiment 1]

[0095] An example in which the semiconductor device 100 is mounted in a housing will be described. Figure 3 It is a top view showing the semiconductor device of Example 1 mounted in a housing. Figure 4 yes Figure 3 A-A section view. Figure 3 and Figure 4 As shown, a substrate 62 is provided on the housing 60. A metal layer 61 is provided on the lower surface of the substrate 62. The metal layer 61 and the housing 60 are joined by a conductive bonding layer. An opening 63 is provided on the substrate 62. The opening 63 is, for example, a groove extending in the Y direction. The housing 60 is exposed from the opening 63. A metal layer 64a and a metal layer 64b are provided on the substrate 62, and the metal layer 64a and the metal layer 64b are lines extending in the X direction. The metal layer 61, the metal layer 64a, and the metal layer 64b that clamp the substrate 62 function as a transmission line (for example, a microstrip line) for transmitting a high-frequency signal. The base 10 of the semiconductor device 100 is joined to the housing 60 in the opening 63 using a solder layer 65. The lead 18a and the lead 18b are joined to the metal layer 64a and the metal layer 64b respectively using solder 66.

[0096] The housing 60 is a metal plate such as a copper plate, an aluminum plate or a stainless steel plate. The substrate 62 is an insulating substrate such as a resin substrate such as a glass epoxy resin substrate. The metal layer 61, the metal layer 64a and the metal layer 64b are, for example, a copper layer or a gold layer. The solder layer 65 and the solder 66 are, for example, tin, silver, copper, etc.

[0097] The high-frequency signal is input from the metal layer 64a to the lead 18a, and is output from the lead 18b to the metal layer 64b. When the base 10 is bonded to the case 60, the heat generated in the semiconductor chip 20 is released to the case 60 through the base 10.

[0098] [Method for manufacturing package of Example 1]

[0099] Figure 5A to Figure 9 It is a figure which shows the manufacturing method of the package of Example 1. Figures 5A to 8A It is a top view. Figure 5B to Figure 8B as well as Fig. 9 is equivalent to Figures 5A to 8A Diagram of the A-A section.

[0100] like Figure 5A and Figure 5B As shown, an opening 58 is formed in a green sheet to form a frame 12. A green sheet is a ceramic sheet before firing. A metal layer 14a and a metal layer 14b are formed on the frame 12. A pattern printing method is used to form the metal layer 14a and the metal layer 14b. A metal layer may be formed on the upper surface of the frame 12 as a circuit pattern in addition to the metal layer 14a and the metal layer 14b. In addition, the opening 58 may be formed after the metal layer 14a and the metal layer 14b are formed on the green sheet.

[0101] like Fig. 6A and Figure 6B As shown, insulating layers 16a and 16b are formed on metal layers 14a and 14b on frame 12. Insulating layers 16a and 16b are formed, for example, by applying a paste material containing particles of an inorganic insulator such as alumina to frame 12. Then, frame 12, insulating layers 16a and 16b are fired.

[0102] like Fig. 7A and Figure 7B As shown, a bonding layer 39 is applied to the lower surface of the frame 12. The frame 12 is arranged on the base 10 with the bonding layer 39 interposed therebetween.

[0103] like Fig. 8A and Figure 8B As shown in FIG. 1 , the leads 18a and 18b coated with the bonding layer 36 on the lower surface are arranged on the metal layers 14a and 14b. The bonding layer 39 is cured by heating, thereby bonding the frame 12 to the base 10, and the leads 18a and 18b are bonded to the metal layers 14a and 14b respectively by curing the bonding layer 36. The bonding temperature is higher than Fig. 6A and Figure 6B The firing temperature is low.

[0104] like Fig. 9 As shown, a metal layer 35 is formed on the exposed surfaces of the metal layer 14a, the metal layer 14b, the lead 18a, and the lead 18b by, for example, plating. The metal layer 35 is a metal having good wettability with solder, for example, a gold plating layer. Figure 1 and Figure 2 In the figure, the metal layer 35 is omitted. Through the above, the package of Example 1 is manufactured.

[0105] Then, if Figure 1 and Figure 2 As shown in FIG. 1 , the semiconductor chip 20, the passive element chip 25, and the passive element chip 30 are bonded to the mounting region 11 using the bonding layer 34. The temperature ratio of the bonding semiconductor chip 20, the passive element chip 25, and the passive element chip 30 is Fig. 8A and Figure 8BThe bonding temperature is low. Then, the bonding wires 40, 42, 44, and 46 are formed. Through the above, the semiconductor device 100 of the first embodiment is manufactured.

[0106] [Comparative Example 1]

[0107] Fig.10 It is an enlarged plan view of the semiconductor device of Comparative Example 1, and is an enlarged plan view of the vicinity of the metal layer 14 a . Fig.11 yes Fig.10 A-A section view. Fig.10 and Fig.11 As shown, when the semiconductor device 110 of Comparative Example 1 is installed, for example, the lead 18a is soldered to Figure 3 and Figure 4 At this time, a metal layer 35 is provided on the surface of the lead 18a and the metal layer 14a. The metal layer 35 is, for example, a gold layer, and has good wettability with the solder 66. Therefore, sometimes the molten solder 66 wets and spreads on the metal layer 35 on the surface of the lead 18a as shown by the arrow 55. Furthermore, the solder 66 wets and spreads on the metal layer 35 on the surface of the metal layer 14a to the portion where the bonding wire 40 is bonded. As a result, a defect occurs in the bonding wire 40. For example, when the bonding wire 40 is a gold wire, the gold reacts with the solder and causes the bonding wire 40 to break.

[0108] [Description of Example 1]

[0109] Fig.12 It is an enlarged top view of the semiconductor device of Example 1, and is an enlarged top view of the vicinity of the metal layer 14 a . Fig.13 yes Fig.12 A-A section view. Fig.12 and Fig.13 As shown, in the package 80 of Example 1, a bonding wire 40 (first bonding wire) electrically connecting the semiconductor chip 20 is bonded to a portion 51a (first portion) of the metal layer 14a (first metal layer). That is, the portion 51a is a portion (bondable portion) for bonding the bonding wire 40. The lead 18a (first lead) is bonded to a portion 52a (second portion) of the metal layer 14a. A portion 53a (first connecting portion) of the metal layer 14a connects the portion 51a and the portion 52a. The insulating layer 16a (first insulating layer) is disposed on the portion 53a in contact with the portion 53a, and crosses the metal layer 14a. Thus, the insulating layer 16a functions as a weir or dam of the solder 66, thereby preventing the solder 66 from being damaged. Fig.10 and Fig.11 As shown in Comparative Example 1, the ions spread to the portion 51a and caused a defect in the bonding wire 40. In addition, the bonding wire 40 and the lead 18a were electrically connected and short-circuited.

[0110] The frame 12 and the insulating layer 16a are mainly composed of ceramics. Thus, the frame 12 and the insulating layer 16a having better high-frequency characteristics than resin can be used. The linear expansion coefficient of ceramics is smaller than that of resin, so the thermal stress between the metal layer 14a and the insulating layer 16a can be reduced. In addition, the linear expansion coefficients of the frame 12 and the insulating layer 16a are close, so the thermal stress can be reduced. The frame 12 and the insulating layer 16a are mainly composed of the same material. Thus, the linear expansion coefficients of the frame 12 and the insulating layer 16a can be made approximately the same, which can reduce thermal stress. Moreover, the frame 12 and the insulating layer 16a are mainly composed of alumina. Thus, the frame 12 and the insulating layer 16a having good high-frequency characteristics can be used. In addition to the main component, the frame 12 and the insulating layer 16a may also contain an organic insulator or an inorganic insulator other than the main component, such as a bonding material. The content of the main component in the frame 12 and the insulating layer 16a is, for example, 50 mol% or more, 80 mol% or more.

[0111] The surface of the insulating layer 16a has lower wettability to the solder 66 than the surface of the metal layer 14a. This can prevent the solder 66 from spreading on the surface of the insulating layer 16a. This can make the insulating layer 16a function as a weir or dam for the solder 66.

[0112] like Figure 1 and Figure 2 As shown, in the metal layer 14b, a bonding wire 46 (second bonding wire) electrically connecting the semiconductor chip 20 is also bonded to a portion 51b (third portion) of the metal layer 14b (second metal layer). A lead 18b (second lead) is bonded to a portion 52b (fourth portion) of the metal layer 14b. A portion 53b (second connection portion) of the metal layer 14b connects the portion 51b to the portion 52b. An insulating layer 16b (second insulating layer) is provided on the portion 53b in contact with the portion 53b, and crosses the metal layer 14b. Thus, similar to the metal layer 14a, it is possible to suppress the solder 66 from spreading to the portion 51b and causing a defect in the bonding wire 46. In this way, when a plurality of metal layers 14a and metal layers 14b are provided, the insulating layer 16a and the insulating layer 16b can be provided on the plurality of metal layers 14a and metal layers 14b, respectively.

[0113] [Example 2]

[0114] Fig.14 It is a top view of the semiconductor device of Example 2. Fig.15 and Fig.16 They are Fig.14 The A-A section view and the B-B section view. Figure 14 to Figure 16As shown, the semiconductor device 102 of the second embodiment includes a package 82. The package 82 includes a cover 38. The cover 38 includes a frame portion 38a and a ceiling portion 38b. The frame portion 38a surrounds the mounting area 11 when viewed from above. The bonding layer 37 bonds the lower surface of the frame portion 38a to the upper surface of the frame 12 and the upper surfaces of the insulating layer 16a and the insulating layer 16b. The ceiling portion 38b is provided in a manner covering the mounting area 11. The base 10, the frame 12, and the cover 38 hermetically seal the semiconductor chip 20, the passive element chip 25, and the passive element chip 30 in the gap.

[0115] The cover 38 is, for example, an insulating plate such as ceramic. The cover 38 may also be a metal plate. The bonding layer 37 is, for example, a resin adhesive such as epoxy resin. Fig.15 and Fig.16 As shown, the upper surface of the frame 12 and the upper surfaces of the insulating layers 16a and 16b are at different heights. The height difference between the upper surface of the frame 12 and the upper surfaces of the insulating layers 16a and 16b can be absorbed by the bonding layer 37.

[0116] [Comparative Example 2]

[0117] Fig.17 FIG. 2 is an enlarged cross-sectional view of a semiconductor device of Comparative Example 2. Fig.17 As shown, in the semiconductor device 112 of Comparative Example 2, the insulating layer 16a is not provided, and the cover 38 is bonded to the metal layer 14a using the bonding layer 37. The other configurations are the same as those of Example 2. The solder 66 is transferred on the surface of the lead 18a and the metal layer 14a as indicated by the arrow 55. If the adhesion between the metal layer 14a and the bonding layer 37 is high, the bonding layer 37 becomes a weir or dam of the solder 66.

[0118] However, the metal layer 14a such as a gold layer has low adhesion to the bonding layer 37 such as a resin adhesive. In particular, the bonding wire 40 is bonded to the upper surface of the metal layer 14a. Therefore, in order to improve the bonding between the bonding wire 40 and the metal layer 14a, the flatness of the upper surface of the metal layer 14a is high. Therefore, the adhesion between the metal layer 14a and the bonding layer 37 is reduced. Therefore, if the temperature rises and falls repeatedly, the metal layer 14a and the bonding layer 37 may peel off. In particular, the linear expansion coefficient of gold is 14×10 -6 K -1 The linear expansion coefficient of aluminum oxide is 7×10 -6 K -1 The linear expansion coefficient of epoxy resin adhesive is 30×10 -6 K -1 ~80×10 - 6 K -1. Thus, the linear expansion coefficient of the resin-based adhesive is larger than that of the metal. Therefore, if the temperature rises and falls repeatedly, a large thermal stress is applied between the metal layer 14a and the bonding layer 37, and the bonding layer 37 is easily peeled off from the metal layer 14a. If the bonding layer 37 peels off, the solder 66 may sometimes spread between the metal layer 14a and the bonding layer 37 as shown by the dotted ellipse 56, and the solder 66 may reach the bonding portion of the bonding wire 40. As a result, the bonding wire 40 may be broken.

[0119] [Description of Example 2]

[0120] Fig.18 FIG. 2 is an enlarged cross-sectional view of the semiconductor device of Example 2. Fig.18 As shown, in the semiconductor device 102 of the second embodiment, an insulating layer 16a is provided on the metal layer 14a, and a bonding layer 37 is provided on the insulating layer 16a. A cover 38 is bonded to the upper surface of the frame 12 and the upper surface of the insulating layer 16a using a resin adhesive as the bonding layer 37. The insulating layer 16a is a ceramic such as Fig. 6A and Figure 6B As shown, when the frame 12 and the insulating layer 16a sandwich the metal layer 14a for firing, the metal layer 14a and the insulating layer 16a have high adhesion. In addition, the upper surface of the insulating layer 16a has large concavoconvexity, and the adhesion of the insulating layer 16a and the bonding layer 37 is improved due to the anchoring effect. Moreover, when the main components of the frame 12 and the insulating layer 16a are the same, the linear expansion coefficients of the frame 12 and the insulating layer 16a are approximately the same, and the difference in linear expansion coefficients between the metal layer 14a and the insulating layer 16a is smaller than the difference in linear expansion coefficients between the metal layer 14a and the bonding layer 37. As a result, the thermal stress between the metal layer 14a and the insulating layer 16a is smaller than the thermal stress between the metal layer 14a and the bonding layer 37 of Comparative Example 2. As a result, the insulating layer 16a is not easily peeled off from the metal layer 14a. As a result, the insulating layer 16a becomes a weir or dam of the solder 66. As a result, it is possible to prevent the solder 66 from reaching the bonding wire 40 and breaking the bonding wire 40. In Example 2, Fig.14 As shown in the figure, the example in which the frame body portion 38a overlaps with the insulating layer 16a and the insulating layer 16b in a plan view has been described, but the frame body portion 38a and the insulating layer 16a and the insulating layer 16b do not need to overlap.

[0121] In order to reduce thermal stress of the frame 12, the insulating layer 16a and the cover 38, the cover 38 may be made of ceramic. In addition, the main component of the cover 38 may be the same as that of the frame 12 and the insulating layer 16a. The main component of the cover 38 is, for example, aluminum oxide.

[0122] [Example 3]

[0123] Example 3 is an example using a potting resin. Fig.19 It is a top view of the semiconductor device of Example 3. Fig. 20 yes Fig.19 A-A section view. Fig.19 In FIG. 4 , the resin sealant 45 is shown by a dotted line. Fig.19 and Fig. 20 As shown, in the semiconductor device 104 of the third embodiment, the resin sealant 45 is potted on the package 80. The resin sealant 45 is bonded to the upper surface of the frame 12 and the upper surfaces of the metal layer 14a and the metal layer 14b to seal the semiconductor chip 20. The resin sealant 45 is, for example, epoxy resin, polyurethane resin or silicone resin. The potted resin sealant 45 is softer than the cover 38 shown in the second embodiment. Therefore, the stress between the resin sealant 45 and the frame 12 is relieved. However, the adhesion between the resin sealant 45 and the metal layer 14a is low. Therefore, if the insulating layer 16a and the insulating layer 16b are not provided, the solder 66 will enter between the metal layer 14a and the metal layer 14b and the resin sealant 45, and the bonding wire 40 is easily broken. Therefore, by providing the insulating layer 16a and the insulating layer 16b, the solder 66 can be suppressed from being transferred between the metal layer 14a and the metal layer 14b and the resin sealant 45.

[0124] [Example 4]

[0125] Embodiment 4 is an example in which a multilayer printed circuit board is used in a frame. Fig.21 This is a top view of the semiconductor device of Example 4. Fig. 22 yes Fig.21 A-A section view. Fig.21 and Fig. 22 As shown, the semiconductor device 106 of the fourth embodiment includes a package 84. The package 84 includes a multilayer substrate 15. The multilayer substrate 15 includes insulating layers 15a to 15c stacked in layers. The insulating layer 15a is the lowest insulating layer and corresponds to the base 10. A metal plate 15d (copper plate (coin)) is embedded in the insulating layer 15a. The metal plate 15d corresponds to the mounting area 11. The semiconductor chip 20, the passive component chip 25, and the passive component chip 30 are mounted on the metal plate 15d. A metal layer 13 is provided on the lower surface of the insulating layer 15a and the metal plate 15d. The insulating layer 15b and the insulating layer 15c correspond to the frame 12. A metal layer 48a and a metal layer 48b are provided between the insulating layer 15b and the insulating layer 15c. A metal layer 14a and a metal layer 14b are provided on the upper surface of the insulating layer 15c.

[0126] Fig.23 This is an enlarged top view of the semiconductor device of Example 4. Fig.24 yes Fig.23 A-A section view. Fig.23 The through hole 47 is shown by a dotted line in FIG. Fig.23 and Fig.24As shown, the metal layer 14a is provided in the portion 51a and the portion 52a, but not in the portion 53a. The insulating layer 15c is exposed from the metal layer 14a in the portion 53a. In the portion 53a, the metal layer 48a is provided under the insulating layer 15c. The two ends of the metal layer 48a in the X direction are electrically connected to the metal layers 14a of the portion 51a and the portion 52a via the metal layer in the through hole 47 penetrating the insulating layer 15c, respectively, and are short-circuited. Thus, the portion 51a and the portion 52a are electrically connected via the metal layer 48a.

[0127] The wettability of the surface of the insulating layer 15c of the portion 53a to the solder is lower than the wettability of the surface of the metal layer 35 to the solder. Even if the solder 66 wets and spreads on the metal layer 35 on the surface of the lead 18a and the metal layer 14a as shown by the arrow 55, the solder 66 does not wet and spread to the upper surface of the insulating layer 15c. As a result, the solder 66 does not spread to the portion 51a, and the breakage of the bonding wire 40 can be suppressed.

[0128] The insulating layers 15a to 15c are resin layers such as glass epoxy resin, for example. The metal plate 15d is a copper plate, for example. The metal layer 48a is a single layer, a laminated layer, or an alloy layer of silver, gold, or copper, for example. The other configurations are the same as those in the first embodiment, and their description is omitted.

[0129] According to Embodiment 4, on the upper surface of the frame 12, the portion 51a of the metal layer 14a is separated from the portion 52a, and the upper surface of the frame 12 is exposed from the metal layer 14a in a manner that crosses the metal layer 14a in the region where the portion 51a is separated from the portion 52a. The metal layer 48a (first wiring) electrically connects the portion 51a and the portion 52a. In this way, by using the upper surface of the frame 12 as a weir or dam of the solder 66, it is possible to suppress the solder 66 from spreading to the bonding wire 40 and causing a defect in the bonding wire 40. In addition, the bonding wire 40 can be electrically connected to the lead 18a through the metal layer 48a to short-circuit.

[0130] The wettability of the surface of the frame 12 to the solder 66 is lower than the wettability of the surface of the metal layer 14a to the solder 66. This can suppress the solder 66 from spreading on the surface of the frame 12. This can make the frame 12 function as a weir or dam for the solder 66.

[0131] like Fig.21 and Fig. 22 As shown, in the metal layer 14b, also on the upper surface of the frame 12, the portion 51b of the metal layer 14b is separated from the portion 52b, and the upper surface of the frame 12 is exposed from the metal layer 14b in a manner that crosses the metal layer 14b in the region where the portion 51b is separated from the portion 52b. The metal layer 48b (second wiring) electrically connects the portion 51b and the portion 52b. Thus, as with the metal layer 14a, it is possible to suppress the solder 66 from spreading to the portion 51b and causing a defect in the bonding wire 46.

[0132] As shown in Example 4, when a multilayer printed circuit board is used in the frame, the cover 38 may be bonded to the upper surface of the frame 12 and the upper surface of the insulating layer 15c to seal the semiconductor chip 20 as shown in Example 2. This can prevent the solder 66 from passing through between the metal layer 14a and the metal layer 14b and the cover 38 and reaching the bonding wire 40 and the bonding wire 46.

[0133] Furthermore, when a multilayer printed circuit board is used in the frame 12, the semiconductor chip 20 may be sealed by bonding the resin sealant 45 to the upper surface of the frame 12 and the upper surfaces of the metal layers 14a and 14b as shown in Embodiment 3. This prevents the solder 66 from passing through between the metal layers 14a and 14b and the resin sealant 45 and reaching the bonding wires 40 and 46.

[0134] The embodiments disclosed herein should be considered to be illustrative in all aspects and not restrictive. The scope of the present disclosure is indicated by the claims rather than the above meaning, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A package comprising: A base having a mounting area for mounting a semiconductor chip; A frame body is arranged on the base in a manner of surrounding the installation area; The first metal layer is disposed on the upper surface of the frame body and has a first portion, a second portion and a first connecting portion, wherein: The first portion is used for bonding a first bonding wire that electrically connects the semiconductor chip, the second portion is away from the mounting area relative to the first portion, and the first connecting portion connects the first portion and the second portion; A first insulating layer, connected to the first connecting portion and disposed on the first connecting portion, and crossing the first metal layer; as well as The first lead is connected to the second portion.

2. The package according to claim 1, wherein: The frame body and the first insulating layer are mainly composed of ceramics.

3. The package according to claim 1 or 2, wherein: The wettability of the surface of the first insulating layer to the solder is lower than the wettability of the surface of the first metal layer to the solder.

4. The package according to claim 1 or 2, comprising: The second metal layer is disposed on the upper surface of the frame body and has a third portion, a fourth portion and a second connecting portion, wherein: The third portion is used for bonding with a second bonding wire electrically connecting the semiconductor chip, the fourth portion is away from the mounting area relative to the third portion, and the second connecting portion connects the third portion and the fourth portion; A second insulating layer, connected to the second connecting portion and disposed on the second connecting portion, and crossing the second metal layer; as well as The second lead is connected to the fourth portion.

5. A package comprising: A base having a mounting area for mounting a semiconductor chip; A frame body is arranged on the base in a manner of surrounding the installation area; The first metal layer is disposed on the upper surface of the frame body and has a first part and a second part, wherein: The first portion is bonded with a first bonding wire for electrically connecting the semiconductor chip, and the second portion is away from the mounting area relative to the first portion and is separated from the first portion on the upper surface of the frame; a first wiring, disposed in the frame, electrically connecting the first portion and the second portion; as well as A first lead is bonded to the second portion. The upper surface of the frame is exposed from the first metal layer in a region separating the first portion from the second portion so as to cross the first metal layer.

6. The package according to claim 5, wherein: The wettability of the surface of the frame to the solder is lower than the wettability of the surface of the first metal layer to the solder.

7. The package according to claim 5 or 6, comprising: The second metal layer is disposed on the upper surface of the frame and has a third part and a fourth part, wherein: The third portion is for bonding with a second bonding wire electrically connecting the semiconductor chip, and the fourth portion is away from the mounting area relative to the third portion; a second wiring, disposed in the frame, electrically connecting the third portion and the fourth portion; as well as A second lead is bonded to the fourth portion, The upper surface of the frame is exposed from the second metal layer in a region separating the third portion from the fourth portion so as to cross the second metal layer.

8. A semiconductor device comprising: The package as claimed in claim 1; and The semiconductor chip is mounted on the base.

9. The semiconductor device according to claim 8, comprising: The resin sealing member is bonded to the upper surface of the frame body and the upper surface of the first metal layer to seal the semiconductor chip.

10. A semiconductor device comprising: The package as claimed in claim 2; The semiconductor chip is mounted on the base; and The cover is bonded to the upper surface of the frame body and the upper surface of the first insulating layer using a resin adhesive to seal the semiconductor chip.

11. A semiconductor device comprising: The package as claimed in claim 5; and The semiconductor chip is mounted on the base.

12. The semiconductor device according to claim 11, comprising: The resin sealing member is bonded to the upper surface of the frame body and the upper surface of the first metal layer to seal the semiconductor chip.

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