Back-side powered chip stacking structure and preparation method thereof

The back-side powered chip stacking structure achieves a double increase in the number of transistors in the same area, solves the problems of large power supply network space occupation and IR voltage drop, improves the chip density and performance of the packaging structure, and reduces production costs.

CN119447065BActive Publication Date: 2025-10-03SJ SEMICONDUCTOR (JIANGYIN) CORP
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Patent Information

Application Number
CN202310957837.4
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2023-07-31
Publication Date
2025-10-03
Estimated Expiration
2043-07-31

AI Technical Summary

Technical Problem

The power supply network in traditional 2.5D or 3D packaging occupies a large space, making it difficult to reduce the volume of the packaging structure. The high IR voltage drop leads to increased power consumption and decreased device performance, making it difficult to increase chip density and the number of transistors.

Method used

The chip stacking structure with back-side power supply includes two chips bonded together, and signal transmission is achieved through the signal connection layer. The power supply is combined with the power rail and the buried power layer. Only a metal interconnection layer is formed on the back of the chip as the back power supply layer to achieve electrical connection and signal transmission between the upper and lower chips.

Benefits of technology

Double the number of transistors in the same area to achieve the same performance, save process costs, and reduce production costs by using the second chip as a temporary carrier.

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Abstract

The present invention provides a back-powered chip stacking structure and a preparation method thereof, wherein the chip stacking structure comprises two chips bonded together, and the two chips realize signal transmission through a mutually bonded signal connection layer. At the same time, in combination with the setting of the power rail and the embedded power layer, it is only necessary to form a metal interconnection layer as a back power supply layer on the back of the first chip, so that the transistors of the upper and lower chips can be powered and the transmission of electrical signals can be realized. Through the stacking design, the chip stacking structure can achieve twice the number of transistors in the same area. For example, only a 14nm process can be used, and the upper and lower transistor stacking method of the present application can be combined to achieve the number of transistors under a 7nm process, achieving the same performance, thereby saving process costs. In addition, the second chip bonded to the first chip also acts as a temporary carrier, and there is no need to provide an additional temporary carrier, further reducing the production cost.
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