Electronic device and method for manufacturing electronic device

Abstract

An electronic device includes a first electronic component having a Ni-based electrode; and a second electronic component bonded to the Ni-based electrode via the Sn-based solder, in which a (Cu, Ni, Pd) 6Sn5 compound layer is present at a bonding interface between the Ni-based electrode and the Sn-based solder, and the content of Pd present as a (Pd, Ni) Sn4 compound in a matrix phase of the Sn-based solder after bonding is less than or equal to zero than the content of Pd present as the (Cu, Ni, Pd) 6Sn5 compound layer.

Description

Technical Field

[0001] The invention relates to an electronic device and a method for manufacturing the electronic device. Background Art

[0002] Since the RoHS Directive and the ELV Directive restrict the use of lead in electronic control devices installed in automobiles, lead-free has been achieved so far through lead-free solders mainly composed of Sn-3Ag-0.5Cu (weight %). The power modules used in inverters are miniaturized and lightweight, and high power density has become a trend. For example, the following two points need to be met. First, by soldering the upper and lower surfaces of the power semiconductor, heat can be dissipated from the upper and lower surfaces of the power module. Second, by increasing the guaranteed temperature of the power semiconductor joint, more current can flow.

[0003] The Ni-based electrode responsible for bonding with the solder is used as an electrode of the semiconductor element. In order to easily ensure the wettability of the solder, Au or Ag metallization is implemented on the surface of the electrode. However, depending on the heating and storage environment during the chip manufacturing process, Ni sometimes diffuses to the surface of the thin Au metallization or the Ag metallization with more defects, and Ni oxide is generated on the surface farthest from the surface, thereby impairing the bonding performance of the solder. Therefore, a Pd layer is provided on the Ni-based electrode, and Au or Ag metallization is implemented thereon so that Ni oxide is not formed on the surface. This is increasingly the case. Patent document 1 discloses an alloy for lead-free solder balls, which is composed of: Ag: 3% to 6%, Cu: 1% to 4%, Co: 0.01% to 2%, Sn: the rest in terms of atomic %. Prior art literature Patent Literature

[0004] [Patent Document 1] Japanese Patent No. 3724486 Summary of the invention Technical problem to be solved by the invention

[0005] In the invention described in Patent Document 1, there is still room for improvement in the countermeasure against shrinkage cavities. Technical means for solving technical problems

[0006] The electronic device involved in the first embodiment of the present invention includes: a first electronic component, which has a Ni-based electrode; and a second electronic component, which is joined to the Ni-based electrode via a Sn-based solder, and a (Cu, Ni, Pd)6Sn5 compound layer exists at the interface of the joining portion between the Ni-based electrode and the Sn-based solder, and the Pd content existing as a (Pd, Ni)Sn4 compound in the matrix phase of the Sn-based solder after joining is less than the Pd content existing as the (Cu, Ni, Pd)6Sn5 compound layer, or is zero. In the manufacturing method of an electronic device involved in the second embodiment of the present invention, the electronic device includes a first electronic component having a Ni-based electrode and a second electronic component joined to the Ni-based electrode via a Sn-based solder. The manufacturing method of the electronic device includes a configuration step, in which a Sn-based solder containing more Cu than the eutectic component is configured on the surface of the Pd layer for the first electronic component having a Pd layer formed on the periphery of the Ni-based electrode, and the electronic device forms a (Cu, Ni, Pd)6Sn5 compound layer at the interface of the joint between the Ni-based electrode and the Sn-based solder. Effects of the Invention

[0007] According to the present invention, the occurrence of shrinkage cavities can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram showing an example of shrinkage cavities. Figure 2 This is a diagram showing the behavior of solder during cooling. Figure 3 2 is a diagram showing a first structure of an electronic component. Figure 4 This is a diagram showing a structure using general solder. Figure 5 is a diagram showing a second structure of an electronic component. Figure 6 A diagram showing a method for manufacturing a semiconductor device. Figure 7 It is a figure which shows Example 1-6. Figure 8 It is a figure which shows comparative examples 1-2. Fig. 9 It is a diagram showing a method for manufacturing a semiconductor device. Fig.10 It is a figure which shows Example 7-9. Fig.11 It is a figure which shows Comparative Examples 3 and 4. DETAILED DESCRIPTION

[0009] - Implementation Method 1 - Below, refer to Figures 1 to 11 Embodiment 1 of a semiconductor device as an electronic component is described. It is known that when a chip having a Pd (palladium) layer provided on a Ni (nickel)-based electrode is used, shrinkage cavities are more likely to occur at solder joints than when a chip without a Pd layer is used.

[0010] Figure 1 is a diagram showing an example of shrinkage cavities. Figure 1 In FIG. 1 , a solder joint 3 is formed between a semiconductor element 1 and an emitter-side lead 2 of a power module. A shrinkage cavity 101 shown in black is formed in a region of the solder joint 3 close to the emitter-side lead 2. Figure 1 In the example shown, more heat is dissipated from the semiconductor element 1 side than from the emitter side lead 2 side. When shrinkage cavities are formed, the heat dissipation path for releasing the heat of the semiconductor element generated by energization becomes less, making it difficult to ensure reliability. Therefore, if shrinkage cavities are formed, they are judged as defective products in the quality inspection after assembly. It is believed that shrinkage cavities are generated because when Pd formed on the Ni-based electrode of the semiconductor element is soldered, Pd diffuses into the molten Sn (tin)-based lead-free solder, causing the liquidus temperature of the Sn-based lead-free solder to rise.

[0011] The Ni-based electrode in this embodiment is, for example, an electrode formed of only nickel, an electrode formed of nickel and phosphorus, an electrode formed of nickel and vanadium, etc. In this case, the ratio of nickel to phosphorus is, for example, about 100:1 to 15. In this case, the ratio of nickel to vanadium is, for example, about 100:1 to 15.

[0012] Figure 2 This is a diagram showing the behavior of solder during cooling. Figure 2 The left side shows the case where the temperature difference between the start and end of solder solidification is small. Figure 2 The right side of shows a situation where the temperature difference between the start and end of solder solidification is large. Figure 2 In the figure, time passes from the top to the bottom. Figure 2 In the example shown, more heat is dissipated from the side of the semiconductor element 1. Figure 2 As shown on the left, when the temperature difference between the start and end of solder solidification is small, the entire solder joint 3 shrinks as a whole due to the volume shrinkage caused by solidification. Figure 2As shown on the right side of FIG, when the temperature difference between the start and end of solder solidification is large, the solder gradually solidifies from the cooling side, and is affected by the volume contraction during solidification at the final solidified portion, thereby easily forming a shrinkage cavity 101. In addition, assuming that more heat is dissipated from the emitter side lead 2 side than from the semiconductor element 1 side, the shrinkage cavity 101 is formed on the semiconductor element 1 side.

[0013] Figure 3 1 is a diagram showing a first structure of a semiconductor device 100 as an electronic component in the present embodiment. The left side of the diagram shows a state before bonding, and the right side of the diagram shows a state after bonding. A Ni-based electrode 8, a Pd layer 7, and a metal film 6 are present on the surface of a semiconductor element 1. The metal film 6 is a metallization layer formed of Au (gold) or Ag (silver). A Ni plating layer 5 is present on the surface of an emitter side lead 2. In the present embodiment, a copper-added solder 24 is arranged between the metal film 6 and the Ni plating layer 5 and bonded. The copper-added solder 24 is a Sn-based solder to which more Cu (copper) than the eutectic component is added. Specifically, in the copper-added solder 24, the weight % of Cu is greater than 0.9%, preferably greater than 3% and less than 6%, and the weight % of Sn is greater than 80%.

[0014] The copper-added solder 24 containing more Cu than the eutectic component contains a large amount of Cu6Sn5 compound indicated by reference numeral 25 in the solder. By using the Cu6Sn5 compound for bonding, Pd can be incorporated into the Cu6Sn5 compound provided by the solder, and a compound can be formed as a (Cu, Ni, Pd)6Sn5 compound at the bonding interface 26. The solder bonding portion is composed of the bonding interface 26 existing above and below the figure and the solder center layer 27.

[0015] At this time, the Cu content contained in the solder and the thickness L of the solder joint are controlled according to the Pd thickness of the semiconductor element 1, so that Pd can be basically incorporated into the (Cu, Ni, Pd)6Sn5 compound formed on the joint interface 26. Here, the thickness of the Pd layer 7 is represented by d, the thickness of the Pd layer is represented by d, the thickness of the upper joint interface 26 is represented by y1, the thickness of the lower joint interface 26 is represented by y2, the density of Pd is represented by D1, and the density D2 of (Cu, Ni, Pd)6Sn5 is represented by D2. The Pd in ​​(Cu, Ni, Pd)6Sn5 is 3.6% by weight, so the following formula 1 holds true with respect to the weight of Pd. The left side of formula 1 describes the Pd before joining, and the right side describes the Pd after joining. In addition, "x" in formula 1 is an operation symbol representing the product.

[0016] d×D1=(y1+y2)×D2×0.036···(Formula 1)

[0017] Here, the Pd density D1 is 12.03 g / cm3, and the (Cu, Ni, Pd)6Sn5 density D2 is 8.33 g / cm3. Therefore, if equation 1 is rearranged, the following equation 2 can be obtained.

[0018] y=y1+y2=40. 1 × d · · · (Formula 2)

[0019] That is, it can be seen from Formula 2 that the sum of the thickness of the upper joint interface 26 and the thickness of the lower joint interface 26 is about 40 times the thickness of the Pd layer 7 before joining. In addition, when the desired solder thickness L is determined, the required Cu content of the solder can be calculated based on the thickness y of the joint interface 26.

[0020] If all Pd is incorporated into the joint interface 26, the (Pd, Ni)Sn4 compound is almost absent in the solder central layer 27, which can suppress the rise in liquidus temperature and thus suppress shrinkage cavities. When the Pd content present as the (Pd, Ni)Sn4 compound in the matrix phase of the above-mentioned Sn-based solder after joining is less than the Pd content present as the above-mentioned (Cu, Ni, Pd)6Sn5 compound layer, or is zero, the effect of suppressing shrinkage cavities can be significantly obtained. In addition, the Ni content in the (Cu, Ni, Pd)6Sn5 compound layer is less than 5wt.%.

[0021] Figure 4 FIG. 1 is a diagram showing a structure using a general solder for comparison. The left side of the diagram shows the state before joining, and the right side of the diagram shows the state after joining. Figure 4 The left side and Figure 3 Compared with the left side, the general solder 4 is used instead Figure 3 The presence of the Ni-based electrode 8, the Pd layer 7, and the metal film 6 on the surface of the semiconductor element 1 and the presence of the Ni plating layer 5 on the surface of the emitter side lead 2 are similar to Figure 3 The general solder 4 is a Sn-based lead-free solder such as Sn-3Ag-0.5Cu.

[0022] In this case, the Pd contained in the Pd layer 7 is distributed as follows: a portion that reacts with the solder and is incorporated as a component of the (Ni, Cu, Pd)3Sn4 compound formed on the interface of the joint; and a portion that exists as a (Pd, Ni)Sn4 compound in the form of floating islands inside the solder joint. Here, when the joint is considered to be an intermetallic compound at the interface of the joint and a solder portion other than this, the intermetallic compound formed at the interface of the joint has nothing to do with the liquidus temperature of the solder, while the liquidus temperature of the solder portion other than this will affect the difficulty of forming shrinkage cavities. Here, the more (Pd, Ni)Sn4 compounds 23 are formed, the higher the liquidus temperature of the solder, and the easier it is to form shrinkage cavities.

[0023] Figure 5 2 is a diagram showing a second structure of the semiconductor device 100 in this embodiment. Figure 5 As shown, in a semiconductor element 1 such as a power module, two surfaces on the emitter side and the collector side can be soldered together. Specifically, Figure 5 The semiconductor element 1 shown is sandwiched between the collector side lead 12 shown below and the emitter side lead 2 shown above. In this case, since the collector side lead 12 shown below is cooled, the collector side joint portion 13 present on the lower side of the semiconductor element 1 is cooled faster, while the emitter side joint portion denoted by the reference numeral 3 is cooled slower. Since the slower the cooling speed, the more likely shrinkage cavities are to be generated, the emitter side joint portion is more likely to form shrinkage cavities. Therefore, at least in the emitter side joint portion, by joining the semiconductor element having Pd to the Ni-based electrode using a Sn-based solder to which more Cu than the eutectic component is added, the generation of shrinkage cavities can be suppressed.

[0024] (Examples 1 to 6) refer to Figure 6 and Figure 7 Embodiments 1 to 6 will be described. Figure 6 The manufacturing method of the semiconductor device 100A shown is as follows. First, the collector side solder 24-2 is provided to the solder mounting position of the collector side lead 32 made of Cu with roughened Ni plating. On it, a semiconductor element 1 having a Pd layer with a thickness of 600nm is joined to the Ni-based electrodes on both sides. In addition, the emitter side solder 24-1 is arranged on the electrode on the upper surface of the joined semiconductor element 1, and the emitter side lead 31 made of copper with a roughened Ni plating layer is stacked and joined thereon. As a result, in the emitter side joint portion where shrinkage cavities are easily generated, the Pd provided from the semiconductor element can be incorporated into the (Cu, Ni, Pd)6Sn5 compound at the interface of the joint portion in a state where there is almost no (Pd, Ni)Sn4 compound inside the joint portion. Thereafter, the semiconductor device 100A is manufactured by sealing with a transfer molding resin 33.

[0025] The respective compositions of the emitter side solder 24 - 1 and the collector side solder 24 - 2 of each embodiment are as follows: Fig.10 As described in the columns of "Solder on the upper part of the substrate" and "Solder on the lower part of the substrate". For example, in Example 1, the collector side solder 24-2 and the emitter side solder 24-1 are solders containing Sn as the main component and containing 3 wt% or more and less than 6 wt% of Cu. In Example 2, the collector side solder 24-2 and the emitter side solder 24-1 are solders containing Sn as the main component, containing 4 wt% of Ag, and containing 3 wt% or more and less than 6 wt% of Cu.

[0026] In each example, 100 semiconductor devices 100A were manufactured and evaluated for the presence of shrinkage cavities 101. In the evaluation of shrinkage cavities 101, if shrinkage cavities 101 exceeding 5% of the bonding area were not observed in any of the 100 devices, the evaluation was "acceptable", and if shrinkage cavities 101 exceeding 5% were observed in one device, the evaluation was "unacceptable". As a result, all Examples 1 to 6 were "acceptable".

[0027] (Comparative Examples 1-2) refer to Figure 6 and Figure 8 Comparative Examples 1 and 2 are described below. Semiconductor devices were fabricated and evaluated in the same manner as in Comparative Examples 1 and 2, where only the compositions of the emitter-side solder 24-1 and the collector-side solder 24-2 were different from those of Examples 1 to 6. The evaluation results were "failed" in all Comparative Examples 1 and 2.

[0028] (Examples 7 to 9) refer to Fig. 9 and Fig.10 Embodiments 7 to 9 will be described. Fig. 9 The manufacturing method of the semiconductor device 100B shown is as follows. First, a sheet of the substrate lower solder 24-4 is placed on the heat dissipation base 45, and a ceramic insulating substrate 43 is stacked thereon. The emitter side lead 2 is arranged on the upper side of the ceramic insulating substrate 43 as shown in the figure. Next, the substrate upper solder 24-3 is placed on the emitter side lead 2, and after the semiconductor element 1 is set, it is heated and joined. Then, after the solder is joined, the aluminum wire 42 and the terminal 41 are joined, and then the housing 47 is installed. Finally, the semiconductor device 100B is manufactured by sealing the inside of the housing 47 with the gel 46.

[0029] The compositions of the upper substrate solder 24-3 and the lower substrate solder 24-4 of each embodiment are as follows: Fig.10As described in the "Solder on the upper part of the substrate" and "Solder on the lower part of the substrate" columns. In each example, 100 semiconductor devices 100B were produced and the presence of shrinkage cavities 101 was evaluated. In the evaluation of shrinkage cavities 101, if none of the 100 devices was confirmed to have shrinkage cavities 101 exceeding 5% of the bonding area, it was evaluated as "acceptable", and if shrinkage cavities 101 exceeding 5% were observed in one device, it was evaluated as "unacceptable". The result was as follows. Fig.10 As shown, Examples 7 to 9 are all "qualified".

[0030] (Comparative Examples 3 to 4) refer to Fig. 9 and Fig.11 Comparative Examples 3 to 4 are described below. Only the composition of the upper substrate solder 24-3 and the lower substrate solder 24-4 is different from that of Examples 7 to 9. Semiconductor devices were fabricated and evaluated in the same manner as in Comparative Examples 3 to 4. The compositions of the upper substrate solder 24-3 and the lower substrate solder 24-4 of Comparative Examples 3 to 4 are as follows: Fig.11 The evaluation results were as described in the columns of "Solder on the upper part of the substrate" and "Solder on the lower part of the substrate". All of Comparative Examples 1 and 2 were "unacceptable".

[0031] According to the above-described first embodiment, the following effects can be obtained. (1) A semiconductor device 100 as an electronic device includes a semiconductor element 1 having a Ni-based electrode, and an emitter-side lead 2 joined to the Ni-based electrode via a Sn-based solder. A (Cu, Ni, Pd)6Sn5 compound layer exists at a joint interface 26 between the Ni-based electrode and the Sn-based solder, and the Pd content existing as a (Pd, Ni)Sn4 compound in the matrix phase of the Sn-based solder after joining is less than the Pd content existing as a (Cu, Ni, Pd)6Sn5 compound layer, or is zero. Therefore, the generation of shrinkage cavity 101 can be suppressed.

[0032] (2) The semiconductor element 1 includes a plurality of Ni-based electrodes, and the (Cu, Ni, Pd)6Sn5 compound layer exists at least at the interface of the joint between the Ni-based electrode and the Sn-based solder, where the heat dissipation takes the longest time among the plurality of Ni-based electrodes. Figure 6 In the example shown, since heat is dissipated from the collector side lead 32 side at the lower part of the figure, the collector side solder 24-2 that cools faster is less likely to generate shrinkage cavity 101, so the need for countermeasures is low. Figure 6 In the example of the emitter side, if no countermeasures are taken, there is a possibility that the shrinkage cavity 101 will be generated, so the generation of the shrinkage cavity 101 is suppressed by using the solder having the above-mentioned composition.

[0033] (3) In the semiconductor device 100, the Ni content in the (Cu, Ni, Pd)6Sn5 compound layer is 5 wt.% or less.

[0034] (4) A method for manufacturing a semiconductor device 100 including a semiconductor element 1 having a Ni-based electrode and an emitter-side lead 2 joined to the Ni-based electrode via a Sn-based solder includes: for a semiconductor element 1 having a Pd layer formed on the periphery of the Ni-based electrode, a copper-added solder 24 containing more Cu than the eutectic component is arranged on the surface of the Pd layer. In the semiconductor device 100, a (Cu, Ni, Pd)6Sn5 compound layer is formed at the interface of the joint between the Ni-based electrode and the Sn-based solder.

[0035] (5) The semiconductor element 1 includes a plurality of Ni-based electrodes. In the arrangement process, at least during the time required for heat dissipation, Figure 6 A copper-added solder 24 containing more Cu than the eutectic component is arranged between the Ni-based electrode on the upper side of the drawing and the emitter-side lead 31.

[0036] (6) The composition of the copper-added solder 24 containing more Cu than the eutectic component contains 3 to 6 wt. % of Cu.

[0037] (7) As reference Figure 3 As described above, a (Cu, Ni, Pd) 6 Sn 5 compound layer having a thickness L that is 40 times the thickness d of the Pd layer on the Ni electrode of the semiconductor element 1 is formed at the interface of the bonding portion. (Variant 1) In the above-mentioned first embodiment, the composition of the solder for suppressing the generation of the shrinkage cavity 101 in the joint of the power module as a semiconductor element is described. However, since the generation of the shrinkage cavity 101 may become a problem in all cases of electronic components, the application object of the present invention is not limited to the power module, and various semiconductor elements can be applied. In addition, it is not limited to semiconductors, and it can be applied to various electronic devices including electrodes.

[0039] The above-mentioned embodiments and modifications can be combined respectively. Although various embodiments and modifications are described in the above content, the present invention is not limited to these contents. Other modes considered within the scope of the technical concept of the present invention are also included in the scope of the present invention. Description of symbols

[0040] 1: Semiconductor components 7: Pd layer 8: Ni-based electrode 12: Collector side lead 24: Add copper solder 24-1: Emitter side solder 24-2: Collector side solder 24-3: Solder on the upper part of the substrate 24-4: Solder on the bottom of the substrate 31: Emitter side lead 32: Collector side lead 100, 100A, 100B: Semiconductor device 101: Shrinkage.

Claims

1. An electronic device, characterized in that: include: a first electronic component having a Ni-based electrode; as well as a second electronic component joined to the Ni-based electrode via a Sn-based solder, A (Cu, Ni, Pd)6Sn5 compound layer exists at the interface of the joint between the Ni-based electrode and the Sn-based solder. The Pd content existing as the (Pd, Ni)Sn4 compound in the matrix phase of the Sn-based solder after joining is less than the Pd content existing as the (Cu, Ni, Pd)6Sn5 compound layer, or is zero.

2. The electronic device according to claim 1, wherein: The first electronic component is a semiconductor element.

3. The electronic device according to claim 1, wherein: The first electronic component is a semiconductor element having a plurality of the Ni-based electrodes, The (Cu, Ni, Pd)6Sn5 compound layer exists at least at the interface of the joint between the Ni-based electrode and the Sn-based solder, where heat dissipation takes the longest time among the plurality of Ni-based electrodes.

4. The electronic device according to claim 1, wherein: The Ni content in the (Cu, Ni, Pd)6Sn5 compound layer is less than 5 wt.%.

5. A method for manufacturing an electronic device, the electronic device comprising a first electronic component having a Ni-based electrode and a second electronic component joined to the Ni-based electrode via a Sn-based solder, the method for manufacturing an electronic device being characterized in that: The method comprises the step of arranging, on the first electronic component having a Pd layer formed on the periphery of the Ni-based electrode, a Sn-based solder containing a larger amount of Cu than a eutectic component on the surface of the Pd layer, The electronic device forms a (Cu, Ni, Pd)6Sn5 compound layer at the interface of the bonding portion between the Ni-based electrode and the Sn-based solder.

6. The method for manufacturing an electronic device according to claim 5, wherein: The first electronic component is a semiconductor element.

7. The method for manufacturing an electronic device according to claim 5, wherein: The first electronic component is a semiconductor element having a plurality of the Ni-based electrodes, In the arrangement step, a Sn-based solder containing a larger amount of Cu than a eutectic component is arranged between at least the Ni-based electrode that requires the longest time to dissipate heat among the plurality of Ni-based electrodes and the second electronic component.

8. The method for manufacturing an electronic device according to claim 5, wherein: The composition of the Sn-based solder containing more Cu than the eutectic component includes 3 to 6 wt. % of Cu.

9. The method for manufacturing an electronic device according to claim 5, wherein: A (Cu, Ni, Pd) 6 Sn 5 compound layer having a thickness 40 times that of the Pd layer on the Ni electrode of the first electronic component is formed at the interface of the bonding portion.

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