A time self-correction method for hot runner timing controller

Abstract

The present application relates to the technical field of hot runner timing controllers, and discloses a time self-correction method for a hot runner timing controller, which includes: collecting input power frequency signals through an AC detection module; preprocessing the input power frequency signals to obtain preprocessed input power frequency signals; determining suspected zero-crossing positions from the preprocessed input power frequency signals based on a threshold algorithm to obtain a set of suspected zero-crossing positions; generating a logic level diagram based on the input power frequency signal; and verifying each suspected zero-crossing position in the set of suspected zero-crossing positions based on the logic level diagram to obtain a set of confirmed zero-crossing positions. In this way, by introducing a dual verification mechanism of a threshold algorithm and a logic level diagram, the accuracy of zero-crossing detection is significantly improved, and misjudgment caused by noise and other interference is effectively avoided, thereby enhancing the stability and accuracy of the entire time self-correction process.

Description

Technical Field

[0001] The present application relates to the technical field of hot runner timing controllers, and more specifically, to a time self-correction method for a hot runner timing controller. Background Art

[0002] In the field of time self-correction technology for hot runner timing controllers, ensuring high precision and stability of time is the key to achieving precise control. Prior art CN115079553A proposes a time self-correction method for hot runner timing controllers, the core of which is to control the timer to start time correction through a microcontroller, and record the internal time data when the zero-crossing interrupt occurs, and then use the sliding arithmetic mean filter to process these data to obtain the timer calibration coefficient under the current environment, and finally compensate and correct the timer based on the nominal value of the crystal oscillator frequency. This method can effectively reduce the clock deviation caused by factors such as temperature changes and device aging, ensure that the deviation will not accumulate during long-term operation, and maintain the normal operation of the timing controller.

[0003] However, although this solution solves the problem of time accuracy to a certain extent, it still has some limitations in practical applications. For example, it may not fully consider the noise interference in the input power frequency signal and the misjudgment of the suspected zero-crossing point position, which may lead to inaccurate zero-crossing interrupt detection, thereby affecting the accuracy of subsequent time correction. In addition, the existing technology fails to provide sufficient safeguards for how to accurately determine the position of the zero-crossing point, especially when facing a complex and changeable working environment, so that in some cases, the effect of time correction may be discounted.

[0004] Therefore, an optimized hot runner timing controller time self-correction method is expected. Summary of the invention

[0005] In order to solve the above technical problems, the present application is proposed. The embodiment of the present application provides a time self-correction method for a hot runner timing controller, which significantly improves the accuracy of zero-crossing point detection by introducing a dual verification mechanism of a threshold algorithm and a logic level diagram, effectively avoids misjudgment caused by noise and other interference, and thus enhances the stability and accuracy of the entire time self-correction process.

[0006] According to one aspect of the present application, a method for self-correction of time of a hot runner timing controller is provided, comprising the steps of: controlling a timer in the timing controller to start a time correction program based on a microcontroller of the timing controller; after the timer starts the time correction program, detecting a zero-crossing interrupt and recording the internal time data of the microcontroller each time a zero-crossing interrupt occurs; processing the internal time data to obtain a correction coefficient of the timer under the current environment; and compensating and correcting the timer based on the correction coefficient, wherein the detecting a zero-crossing interrupt and recording the internal time data of the microcontroller each time a zero-crossing interrupt occurs comprises: collecting an input power frequency signal through an AC detection module; preprocessing the input power frequency signal to obtain a preprocessed input power frequency signal; determining a suspected zero-crossing position from the preprocessed input power frequency signal based on a threshold algorithm to obtain a set of suspected zero-crossing positions; generating a logic level diagram based on the input power frequency signal; and verifying each suspected zero-crossing position in the set of suspected zero-crossing positions based on the logic level diagram to obtain a set of confirmed zero-crossing positions.

[0007] In the above-mentioned hot runner timing controller time self-correction method, the input power frequency signal is preprocessed to obtain a preprocessed input power frequency signal, including: inputting the input power frequency signal into a low-pass filter to remove high-frequency noise in the input power frequency signal to obtain the preprocessed input power frequency signal, wherein the cutoff frequency of the low-pass filter is 80 Hz.

[0008] In the above-mentioned hot runner timing controller time self-correction method, a logic level diagram is generated based on the input power frequency signal, including: using an analog-to-digital converter to sample the input power frequency signal to obtain a set of sampling point data; inputting the set of sampling point data into a comparator to obtain the logic level diagram.

[0009] In the above-mentioned hot runner timing controller time self-correction method, the set of sampling point data is input into the comparator to obtain the logic level diagram, including: in response to the sampling point data exceeding the preset threshold, outputting a high level; in response to the sampling point data being lower than the preset threshold, outputting a low level.

[0010] In the above-mentioned hot runner timing controller time self-correction method, based on the logic level diagram, each suspected zero-crossing position in the set of suspected zero-crossing positions is verified to obtain a set of confirmed zero-crossing positions, including: aligning the logic level diagram and the pre-processed input power frequency signal; marking the actual interruption position in the logic level diagram to obtain a set of actual interruption positions; for each group of corresponding suspected zero-crossing positions and actual interruption positions, calculating the time interval between the suspected zero-crossing position and the actual interruption position; based on the time interval, verifying each suspected zero-crossing position.

[0011] In the above-mentioned hot runner timing controller time self-correction method, the logic level diagram and the pre-processed input power frequency signal are aligned, including: selecting a common reference point in the logic level diagram and the pre-processed input power frequency signal as a starting point; based on the position difference between the reference point of the logic level diagram and the reference point of the pre-processed input power frequency signal, adjusting the lateral displacement of the logic level diagram relative to the pre-processed input power frequency signal so that the logic level diagram and the pre-processed input power frequency signal are aligned with each other.

[0012] In the above-mentioned hot runner timing controller time self-correction method, each suspected zero-crossing position is verified based on the time interval, including: in response to the time interval being less than or equal to a preset time threshold, determining the suspected zero-crossing position as a confirmed zero-crossing position.

[0013] Compared with the prior art, the hot runner timing controller time self-correction method provided in the present application significantly improves the accuracy of zero-crossing point detection by introducing a dual verification mechanism of a threshold algorithm and a logic level diagram, effectively avoiding misjudgment caused by noise and other interferences, thereby enhancing the stability and accuracy of the entire time self-correction process. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present application will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0015] Figure 1 The figure shows a flow chart of a method for self-calibration of time of a hot runner timing controller according to an embodiment of the present application.

[0016] Figure 2 The figure shows a flow chart of detecting a zero-crossing interrupt and recording the internal time data of the microcontroller each time a zero-crossing interrupt occurs according to an embodiment of the present application.

[0017] Figure 3 The figure shows a schematic diagram of a flow chart of generating a logic level diagram based on the input power frequency signal according to an embodiment of the present application.

[0018] Figure 4 The figure shows a schematic flow chart of verifying each suspected zero-crossing point position in the set of suspected zero-crossing point positions based on the logic level diagram to obtain a set of confirmed zero-crossing point positions according to an embodiment of the present application. DETAILED DESCRIPTION

[0019] Below, the exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the exemplary embodiments described here.

[0020] Figure 1 FIG. 1 is a flow chart of a method for self-calibration of a hot runner timing controller according to an embodiment of the present application. Figure 1 As shown, the hot runner timing controller time self-correction method includes the following steps: S1, based on the microcontroller of the timing controller, controlling the timer in the timing controller to start the time correction program; S2, after the timer starts the time correction program, detecting the zero-crossing interrupt and recording the internal time data of the microcontroller when each zero-crossing interrupt occurs; S3, processing the internal time data to obtain the correction coefficient of the timer under the current environment; S4, compensating and correcting the timer based on the correction coefficient.

[0021] In step S1, a microcontroller based on a timing controller controls a timer in the timing controller to start a time correction program. Specifically, the microcontroller, as the brain of the entire control system, is responsible for coordinating and managing all operations. When it receives an instruction to start the time correction program, it means that the system is ready to enter a new correction cycle. At this point, the microcontroller will issue a command to the timer, instructing it to start monitoring and capturing zero-crossing events.

[0022] In step S2, after the timer starts the time correction program, the zero-crossing interrupt is detected and the internal time data of the microcontroller is recorded each time the zero-crossing interrupt occurs. Here, when the timer starts working, it will monitor the zero-crossing event in the input power frequency signal. The so-called "zero-crossing point" refers to the moment when the voltage of the alternating current changes from a positive value to a negative value or vice versa within a cycle. For most power applications, this change usually occurs at half of each cycle. After the zero-crossing point is detected, the system generates a zero-crossing interrupt signal, which is sent to the microcontroller. Once the zero-crossing point is successfully detected, the microcontroller will respond quickly and record various status information of the internal counter at that time, including the second count value, the millisecond count value, and the current count value of the timer. The reason for recording these data is that they directly reflect the behavioral characteristics of the timer at a specific moment. By saving a large amount of such snapshot data, it can be deeply analyzed afterwards to find out potential trends or laws. More importantly, these data will become the basic material for subsequent calculation of calibration coefficients.

[0023] In particular, considering the noise interference in the input power frequency signal and the misjudgment of the suspected zero-crossing point position, these problems may lead to inaccurate zero-crossing interrupt detection, thereby affecting the accuracy of subsequent time correction. In addition, the prior art fails to provide sufficient safeguards for how to accurately determine the position of the zero-crossing point, especially when facing a complex and changeable working environment, so that in some cases, the effect of time correction may be compromised. In response to the above-mentioned shortcomings, the present application proposes new improvement measures in detecting zero-crossing interrupts and recording the internal time data of the microcontroller each time a zero-crossing interrupt occurs. Specifically, the new method not only relies on simple zero-crossing interrupt detection, but introduces a more sophisticated verification mechanism.

[0024] Figure 2 The figure shows a flow chart of detecting a zero-crossing interrupt and recording the internal time data of the microcontroller each time a zero-crossing interrupt occurs according to an embodiment of the present application. Figure 2 As shown, the detection of zero-crossing interruption and recording of the internal time data of the microcontroller each time the zero-crossing interruption occurs include: S21, collecting input power frequency signals through an AC detection module; S22, preprocessing the input power frequency signals to obtain preprocessed input power frequency signals; S23, determining suspected zero-crossing positions from the preprocessed input power frequency signals based on a threshold algorithm to obtain a set of suspected zero-crossing positions; S24, generating a logic level diagram based on the input power frequency signal; S25, based on the logic level diagram, verifying each suspected zero-crossing position in the set of suspected zero-crossing positions to obtain a set of confirmed zero-crossing positions.

[0025] In step S21, the input power frequency signal is collected by the AC detection module. Specifically, the AC power will experience a change from positive to negative or vice versa in one cycle, which is the so-called "zero crossing point". For applications that require high-precision time control, it is crucial to accurately identify these zero crossing points because they provide a stable time reference. Collecting the input power frequency signal through the AC detection module can provide a reliable reference point for the timer, so that the microcontroller can adjust the state of the internal counter according to this reference point, thereby achieving accurate measurement and correction of time.

[0026] In the step S22, the input power frequency signal is preprocessed to obtain a preprocessed input power frequency signal. That is, considering that in an industrial environment, due to the presence of various electromagnetic interferences and other unstable factors, directly using the unprocessed original power frequency signal often cannot meet the high-precision requirements. Therefore, the collected power frequency signal is purified by preprocessing to remove high-frequency noise and other interference components therein. In one example, the input power frequency signal is preprocessed to obtain a preprocessed input power frequency signal, including: inputting the input power frequency signal into a low-pass filter to remove the high-frequency noise in the input power frequency signal to obtain the preprocessed input power frequency signal, wherein the cutoff frequency of the low-pass filter is 80Hz. A low-pass filter is used here to reduce the high-frequency components in the signal and retain the main 50Hz or 60Hz frequency components. 80Hz is selected as the cutoff frequency because there are often a large number of electromagnetic interference sources in industrial environments, and these interferences may be mixed into the power frequency signal, resulting in inaccurate zero-crossing detection. The 80Hz cutoff frequency can effectively filter out most of the unnecessary high-frequency components without affecting the standard power frequency, thereby generating a purer pre-processed input power frequency signal.

[0027] It should be understood that the core of the filter lies in its frequency response characteristics, that is, it allows signals below a certain frequency (such as 80Hz) to pass smoothly, while attenuating signals above this frequency. This frequency selectivity enables the filtered output signal to better reflect the changes in the actual grid voltage without being affected by high-frequency noise. For example, in a typical 50Hz power frequency environment, any component exceeding 80Hz is regarded as potential interference and is effectively suppressed. In this way, the final output signal only contains the low-frequency parts related to the actual power frequency, providing a solid foundation for subsequent sampling and comparison operations.

[0028] In the step S23, the suspected zero-crossing position is determined from the pre-processed input power frequency signal based on the threshold algorithm to obtain a set of suspected zero-crossing positions. It should be understood that, considering that there may be a certain degree of voltage fluctuation in the actual application scenario, the zero-crossing point cannot be simply defined based on zero volts. Instead, an appropriate threshold interval, such as ±5V or so, should be set based on the understanding of the input signal amplitude under normal working conditions. When the signal crosses from the negative half cycle to the positive half cycle or vice versa, and crosses the set threshold limit, it is considered that a zero-crossing event may have occurred.

[0029] In order to accurately capture the zero-crossing moment, the following strategy is adopted in this application: continuously monitor the sign changes of two adjacent samples. If the previous sampling value is less than or equal to the lower threshold and the next sampling value is greater than or equal to the upper threshold (or vice versa), then record this moment as a potential zero-crossing point. In addition, in order to further improve the detection accuracy, after detecting the possible zero-crossing point, the interpolation method can be used to estimate a more accurate zero-crossing moment. For example, linear interpolation can be used to deduce the true zero-crossing time based on the slope between two adjacent sampling points; for nonlinear changes, higher-order polynomial fitting or other numerical methods can be considered.

[0030] In the step S24, a logic level diagram is generated based on the input power frequency signal. It should be understood that the above detection method is not enough to ensure that all suspected zero crossings are real. Therefore, an additional verification step must be introduced to further screen out the real zero crossings. In the present application, by generating a logic level diagram, the continuously changing analog input power frequency signal can be converted into a discrete, easy to process and analyze form, so as to more accurately determine the position of the zero crossing. This step provides a reliable reference point for the timer, so that the microcontroller can adjust the state of the internal counter according to this reference point, thereby achieving accurate measurement and correction of time.

[0031] In one example, generating a logic level diagram based on the input power frequency signal includes: S241, using an analog-to-digital converter to sample the input power frequency signal to obtain a set of sampling point data; S242, inputting the set of sampling point data into a comparator to obtain the logic level diagram.

[0032] Specifically, first, in order to convert the continuously changing analog input power frequency signal into digital form, an analog-to-digital converter (ADC) is required. The selection of ADC is very critical because it directly determines the accuracy of the logic level diagram. In order to obtain high-quality data, an ADC with a higher resolution is usually selected, combined with a reasonable sampling rate. For example, for a 50Hz power frequency signal, the ideal sampling rate should be at least 20 points per cycle, which means that the sampling frequency is at least 1kHz. However, in practical applications, in order to capture as much information as possible and reduce errors, this application selects a higher sampling rate, at least 40 points per cycle, that is, for a 50Hz signal, it means that the sampling frequency reaches more than 2kHz. Such a high sampling rate helps to more finely depict the changing trend of the signal, thereby improving the reliability of subsequent analysis. After completing the analog-to-digital conversion, the next step is to perform threshold determination on the collected data to generate a logic level diagram. This step is completed by a comparator, which outputs a high level when the sampling point data exceeds the preset threshold and outputs a low level when it is lower than the preset threshold. This method helps to screen out the suspected zero-crossing position and provide a reference for further verification. It is worth noting that the threshold setting here is not randomly selected, but is based on a deep understanding of the normal power frequency range and an estimation of the maximum possible deviation. For example, for a 50Hz power frequency signal, if the fluctuation range of ±5% is taken into account, the threshold can be set between the corresponding upper and lower limits. This not only improves the accuracy of the judgment, but also enhances the robustness of the system, enabling it to adapt to different working conditions within a certain range.

[0033] That is, in one example, the set of sampling point data is input into a comparator to obtain the logic level diagram, including: in response to the sampling point data exceeding a preset threshold, outputting a high level; in response to the sampling point data being lower than a preset threshold, outputting a low level.

[0034] In the step S25, based on the logic level diagram, each suspected zero-crossing position in the set of suspected zero-crossing positions is verified to obtain a set of confirmed zero-crossing positions. In one example, based on the logic level diagram, each suspected zero-crossing position in the set of suspected zero-crossing positions is verified to obtain a set of confirmed zero-crossing positions, including: S251, aligning the logic level diagram and the pre-processed input power frequency signal; S252, marking the actual interruption position in the logic level diagram to obtain a set of actual interruption positions; S253, for each group of corresponding suspected zero-crossing positions and actual interruption positions, calculating the time interval between the suspected zero-crossing position and the actual interruption position; S254, verifying each suspected zero-crossing position based on the time interval.

[0035] That is, in order to ensure the time consistency between the logic level diagram and the preprocessed input power frequency signal, an alignment operation is first performed. The alignment operation can provide an accurate basis for subsequent comparison and verification. In one example, the logic level diagram and the preprocessed input power frequency signal are aligned, including: selecting a common reference point as a starting point in the logic level diagram and the preprocessed input power frequency signal; based on the position difference between the reference point of the logic level diagram and the reference point of the preprocessed input power frequency signal, adjusting the logic level diagram to be laterally displaced relative to the preprocessed input power frequency signal so that the logic level diagram and the preprocessed input power frequency signal are aligned with each other. Specifically, the present application selects a common reference point as a starting point in the logic level diagram and the preprocessed input power frequency signal. This reference point can be a known stable peak or trough position, or the most recently successfully detected zero crossing point. Selecting a stable and easily identifiable reference point helps reduce errors and makes the alignment of the two more accurate. Based on the position difference between the reference point of the logic level diagram and the reference point of the preprocessed input power frequency signal, the lateral displacement of the logic level diagram relative to the input power frequency signal is adjusted until the two overlap as much as possible. Considering the slight delay that may be caused by factors such as hardware processing speed, a compensation mechanism can also be introduced to correct this fixed time difference. This process may require several iterations to achieve the best effect and ensure the highest time synchronization between the two.

[0036] Once the alignment is completed, the next step is to mark the actual interruption position on the logic level diagram to form a set of actual interruption positions. Whenever the AC detection module captures a zero-crossing event, an interrupt signal is generated, which is recorded and used as a mark on the logic level diagram. For each set of corresponding suspected zero-crossing positions and actual interruption positions, the time interval (i.e., position difference) between them is calculated. Ideally, these differences should be very small and relatively stable. In this way, those suspected zero-crossing points with large time intervals can be preliminarily screened out, because they may be false alarms caused by noise or other interference factors. For example, in actual applications, if a measurement result shows that most of the time intervals are within ±50μs, but there are two large deviations close to 200μs, then these large deviations are likely to be false detections caused by external interference.

[0037] Finally, each suspected zero-crossing position is verified based on the calculated time interval. Specifically, if the time interval between the suspected zero-crossing position and the actual interruption position is less than or equal to the preset time threshold, the suspected zero-crossing position is determined to be a confirmed zero-crossing position. The preset threshold is set according to the accuracy requirements of the system and the expected working environment, and it usually reflects the maximum allowable deviation range. That is, in one example, based on the time interval, each suspected zero-crossing position is verified, including: in response to the time interval being less than or equal to the preset time threshold, the suspected zero-crossing position is determined to be a confirmed zero-crossing position. This method effectively excludes those data points that are obviously deviated from the normal range, and they are considered to be misjudgments caused by interference. The remaining zero-crossing points after screening are considered to be true and can be used to trigger the timer to start the time correction function. In addition, in order to improve the accuracy of verification, the system will also count multiple groups of such time interval data and perform statistical analysis, such as calculating the average value, standard deviation, etc., to evaluate the overall consistency level. If it is found that large fluctuations frequently occur in certain specific time periods, it may be affected by periodic interference sources, and it is necessary to further analyze the causes of the differences and take corresponding measures to solve them accordingly.

[0038] In a specific example, a hot runner timing controller with a working power supply of standard 220V / 50Hz AC. In order to verify the zero crossing point, the following process is used. First, a 16-bit ADC is used to sample the input power frequency signal in real time at a sampling rate of 10kHz to obtain a signal image; at the same time, a fast-response comparator is used to generate a logic level diagram at the same time point. The high-resolution ADC ensures that even small voltage changes can be accurately captured, improving the quality and accuracy of the data. Selecting a sampling rate of 10kHz means that for a 50Hz signal, there are at least 200 sampling points per cycle. Such a high sampling rate helps to more finely depict the changing trend of the signal, thereby improving the reliability of subsequent analysis. Since the present application knows that a complete cycle of a 50Hz power grid signal is approximately 20ms, the most recently successfully detected zero crossing point can be selected as a reference point, and the logic level diagram can be adjusted so that it is perfectly aligned with the corresponding position on the signal image. Considering that the hardware processing delay is about 1μs, the present application moves this tiny amount of time backward on the logic level diagram. Doing so not only simplifies the subsequent analysis process, but also ensures that the synchronization of the two reaches the highest level, reducing the error caused by time inconsistency. In the next full cycle, the present application marks two suspected zero crossings and the corresponding interruption points, and measures the time interval between them. The results show that most of the differences are within ±50μs, but there are two large deviations close to 200μs. Through the review of historical data, the present application noticed that similar large fluctuations occurred whenever the large motors in the factory were started. In addition, compared with the pre-stored standard data, the results of this measurement did have obvious over-standard conditions. From this, the present application can infer that this is caused by the strong electromagnetic interference generated by the startup moment of nearby equipment. By comparing the standard data set, it can be further confirmed whether there is an abnormal situation, and corresponding measures can be taken to solve it accordingly. Check whether the position difference is randomly distributed or has a certain regularity. If it is found that large fluctuations frequently occur in certain specific time periods, it may be affected by periodic interference sources. For example, in the embodiment of the present application, whenever the large motors in the factory are started, significant fluctuations will be caused. By comparing with the pre-stored standard data set, the present application can find that these fluctuations exceed the allowable range, indicating that there is an interference problem. Further analysis shows that this is due to the strong electromagnetic interference generated at the moment of motor startup. Based on this information, shielding measures can be taken or detection parameters can be adjusted to reduce the impact of interference. Finally, this application regards the two abnormally large position differences as false detections caused by interference and deletes them from the candidate list. The remaining small range of difference points that meet expectations are identified as true zero crossings for subsequent time correction processes.This method can not only effectively eliminate the influence of noise and other interference factors, but also ensure that the final zero-crossing point position is accurate, providing a reliable time reference for the hot runner timing controller.

[0039] In a preferred embodiment of the present application, for the ideal linear behavior of the timer, when each to-be-matched position in the timing direction has a constant proportional error, the selection of the position of the common reference point in the logic level diagram and the preprocessed input power frequency signal has no effect. However, considering the disturbance of the level signal of the logic level diagram by the nonlinear error factor, that is, the disturbance error of the actual interruption position obtained after aligning the logic level diagram and the preprocessed input power frequency signal, it is preferred to use each suspected zero-crossing position as a reference point to calculate the position difference between the reference point of the preprocessed input power frequency signal and ... level signal of the logic level diagram caused by the nonlinear error factor. , and the time interval between each group of suspected zero-crossing positions and the actual interruption positions is .

[0040] Then, since the error disturbance is actually reflected in each group and Therefore, first consider the relationship between and The relationship between In the case of right If a noise-induced phase transition is generated, the noise weak link relationship is used to correct and The global fidelity of is expressed as: In addition, In the case of right A noise-induced phase transition occurs, then: That is, when correcting the fidelity, it is necessary to compensate for the anti-concentration in the common disturbance direction for each suspected zero-crossing position.

[0041] in The modulation coefficient is disturbed to ensure that the difference before and after modulation is less than a predetermined threshold, thereby focusing on the adjustment of the mutual relationship without generating overflow values.

[0042] Then, all the calculated Take the average to obtain the lateral displacement adjustment of the logic level diagram relative to the pre-processed input power frequency signal, and As the time interval between the suspected zero-crossing position and the actual interruption position.

[0043] In step S3, the internal time data is processed to obtain the correction coefficient of the timer in the current environment. Here, the sliding arithmetic mean filtering method is used to process the internal time data. The advantage of this method is that it can smooth out short-term fluctuations and retain long-term trends, so that the obtained results are more stable and reliable. Specifically, the present application will traverse all recorded timestamps, calculate the time difference Δt between each pair of adjacent timestamps, and ensure that the difference is consistent throughout the sequence. The purpose of this is to verify the assumption of the present application that, ideally, the time interval between two zero crossings should be constant. On this basis, the present application selects a suitable time period as a reference, extracts the start time and the end time from it, and calculates the time difference ΔT1-2 corresponding to the timer and the selected time period within the period. With these two time quantities, the calibration coefficient K can be easily obtained. The significance of this coefficient is that it quantifies the gap between the actual operation of the timer under the current environmental conditions and the theoretical expectations. In other words, it tells the present application how to adjust the timer settings to make it perform more in line with expectations.

[0044] In the step S4, the timer is compensated and corrected based on the correction coefficient. Here, based on the calculated calibration coefficient, the present application can take appropriate measures to compensate and correct the timer. The specific approach involved here depends on the size of the frequency deviation value Δf. If the deviation value is relatively small, it can be adjusted directly at one time; but if the deviation is large, it is recommended to adopt a step-by-step compensation strategy to gradually approach the target value. Doing so can not only avoid the risks brought about by a one-time adjustment that is too large, but also give the system enough time to adapt to the new settings, ensuring a smooth transition throughout the process.

[0045] The present invention has the following advantages: by introducing a dual verification mechanism of a threshold algorithm and a logic level diagram, the accuracy of zero-crossing point detection is significantly improved. Specifically, after the AC detection module collects the input power frequency signal, it is pre-processed (such as low-pass filtering to remove high-frequency noise), and the suspected zero-crossing point position is preliminarily determined using a threshold algorithm, and a logic level diagram is generated. Subsequently, these suspected zero-crossing points are further verified based on the logic level diagram to ensure that the zero-crossing point position finally confirmed is accurate. This method not only effectively avoids misjudgments caused by noise and other interferences, but also improves the noise resistance and robustness of the system.

[0046] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0047] The block diagrams of the devices, apparatuses, equipment, and systems involved in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagram. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open words, referring to "including but not limited to", and can be used interchangeably with them. The words "or" and "and" used here refer to the words "and / or" and can be used interchangeably with them, unless the context clearly indicates otherwise. The words "such as" used here refer to the phrase "such as but not limited to", and can be used interchangeably with them.

[0048] It should also be noted that in the apparatus, device and method of the present application, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present application.

[0049] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0050] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A method for self-correcting the time of a hot runner timing controller, comprising the steps of: controlling a timer in the timing controller based on a microcontroller of the timing controller to start a time correction program; after the timer starts the time correction program, detecting a zero-crossing interrupt and recording the internal time data of the microcontroller each time a zero-crossing interrupt occurs; processing the internal time data to obtain a correction coefficient of the timer under the current environment; and compensating and correcting the timer based on the correction coefficient, characterized in that: The method of detecting zero-crossing interrupts and recording the internal time data of the microcontroller each time a zero-crossing interrupt occurs includes: collecting an input power frequency signal through an AC detection module; preprocessing the input power frequency signal to obtain a preprocessed input power frequency signal; determining a suspected zero-crossing point position from the preprocessed input power frequency signal based on a threshold algorithm to obtain a set of suspected zero-crossing point positions; generating a logic level diagram based on the input power frequency signal; and verifying each suspected zero-crossing point position in the set of suspected zero-crossing point positions based on the logic level diagram to obtain a set of confirmed zero-crossing point positions. Wherein, based on the logic level diagram, each suspected zero-crossing position in the set of suspected zero-crossing positions is verified to obtain a set of confirmed zero-crossing positions, including: aligning the logic level diagram and the pre-processed input power frequency signal; marking the actual interruption position on the logic level diagram to obtain a set of actual interruption positions; for each group of corresponding suspected zero-crossing positions and actual interruption positions, calculating the time interval between the suspected zero-crossing position and the actual interruption position; and verifying each suspected zero-crossing position based on the time interval; Wherein, based on the time interval, each suspected zero-crossing position is verified, including: for each of the suspected zero-crossing positions, using it as a reference point to calculate the position difference between it and the reference point of the preprocessed input power frequency signal to obtain a position difference; correcting the global fidelity of the position difference and the time interval based on the noise weak link relationship to obtain a set of compensated position differences and a set of compensated time intervals; taking the mean of the set of compensated position differences as the lateral displacement adjustment of the logic level diagram relative to the preprocessed input power frequency signal; and taking each compensated time interval in the set of compensated time intervals as the time interval between the suspected zero-crossing position and the actual interruption position.

2. The hot runner timing controller time self-calibration method according to claim 1, characterized in that: The input power frequency signal is preprocessed to obtain a preprocessed input power frequency signal, comprising: inputting the input power frequency signal into a low-pass filter to remove high-frequency noise in the input power frequency signal to obtain the preprocessed input power frequency signal, wherein the cutoff frequency of the low-pass filter is 80 Hz.

3. The hot runner timing controller time self-correction method according to claim 1, characterized in that: Based on the input power frequency signal, a logic level diagram is generated, including: using an analog-to-digital converter to sample the input power frequency signal to obtain a set of sampling point data; and inputting the set of sampling point data into a comparator to obtain the logic level diagram.

4. The hot runner timing controller time self-correction method according to claim 3, characterized in that: The set of the sampling point data is input into a comparator to obtain the logic level diagram, including: in response to the sampling point data exceeding a preset threshold, outputting a high level; in response to the sampling point data being lower than a preset threshold, outputting a low level.

5. The hot runner timing controller time self-calibration method according to claim 1, characterized in that: The logic level diagram and the preprocessed input power frequency signal are aligned, including: selecting a common reference point as a starting point in the logic level diagram and the preprocessed input power frequency signal; based on the position difference between the reference point of the logic level diagram and the reference point of the preprocessed input power frequency signal, adjusting the lateral displacement of the logic level diagram relative to the preprocessed input power frequency signal so that the logic level diagram and the preprocessed input power frequency signal are aligned with each other.

6. The hot runner timing controller time self-calibration method according to claim 1, characterized in that: Based on the time interval, verifying each of the suspected zero-crossing positions includes: in response to the time interval being less than or equal to a preset time threshold, determining the suspected zero-crossing position as a confirmed zero-crossing position.

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