A method and apparatus for optimizing the execution of a multiplication function

Abstract

The specification provides a compilation processing method for optimizing multiplication function execution, applied to a compiler including a front-end module and a back-end module. The front-end module converts a large number multiplication function called in a high-level language code into an intermediate representation (IR) code through a preset compilation template; the IR code indicates that a segment multiplication function is called multiple times, and the results of each time are accumulated; wherein each segment multiplication function is used to perform multiplication operation of two data segments of a preset length obtained by segmenting parameters of the large number multiplication function. The back-end module converts the segment multiplication function in the IR code into a hardware instruction suitable for execution by an accelerator. Through the above-mentioned framework of the compiler, parallelization optimization of the back-end and high-level parameter decoupling of the front-end can be realized, so that code generation of optimized large number multiplication suitable for various environments can be realized by using the compilation template.

Description

Technical Field

[0001] This specification relates to the field of computer application technology, and in particular to a compilation processing method and apparatus for optimizing the execution of multiplication functions. Background Technology

[0002] With the development of data privacy technologies, more and more privacy protection technologies are being widely used. These technologies often involve numerous encryption operations, which, for security reasons, typically use at least a 2048-bit key. This results in each encryption operation involving multiple large number multiplications.

[0003] For large number multiplication, there is a lack of an efficient solution that can be performed by accelerator devices in the existing technology. Summary of the Invention

[0004] In view of this, one or more embodiments of this specification provide a compilation processing method and apparatus for optimizing the execution of multiplication functions.

[0005] According to a first aspect of one or more embodiments of this specification, a compilation processing method for optimizing the execution of multiplication functions is proposed, applied to a compiler, the compiler including a front-end module and a back-end module; the method includes:

[0006] The front-end module extracts the large number multiplication function from the high-level language code and converts the large number multiplication function into intermediate expression (IR) code according to a preset compilation template. The IR code indicates that the segment multiplication function is called multiple times and the results of each segment multiplication function are accumulated. The segment multiplication function is used to perform the multiplication of two data segments of a preset length, and the data segments are obtained by segmenting the parameters of the large number multiplication function.

[0007] The backend module converts the segment multiplication function in the IR code into hardware instructions suitable for accelerator execution.

[0008] According to a second aspect of one or more embodiments of this specification, a compiler processing apparatus for optimizing the execution of multiplication functions is provided, applied to a compiler, the apparatus comprising:

[0009] The front-end module is used to extract large number multiplication functions from high-level language code and convert the large number multiplication functions into intermediate expression (IR) code according to a preset compilation template. The IR code indicates that the segment multiplication function is called multiple times and the results of each segment multiplication function are accumulated. The segment multiplication function is used to perform the multiplication of two data segments of preset length, and the data segments are obtained by segmenting the parameters of the large number multiplication function.

[0010] The backend module is used to convert the segment multiplication function in the IR code into hardware instructions suitable for execution by the accelerator.

[0011] According to a third aspect of the embodiments of this specification, a computer-readable storage medium is provided that stores computer instructions thereon, which, when executed by a processor, implement the compilation processing method for optimizing the execution of a multiplication function as described in the first aspect of the embodiments of this specification.

[0012] According to a fourth aspect of the embodiments of this specification, a computer device is provided, the computer device comprising:

[0013] processor;

[0014] Memory used to store processor-executable instructions;

[0015] The processor executes the executable instructions to implement the compilation processing method for optimizing the execution of multiplication functions as described in the first aspect of the embodiments of this specification.

[0016] According to a fifth aspect of the embodiments of this specification, a computer program product is provided, which, when executed by a processor, implements the compilation processing method for optimizing the execution of multiplication functions as described in the first aspect of the embodiments of this specification.

[0017] This specification provides a compilation method for optimizing the execution of multiplication functions, applicable to compilers including front-end and back-end modules. The front-end module converts large number multiplication functions called in the high-level language code into Intermediate Representation (IR) code using a predefined compilation template. The IR code indicates multiple calls to segmented multiplication functions and the summation of the results of each segmented multiplication. Each segmented multiplication function performs the multiplication of two data segments of a predefined length obtained by segmenting the parameters of the large number multiplication function. The back-end module converts the segmented multiplication functions in the IR code into hardware instructions suitable for accelerator execution.

[0018] In the above method, large number multiplication operations in the high-level language are encapsulated into a directly callable function. Through an IR based on piecewise integer multiplication, the piecewise multiplication operation is encapsulated within the piecewise multiplication function. Large number multiplication in the high-level language is encapsulated within a high-level language function independent of various high-level parameters. The backend piecewise multiplication is implemented based on parameterized hardware instructions suitable for accelerator cores, transformed from the piecewise multiplication function. Through the compiler framework described above, backend parallelization optimization and frontend high-level parameter decoupling can be achieved, thus enabling the automatic generation of optimized large number multiplication code suitable for various environments using compilation templates.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0021] Figure 1 This is a schematic diagram illustrating a compiler according to an exemplary embodiment of this specification.

[0022] Figure 2 This is a flowchart illustrating a compilation processing method for optimizing the execution of a multiplication function, according to an exemplary embodiment of this specification.

[0023] Figure 3 This is a schematic diagram of a calculation graph shown in this specification.

[0024] Figure 4 This is a schematic diagram of another calculation diagram shown in this specification.

[0025] Figure 5 This is a schematic diagram of yet another calculation diagram shown in this specification.

[0026] Figure 6 This is a block diagram illustrating a compiler processing apparatus for optimizing the execution of multiplication functions according to an exemplary embodiment of this specification.

[0027] Figure 7 This is a hardware structure diagram of a computer device illustrated in this specification according to an exemplary embodiment. Detailed Implementation

[0028] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with one or more embodiments of this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of one or more embodiments of this specification as detailed in the appended claims.

[0029] It should be noted that the steps of the corresponding methods are not necessarily performed in the order shown and described in this specification in other embodiments. In some other embodiments, the methods may include more or fewer steps than described in this specification. Furthermore, a single step described in this specification may be broken down into multiple steps in other embodiments; and multiple steps described in this specification may be combined into a single step in other embodiments.

[0030] In encryption algorithms, a key of at least 2048 bits is generally required to ensure security. Due to this key bit limitation, the large integer multiplication operations used for key operations during encryption require at least 4096 32-bit integer multiplication instructions; this type of large integer multiplication will be referred to as large number multiplication. The complexity of the encryption process means that it may involve thousands of large number multiplications, which slows down the encryption process.

[0031] In high-level language large number multiplication, the algorithm can be adapted to parameters of different lengths by adjusting loop bounds, and different multiplication variants can be accommodated by modifying the control flow (e.g., eliminating redundant calculations in the squaring operation). In other words, optimizations can be performed at the high-level language algorithm level. Furthermore, to accelerate the encryption process, accelerators (such as GPUs and FPGAs) adept at parallel integer processing are typically used. To better leverage the performance advantages of accelerators, the integer multiplication code executed by the accelerator device can be manually tuned to balance various factors affecting parallel processing speed (such as chip resource usage, communication costs, workload balancing, and memory access patterns).

[0032] However, optimizing both high-level languages ​​and parallel operations simultaneously presents challenges. For instance, an optimization effective in one environment may perform poorly in another. Therefore, customization is required for different environments with varying bit lengths, accelerator devices, and combinations of multiplication variants, which consumes significant optimization time.

[0033] Based on this, this specification provides a compilation processing method and corresponding compiler framework for optimizing the execution of multiplication functions. This compiler framework includes a front-end module and a back-end module. The overall compiler architecture is as follows: Figure 1 As shown. Figure 1 Solid lines represent compilers or modules within compilers, while dashed lines represent code.

[0034] like Figure 1As shown, the front-end module converts the large number multiplication function called in the high-level language code into Intermediate Representation (IR) code using a preset compilation template. The IR code indicates that the segment multiplication function is called multiple times, and the results of each segment multiplication function are accumulated. For example, in the following text, the segment multiplication function is represented as UNIT_MUL. Each segment multiplication function UNIT_MUL performs the multiplication of two data segments of a preset length obtained by segmenting the parameters of the large number multiplication function. The back-end module converts the segment multiplication function in the IR code into parameterized hardware platform instruction code suitable for the accelerator core, based on the accelerator's specification parameters. In the case of a GPU accelerator, this refers to a kernel function that CUDA can process; a kernel function is a function that can be executed by the accelerator's processing core. In the case of an FPGA accelerator, this can be hardware instruction code such as assembly or machine code that the FPGA IP can accept. In the back-end processing, the back-end module, based on the characteristics of the accelerator hardware, utilizes the accelerator's multi-threaded parallel execution capabilities to provide optimized execution and implementation of the segment multiplication function.

[0035] In the above method, large number multiplication operations in high-level languages ​​are encapsulated into a directly callable function. Furthermore, the IR implementation based on piecewise integer multiplication encapsulates the piecewise multiplication operation within the piecewise multiplication function, independent of high-level parameters. The backend module only performs parallelism optimization on the implementation of the piecewise multiplication function itself. Through the compiler framework described above, backend parallelization optimization and frontend high-level parameter decoupling can be achieved, allowing for the automatic generation of large number multiplication optimized code suitable for various environments using compilation templates.

[0036] The following section will describe a compilation processing method for optimizing the execution of multiplication functions, as shown in this specification.

[0037] The methods described in this specification are applied to a compiler, which includes a front-end module and a back-end module. Through the cooperation of the front-end and back-end modules, the conversion from high-level languages ​​to machine code can be achieved. Machine code can be code that can be directly executed by accelerator devices. Accelerator devices can be Field Programmable Gate Arrays (FPGAs), Graphics Processing Units (GPUs), Application Specific Integrated Circuits (ASICs), etc.

[0038] The method described in this specification is an optimization method proposed for the characteristics of large number multiplication used in cryptography (such as the length of large numbers, the modulus in the calculation process, etc.). It can be understood that if large number multiplication in other fields has similar computational characteristics to the large number multiplication commonly used in cryptography, the method shown in this specification can also be used to optimize large number multiplication.

[0039] like Figure 2 As shown, Figure 2 This specification shows a flowchart of a compilation processing method for optimizing the execution of multiplication functions, including:

[0040] Step 201: The front-end module extracts the large number multiplication function from the high-level language code and converts the large number multiplication function into IR code according to the preset compilation template.

[0041] The IR code indicates that the segment multiplication function is called multiple times and the results of each segment multiplication function are accumulated; the segment multiplication function is used to perform the multiplication of two data segments of a preset length, the data segments being obtained by segmenting the parameters of the large number multiplication function.

[0042] The compiler described in this specification employs a front-end-IR-back-end architecture. The front-end module is responsible for converting the large number multiplication function code from the high-level language into IR code.

[0043] Large number multiplication functions are functions in high-level languages ​​that encapsulate large number multiplication operations, such as Mul(). High-level languages ​​are programming languages ​​closer to natural languages, such as C. Compared to methods in related technologies, the method in this specification eliminates the need to write implementation code for large number multiplication in a high-level language. In the high-level language program code, the large number multiplication function Mul(A,B) can be directly called to multiply two large integers. The parameters of this large number multiplication function can include the two integers A and B to be multiplied.

[0044] Compilation templates are pre-written IR codes that can be used for large number multiplication functions. Compilation templates can directly and easily convert large number multiplication functions of high-level languages ​​into IR codes.

[0045] The specific length of the data segment Ns can be determined based on the specifications of the accelerator. Since different accelerator devices have different optimal bit widths for parallel computation and can handle different numbers of parallel calculations simultaneously, the specific length of the data segment can be determined based on the specifications of different accelerator devices to achieve a better acceleration effect.

[0046] The integer multiplication process embodied in the IR code can be based on the following logic: First, the integers A and B to be operated on by the large number multiplication function Mul can be divided into multiple data segments, SegA[i] and SegB[j]. Then, segment multiplication is performed between the data segments from the two integers respectively to obtain the segment multiplication result. The segment multiplication results are then accumulated to obtain the final integer multiplication result. The specific implementation of the segment multiplication is encapsulated in the segment multiplication function UNIT_MUL, which facilitates the backend to independently optimize the parallelization of segment multiplication.

[0047] To obtain the final calculation result using the accumulation of segmented multiplication, methods such as simulated long multiplication and divide-and-conquer can be employed. For example, when implementing the logic of simulated long multiplication, nested double loops can be used to implement large number multiplication. Specifically, the outer loop iterates through each segment of the integer value of the large number multiplication parameter, while the inner loop accumulates the intermediate results calculated by the segmented multiplication function, thus completing the multiplication calculation by simulating long multiplication.

[0048] Using the method described above, large number multiplication functions in high-level languages ​​can be transformed into a series of segmented multiplication function calls. This allows the front-end to manage various high-level parameters without needing to concern itself with the complex parallelization strategies implemented in the back-end. The high-level parameters mentioned here refer to variables defined by specific cryptographic algorithms when writing cryptographic code in the application layer's high-level language code.

[0049] Furthermore, in addition to taking the large number multiplication function as input, the front-end can also identify the bit length of the integer in the large number multiplication function parameters and use the bit length of the integer as an input parameter to the front-end module. The bit length can affect the number of times the loop is executed. After the bit length is input to the front-end module, it can then determine how many data segments the integer needs to be divided into, thereby generating IR code that is compatible with the integer bit length.

[0050] Furthermore, in the field of cryptography, the large number multiplication required may not be limited to the multiplication of two large numbers; it may also utilize various multiplication variants, such as exponential functions, Montgomery modular multiplication, and so on. The front-end can further optimize these multiplication variants.

[0051] For example, the front-end module can determine the multiplication variant form corresponding to the large number multiplication function based on the encryption method implemented by calling the large number multiplication function in the high-level language code; and determine the compilation template corresponding to the multiplication variant form from the template library as the preset compilation template.

[0052] Since the multiplication variants used by each encryption algorithm are fixed, the front-end can determine the specific multiplication variant that the current large number multiplication code needs to implement based on the context in the high-level language code. It can also automatically determine the corresponding compilation template based on the form of the multiplication variant used.

[0053] Furthermore, the characteristics of different multiplication variants can be utilized to optimize the compilation templates corresponding to different multiplication variants, thereby reducing the number of segment multiplication function calls in the IR code and thus reducing the number of accelerator devices.

[0054] This section will use exponentiation, Montgomery modular multiplication, and constant multiplication as examples to illustrate the optimizations involved in multiplication variants.

[0055] First, for multiplication variants with redundant calculations, redundant calculations can be removed in the IR code.

[0056] For example, in the case where the multiplication variant is exponentiation, the preset compilation template instructs that the first and second data segments of the multiplier be processed using the segment multiplication function, and the result is reused as the result of multiplying the second data segment by the first data segment.

[0057] Specifically, exponentiation can also be called exponentiation. In the calculation process, exponentiation can be broken down into several square operations to save redundant calculations. For example, to calculate A to the power of 8, you can first calculate A squared, then calculate the square of A squared, and so on, until you get A to the power of 8.

[0058] This involves squaring operations. Assume the large number multiplication requires calculating two data points, A and B, which are split into multiple data segments, labeled segA[i] and segB[i]. For squaring, segA[i] and segB[i] are identical; correspondingly, segA[i] * segB[j] is equivalent to segA[j] * segB[i]. Therefore, the segment multiplication result can be reused; that is, the result of the operation on the first and second data segments can be reused as the result of multiplying the second and first data segments. This reduces the number of hardware instructions called and improves the computational efficiency of the acceleration device.

[0059] For example, in the case of a multiplication variant of Montgomery modular multiplication, the preset compilation template indicates that the segment multiplication function is performed only on specific bits in the parameters of the large number multiplication, where the specific bits are the first few high bits or the first few low bits.

[0060] For Montgomery modular multiplication, it generally includes multiplication that only calculates the lower digits (Multiply-low) and multiplication that only calculates the higher digits (Multiply-high). For example, when multiplying two 8-digit numbers, multiplication that only calculates the lower digits takes the lower 8 bits of the result, while multiplication that only calculates the higher digits takes the higher 8 bits of the result. For these multiplications, segment multiplication that is not needed in the result can be omitted.

[0061] Specifically, for multiplications that only calculate the lower-order bits, the result is the sum of the results of several segmented multiplication functions that affect the lower-order bits; that is, the sum of several lower-order operation results of the parameters. Other segmented multiplication functions can be removed from the IR code. For example, if the result of multiplying the first and second data segments is used to calculate the sum of the higher-order bits, then the segmented multiplication function for multiplying the first and second data segments can be omitted from the IR code.

[0062] For multiplication that only calculates the higher-order bits, since carry may affect the result of the higher-order operations, we can analyze whether the lower-order operations will produce carry that affects the result of the higher-order operations based on the number of 0s in the two parameters involved in the large number multiplication function, and based on this, only calculate the segment multiplication function used to accumulate the higher-order bits in the result.

[0063] Secondly, in the field of cryptography, some large number multiplications involve parameters with fixed values. Therefore, these fixed constant values ​​can be written into the corresponding IR code or stored in constant memory to reduce data access to accelerator devices and reduce the use of on-chip storage space for storage cache.

[0064] Using the compilation template described above, along with various parameters that the front-end module may require, IR code adapted to the bit length of the integer and the multiplication variant used can be generated.

[0065] Furthermore, the functionalities implemented by the various modules of the compiler in this application can be integrated as dialects into a Multi-Level Intermediate Representation (MLIR). MLIR provides an extensible compiler framework. A dialect is a variant of an IR language that allows the definition of new operations, properties, and types. By integrating the aforementioned compiler as a dialect into MLIR, high-level parameters and backend architectural details can be decoupled more efficiently, achieving the objectives of the method described in this specification.

[0066] Step 203: The backend module converts the segment multiplication function in the IR code into hardware instructions suitable for accelerator execution.

[0067] After obtaining the IR code, it can be converted into machine code executable by the accelerator device. For segmented multiplication functions, this needs to be converted into corresponding hardware instructions suitable for accelerator execution. For example, in a CUDA GPU-accelerated environment, this can be directly executed as a kernel function. In the case of an FPGA accelerator, it can be converted into assembly instruction code that the FPGA can directly execute. These hardware instructions can be parameterized. For example, on a GPU platform, various parameters in the kernel function can be adjusted to adapt to different hardware. For instance, the workload of each thread can be adjusted, as can the number of threads working in parallel.

[0068] Specifically, the backend module can convert the segment multiplication function into hardware instructions based on the accelerator's specification parameters. These hardware instructions are transmitted via a first number N. T The computation is performed by multiple threads executing in parallel.

[0069] Specifically, hardware instructions adapted to each accelerator can be generated based on its specifications. Furthermore, the generated hardware instructions fully utilize the parallel capabilities of the accelerator devices, with the hardware instructions consisting of N... T Several threads execute in parallel. Furthermore, N T The size can be determined based on the specifications of the accelerator device. In the case of a GPU accelerator, its specifications can be obtained using GPU info.

[0070] In addition to the optimization methods mentioned above, hardware instructions can also be optimized during the backend hardware platform code generation process to achieve better parallelism and improve execution efficiency. The optimization of hardware instructions will be explained below.

[0071] First, optimize the parallelization strategy.

[0072] like Figure 3 As shown, Figure 3 This is a schematic diagram of a computation graph. A computation graph can represent the execution of hardware instructions, and it allows for the analysis of factors affecting the parallel speed of hardware instructions. Figure 3 In this code, each aibj represents a word multiplication operation. A word can be 32 bits of data, and the length of a specific word can vary depending on the specifications of the accelerator device. The two parameters of the large number multiplication function are data segments A and B, where ai represents the words in a specific data segment of parameter A, and bj represents the words in a specific data segment of parameter B.

[0073] Furthermore, the arrows between the aibj elements represent the accumulation of intermediate results obtained from wide-multiply instructions, indicating the data flow during the accumulation process. The yellow outline represents the workload of each thread, that is, the area in the computation graph occupied by the parallel work handled by each thread. Intersections between the arrows and the yellow outlines indicate the need for cross-thread communication.

[0074] Related technologies include, for example Figure 4 The four parallel strategies shown will be combined in the following steps. Figure 4 The computation graph is used to analyze the four parallel strategies.

[0075] Figure 4 The parallel strategy shown in (a) is that each thread is responsible for one word multiplication operation. This requires a large number of threads, each allocated some resources, which leads to the consumption of more on-chip resources and more communication overhead between threads. Moreover, a large number of threads will bring more initialization overhead, and the small workload of each thread is insufficient to offset the overhead of initialization threads.

[0076] Figure 4 The parallel strategy shown in (b) is that each thread is responsible for calculating a single bit in the result of a hardware instruction. While this reduces communication between threads, different threads handle different workloads. Some threads perform only one word multiplication operation, while others need to perform more. Since these threads execute in parallel, this leads to warp divergence, affecting the accelerator's resource utilization.

[0077] Figure 4 The parallel strategy shown in (c) is: N T The number is 1, meaning one thread is responsible for executing one hardware instruction. While this reduces thread bundle divergence, on-chip resource consumption, and communication between threads, it lowers the level of parallelism and reduces loop unrolling.

[0078] Figure 4 The parallel strategy shown in (d) is a one-bit parallelization strategy. That is, each thread is responsible for calculating one or several rows in the graph. Figure 4 (Example using a single line). This approach can balance the factors mentioned above, such as the impact of on-chip resource consumption, parallelization level, and inter-thread communication on computational efficiency.

[0079] In addition, Figure 4 In addition to the parallelization strategy in (d) above, this specification also proposes a two-dimensional parallelization strategy, such as... Figure 5As shown. In this strategy, each thread is responsible for a rectangular area. The range of this rectangle includes N... b1 ×N b2 Multiplication by a single character. The communication overhead between threads is close to N. b1 +N b2 According to the AM-GM inequality, when N b1 =N b2 This approach minimizes communication overhead. In other words, having each thread manage a single square area yields the best results.

[0080] In other words, Figure 5 The hardware instructions corresponding to the computational graph shown indicate that: the N T Each thread executes the first operation in parallel, obtaining several intermediate results. The first operation performed by each thread includes calculating the word multiplication operation within the rectangular range in the diagram, and accumulating the word multiplication results within the rectangular range. The words involved in the word multiplication operation include a preset number of bytes in the data segment. A single thread performs a cross-thread intermediate result accumulation operation to obtain the segment multiplication result.

[0081] Compared to Figure 4 The proposed solution Figure 5 The illustrated two-dimensional parallelization strategy can further balance various factors affecting parallel speed, such as on-chip resource usage, cross-thread communication overhead, degree of parallelism, workload balancing, and memory access patterns. Specifically, the number of threads compared to... Figure 4 Scheme (a) requires fewer threads and avoids excessive resource consumption due to excessive thread allocation. It also guarantees a certain degree of parallelism. Some data exchange occurs within a thread, while some occurs between threads, compared to... Figure 4 Scheme (d) reduces cross-thread communication overhead, thus better balancing the various factors affecting parallel speed.

[0082] also, Figure 5 In the scheme shown, the workload of different threads can be the same, which makes the workload of different threads basically the same and better avoids the problem of thread bundle divergence.

[0083] exist Figure 5 In the scheme shown, N T The size is affected by the size of the data segment, N b1 and N b2 The size of the data segment is a factor, therefore the preset length Ns of the data segment can be determined based on the accelerator specification parameters. In N... b1 =N b2 In this case, based on the accelerator specification parameters, the suitable workload edge length Nb for each thread is determined. Then, the number of threads allocated to each edge in the computation graph, TPS = Ns / Nb, can be calculated. Therefore, N...T The size is the square of TPS.

[0084] Second, carry delay.

[0085] Carry may occur during each word multiplication operation, and each accumulation of carry incurs additional cross-thread communication overhead. Therefore, to reduce the communication overhead caused by carry accumulation, the first operation performed by each thread during hardware instruction execution also includes storing the carry from the word multiplication result into the register corresponding to that thread. The accumulation operation includes: a single thread summing the first result of the intermediate result accumulation with the carry stored in each register.

[0086] In other words, during word multiplication, the carry is first stored in a register without accumulation. After all accumulations are complete, the carry stored in the register is summed with the first accumulated result to obtain the final hardware instruction result. Carry accumulation can be achieved through a warp data shuffle operation.

[0087] Moreover, carry is generally an infrequent and small amount of data, which reduces communication-intensive carry propagation without consuming too many on-chip resources.

[0088] Third, customized storage strategies.

[0089] Specifically, during the execution of the hardware instructions, the data segment is stored in a register, and the intermediate results generated by the word multiplication operation are stored in shared memory.

[0090] First, considering irregular access patterns, data segments can be stored in registers instead of shared memory. This avoids bank conflicts and non-coalesced memory access that can occur when data is stored in shared memory under irregular access patterns.

[0091] In addition, when storing data segments into registers, the data can be stored in shared memory first, and then the data in shared memory can be stored in registers, which can reduce global memory accesses.

[0092] Secondly, intermediate results from word multiplication can be transferred via shared memory instead of thread shuffling. Since the data segment is stored in registers, intermediate results can be stored in other on-chip resources besides registers, thus balancing peak usage across different on-chip resources. Furthermore, this choice is also necessary when using index transposition due to the complex memory access patterns it introduces.

[0093] Fourth, index transposing.

[0094] Different words in the result of hardware instruction operations require the accumulation of different numbers of word multiplication results. For example, the last digit of a segment multiplication result may only need to be obtained from one word multiplication result, while the second to last digit may need to be obtained by accumulating two word multiplication results. While efficient initial task allocation can prevent thread bundle divergence during word multiplication operations, it cannot be prevented during global accumulation. To address this issue, index transposition is performed after the word multiplication operation ends and before accumulation.

[0095] Before index transpose, N T Each thread is responsible for executing hardware instructions, and each thread is assigned as follows: Figure 5 The workload is shown. After index transpose, only Nb threads are responsible for executing hardware instructions, and each thread manages Nb columns of data. As long as... Transposed indexes can effectively reduce thread bundle divergence caused by global accumulation.

[0096] Corresponding to the embodiments of the foregoing methods, this specification also provides embodiments of the apparatus and the computer equipment to which it is applied.

[0097] like Figure 6 As shown, Figure 6 This specification is a block diagram illustrating a compiler processing apparatus for optimizing the execution of multiplication functions according to an exemplary embodiment. The apparatus is applied to a compiler and includes:

[0098] The front-end module 610 is used to extract large number multiplication functions from high-level language code and convert the large number multiplication functions into intermediate expression (IR) code according to a preset compilation template. The IR code indicates that a segment multiplication function is called multiple times and the results of each segment multiplication function are accumulated. The segment multiplication function is used to perform the multiplication of two data segments of a preset length, and the data segments are obtained by segmenting the parameters of the large number multiplication function.

[0099] The backend module 620 is used to convert the segment multiplication function in the IR code into hardware instructions suitable for execution by the accelerator.

[0100] In an optional embodiment, the front-end module 610 is further configured to determine the multiplication variant form corresponding to the large number multiplication function based on the encryption method implemented by calling the large number multiplication function in the high-level language code; and to determine the compilation template corresponding to the multiplication variant form from the template library as the preset compilation template.

[0101] In one optional embodiment, the multiplication variant is an exponentiation; the preset compilation template indicates that the first and second data segments of the multiplier are processed using the segment multiplication function, and the result is reused as the result of multiplying the second data segment and the first data segment.

[0102] In an alternative embodiment, the multiplication variant is a Montgomery modular multiplication, and the preset compilation template indicates that the segment multiplication function is performed only on specific bits in the parameters of the large number multiplication, wherein the specific bits are the first few high bits or the first few low bits.

[0103] In one alternative embodiment, the preset length is determined based on the specifications of the accelerator.

[0104] In an optional embodiment, the backend module 620 is specifically used to convert the segment multiplication function into hardware instructions based on the specification parameters of the accelerator. The hardware instructions are executed in parallel by a first number of NT threads to perform the operation.

[0105] In an optional embodiment, the hardware instruction instructs: the NT threads to perform a first operation in parallel, respectively obtaining several intermediate results; the first operation performed by each thread includes calculating a word multiplication operation within a rectangular area in the diagram, and accumulating the word multiplication results within the rectangular area; the words involved in the word multiplication operation include a preset number of bytes in the data segment; a single thread performs a cross-thread intermediate result accumulation operation to obtain a segment multiplication result.

[0106] In an optional embodiment, the first operation performed by each thread further includes storing the carry of the word multiplication result into the register corresponding to that thread; the accumulation operation includes: a single thread summing the first result of the accumulation of the intermediate results with the carry stored in each register.

[0107] In one optional embodiment, during the execution of the hardware instructions, the data segment is stored in a register, and the intermediate results generated by the word multiplication operation are stored in shared memory.

[0108] The specific implementation process of the functions and roles of each module in the above device can be found in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0109] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of the solution in this specification according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0110] like Figure 7 As shown, Figure 7 The diagram illustrates a hardware structure of a computer device used by the aforementioned compiler. This device may include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, memory 1020, input / output interface 1030, and communication interface 1040 are internally connected to each other via the bus 1050.

[0111] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification. The processor implements the above-described methods by running executable instructions.

[0112] The memory 1020 for storing processor-executable instructions can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1020.

[0113] The input / output interface 1030 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components within the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touchscreens, microphones, various sensors, etc., while output devices may include displays, speakers, vibrators, indicator lights, etc.

[0114] The communication interface 1040 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0115] Bus 1050 includes a pathway for transmitting information between various components of the device, such as processor 1010, memory 1020, input / output interface 1030, and communication interface 1040.

[0116] It should be noted that although the above-described device only shows the processor 1010, memory 1020, input / output interface 1030, communication interface 1040, and bus 1050, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0117] This specification also provides a computer program product that, when executed by a processor, implements the above-described compilation processing method for optimizing the execution of multiplication functions.

[0118] This specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described compilation processing method for optimizing the execution of multiplication functions.

[0119] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0120] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0121] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0122] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

Claims

1. A compilation processing method for optimizing the execution of multiplication functions, applied to a compiler, the compiler including a front-end module and a back-end module; the method includes: The front-end module extracts large number multiplication functions from high-level language code and converts the large number multiplication functions into intermediate representation (IR) code according to a preset compilation template. The IR code indicates that the segment multiplication function is called multiple times and the results of each segment multiplication function are accumulated; the segment multiplication function is used to perform the multiplication of two data segments of a preset length, the data segments being obtained by segmenting the parameters of the large number multiplication function; the large number multiplication function is a function in a high-level language that encapsulates the large number multiplication operation; The backend module converts the segment multiplication function in the IR code into hardware instructions suitable for accelerator execution. The backend module converts the segment multiplication function in the IR code into hardware instructions suitable for accelerator execution, including: The backend module converts the segment multiplication function into hardware instructions based on the accelerator's specification parameters. These hardware instructions are transmitted via a first number N. T The computation is performed by multiple threads executing in parallel. The hardware instructions indicate: The N T Each thread executes the first operation in parallel, obtaining several intermediate results. The first operation performed by each thread includes calculating Nb×Nb word multiplication operations within the rectangular area of ​​the graph, and accumulating the results of the word multiplication operations within the rectangular area. The words involved in the word multiplication operations include a preset number of bytes in the data segment. Nb is determined according to the accelerator specification parameters. A single thread performs the accumulation operation of intermediate results across threads to obtain the segment multiplication result.

2. The method according to claim 1, further comprising: The front-end module determines the multiplication variant form corresponding to the large number multiplication function based on the encryption method implemented by calling the large number multiplication function in the high-level language code; Then, the compilation template corresponding to the multiplication variant form is determined from the template library and used as the preset compilation template.

3. The method according to claim 2, wherein, The multiplication variant is an exponentiation; the preset compilation template indicates that the first and second data segments of the multiplier are processed using the segment multiplication function, and the result is reused as the result of multiplying the second data segment and the first data segment.

4. The method according to claim 2, wherein, The multiplication variant is the Montgomery modular multiplication, and the preset compilation template indicates that the segment multiplication function is performed only on specific bits in the parameters of the large number multiplication, where the specific bits are the first few high bits or the first few low bits.

5. The method according to claim 1, wherein, The preset length is determined based on the specifications of the accelerator.

6. The method according to claim 1, wherein, The first operation performed by each thread also includes storing the carry of the word multiplication result into the register corresponding to that thread; The accumulation operation includes: a single thread summing the first result of the intermediate results with the carry stored in each register.

7. The method according to claim 1, wherein, During the execution of the hardware instructions, the data segment is stored in a register, and the intermediate results generated by the word multiplication operation are stored in shared memory.

8. A compiler processing apparatus for optimizing the execution of multiplication functions, the apparatus comprising: The front-end module is used to extract large number multiplication functions from high-level language code and convert the large number multiplication functions into intermediate representation (IR) code according to a preset compilation template. The IR code indicates that the segment multiplication function is called multiple times and the results of each segment multiplication function are accumulated; the segment multiplication function is used to perform the multiplication of two data segments of a preset length, the data segments being obtained by segmenting the parameters of the large number multiplication function; the large number multiplication function is a function in a high-level language that encapsulates the large number multiplication operation; The backend module is used to convert the segment multiplication function in the IR code into hardware instructions suitable for execution by the accelerator; The backend module is specifically used to convert the segment multiplication function into hardware instructions based on the accelerator's specification parameters. These hardware instructions are transmitted via a first number N. T The computation is performed by multiple threads executing in parallel; wherein, the hardware instructions indicate that the N T Each thread executes the first operation in parallel, obtaining several intermediate results. The first operation executed by each thread includes calculating Nb×Nb word multiplication operations within the rectangular area of ​​the graph, and accumulating the results of the word multiplication operations within the rectangular area. The word involved in the word multiplication operation includes a preset number of bytes in the data segment; Nb is determined according to the accelerator specification parameters; a single thread performs an accumulation operation of intermediate results across threads to obtain the segment multiplication result.

9. A computer program product, which, when executed by a processor, implements the method as described in any one of claims 1-7.

10. A computer device, comprising: processor; Memory used to store processor-executable instructions; The processor implements the method as described in any one of claims 1-7 by executing the executable instructions.

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