Pixel

Abstract

Disclosed is a pixel including: a light emitting element connected between a first power line and a second power line; a first transistor connected between the first power line and a first electrode of the light emitting element, and having a gate electrode connected to a first node; a second transistor connected between the data line and the second node, and having a gate electrode electrically connected to the first scan line; a third transistor connected between the second node and a third node, and having a gate electrode electrically connected to the first light emission control line; and a first capacitor connected between the first node and the third node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0104899 filed in the Korean Intellectual Property Office on August 10, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a pixel and a display device including the pixel. Background Art

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information has become prominent. Therefore, display devices such as liquid crystal display devices and organic light emitting diode display devices have been increasingly used.

[0005] A display device uses pixels to display images. Summary of the invention

[0006] The pixel of the display device may include a P-type transistor and an N-type transistor for high-speed operation and leakage current prevention, respectively. When the P-type transistor is used as a switching transistor for supplying a data signal, the leakage current may increase. In addition, when the N-type transistor is used as a switching transistor, the data signal may not be fully supplied within the desired time (e.g., one horizontal period).

[0007] The embodiments may provide a pixel capable of stably supplying a data signal while minimizing a leakage current, and a display device including the pixel.

[0008] An embodiment of a pixel includes: a light-emitting element connected between a first power line and a second power line; a first transistor connected between the first power line and a first electrode of the light-emitting element and having a gate electrode connected to a first node; a second transistor connected between a data line and a second node and having a gate electrode electrically connected to a first scan line; a third transistor connected between the second node and a third node and having a gate electrode electrically connected to a first light-emitting control line; and a first capacitor connected between the first node and the third node.

[0009] According to an embodiment, the second transistor may be a P-type transistor, and the third transistor may be an N-type transistor.

[0010] According to an embodiment, the second transistor may be a polysilicon semiconductor transistor, and the third transistor may be an oxide semiconductor transistor.

[0011] According to an embodiment, the second transistor may be turned on after the third transistor is turned on, and the third transistor may be turned off after the second transistor is turned off.

[0012] According to an embodiment, the first driving power may be supplied to the first power line, and the second driving power having a voltage value lower than that of the first driving power may be supplied to the second power line.

[0013] According to an embodiment, the pixel may further include: a fourth transistor connected between the second node and a third power line supplied with a reference power, and having a gate electrode electrically connected to the second scan line; a fifth transistor connected between the first transistor and the first electrode of the light-emitting element, and having a gate electrode electrically connected to the first light-emitting control line; and a second capacitor connected between the first power line and the third node.

[0014] According to an embodiment, the fourth transistor may be an N-type transistor, and the fifth transistor may be a P-type transistor.

[0015] According to an embodiment, the third transistor and the fifth transistor may be alternately turned on and off.

[0016] According to an embodiment, the pixel may further include: a sixth transistor, connected between the first node and a common node between the first transistor and the fifth transistor, and having a gate electrode electrically connected to the second scan line; a seventh transistor, connected between the first node and a fourth power line supplied with a first initialization power, and having a gate electrode electrically connected to the third scan line; an eighth transistor, connected between the first power line and the first transistor, and having a gate electrode connected to the second light-emitting control line; a ninth transistor, connected between the first electrode of the light-emitting element and the fifth power line supplied with the second initialization power, and having a gate electrode electrically connected to the fourth scan line; and a tenth transistor, connected between the common node between the eighth transistor and the first transistor and the sixth power line supplied with a bias power, and having a gate electrode electrically connected to the fourth scan line.

[0017] According to an embodiment, the eighth transistor, the ninth transistor, and the tenth transistor may be P-type transistors, and the sixth transistor and the seventh transistor may be N-type transistors.

[0018] An embodiment of a display device includes: a scan driver for driving a first scan line, a second scan line, a third scan line and a fourth scan line; a data driver for driving a data line; a light-emitting driver for driving a first light-emitting control line and a second light-emitting control line; a pixel, which is arranged to be connected to the first scan line, the second scan line, the third scan line, the fourth scan line, the data line, the first emission control line and the second emission control line, wherein a first pixel arranged at an i-th (i is a natural number greater than 0) horizontal line and a j-th (j is a natural number greater than 0) vertical line includes: a light-emitting element connected between a first power line and a second power line; a first transistor connected between the first power line and a first electrode of the light-emitting element and having a gate electrode connected to a first node; a second transistor connected between the j-th data line and a second node and turned on when an enabled first scan signal is supplied to the i-th first scan line; a third transistor connected between the second node and a third node and turned on when a disabled first emission control signal is supplied to the i-th first emission control line; and a first capacitor connected between the first node and the third node.

[0019] According to an embodiment, the second transistor may be a P-type transistor, and the third transistor may be an N-type transistor.

[0020] According to an embodiment, the second transistor may be a polysilicon semiconductor transistor, and the third transistor may be an oxide semiconductor transistor.

[0021] According to an embodiment, the first pixel may further include: a fourth transistor, connected between the second node and the third power line, and turned on when the enabled second scan signal is supplied to the i-th second scan line; a fifth transistor, connected between the first transistor and the first electrode of the light-emitting element, and turned on when the enabled first light-emitting control signal is supplied to the i-th first light-emitting control line; and a second capacitor, connected between the first power line and the third node.

[0022] According to an embodiment, the third transistor and the fifth transistor may be alternately turned on and off.

[0023] According to an embodiment, the first pixel may further include: a sixth transistor, connected between the first node and a common node between the first transistor and the fifth transistor, and turned on when the enabled second scan signal is supplied to the i-th second scan line; a seventh transistor, connected between the first node and the fourth power line, and turned on when the enabled third scan signal is supplied to the i-th third scan line; an eighth transistor, connected between the first power line and the first transistor, and turned on when the enabled second light-emitting control signal is supplied to the i-th second light-emitting control line; a ninth transistor, connected between the first electrode of the light-emitting element and the fifth power line, and turned on when the enabled fourth scan signal is supplied to the i-th fourth scan line; and a tenth transistor, connected between the common node between the eighth transistor and the first transistor and the sixth power line, and turned on when the enabled fourth scan signal is supplied to the i-th fourth scan line.

[0024] According to an embodiment, the fifth transistor, the eighth transistor, the ninth transistor, and the tenth transistor may be P-type transistors, and the fourth transistor, the sixth transistor, and the seventh transistor may be N-type transistors.

[0025] According to an embodiment, the i-th third scan line may be set to the i-1-th second scan line disposed on a previous horizontal line, and the i-th fourth scan line may be set to the i+1-th first scan line disposed on a next horizontal line.

[0026] According to an embodiment, the display device may further include a power supply unit for supplying a first driving power to the first power line, a second driving power to the second power line, a reference power to the third power line, a first initialization power to the fourth power line, a second initialization power to the fifth power line, and a bias power to the sixth power line.

[0027] According to an embodiment, the first driving power may be set to a voltage higher than that of the second driving power, and the first initialization power and the second initialization power may be set to voltages lower than that of the first driving power.

[0028] According to the pixel and the display device including the same according to the embodiment, a data signal is transmitted to the pixel using a P-type transistor and an N-type transistor, thereby stably supplying the data signal and minimizing leakage current.

[0029] However, it should be understood that the effects of the present disclosure are not limited to the above-mentioned effects, and various changes and modifications may be made without departing from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The figure shows an embodiment of a display device.

[0031] Figure 2 The diagram shows Figure 1 An embodiment of a scan driver and a light emitting driver is shown in FIG.

[0032] Figure 3 The diagram shows Figure 1 An embodiment of a pixel is shown in FIG.

[0033] Figure 4 The diagram shows Figure 3 0 is a timing diagram of an embodiment of a pixel driving method shown in FIG.

[0034] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E The diagram shows Figure 4 The timing diagram corresponds to the pixel operation process diagram.

[0035] Figure 6 The diagram shows Figure 1 An embodiment of a pixel is shown in FIG.

[0036] Figure 7 The diagram shows Figure 1 An embodiment of a scan driver and a light emitting driver is shown in FIG. DETAILED DESCRIPTION

[0037] Hereinafter, with reference to the accompanying drawings, various embodiments of the present disclosure will be described in detail so that those skilled in the art can easily implement the present disclosure. The present disclosure can be embodied in many different forms and is not limited to the embodiments described herein.

[0038] In order to clearly illustrate the present disclosure, parts not related to the description are omitted, and the same reference numerals are given to the same or similar constituent elements throughout the specification. Therefore, the above reference numerals may be used in other drawings.

[0039] In addition, the expression "same" in the description may mean "substantially the same". That is, it may be the same degree as that which can be believed by a person of ordinary skill in the art. Other expressions may also be expressions in which "substantially" is omitted.

[0040] As used herein, the term "or" means a logical "or", so that the expression "A, B, or C" means "A and B and C", "A and B but not C", "A and C but not B", "B and C but not A", "A but not B and not C", "B but not A and not C", and "C but not A and not B", unless the context dictates otherwise.

[0041] Some embodiments can be described in the accompanying drawings about functional blocks, units or modules. Those skilled in the art will appreciate that such blocks, units or modules are physically implemented by logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections and other electronic circuits. Semiconductor-based manufacturing techniques or other manufacturing techniques can be used to form. Blocks, units or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed in the present disclosure, and can be optionally driven by firmware or software. In addition, each block, unit or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and related circuits) that perform other functions. In addition, in some embodiments, within the scope of the concept of the present disclosure, these blocks, units or modules can be physically separated into two or more separate blocks, units or modules that interact with each other. In addition, in some embodiments, within the scope of the concept of the present disclosure, these blocks, units or modules can be physically combined into more complex blocks, units or modules.

[0042] The "connection" between two components may mean both electrical connection and physical connection, but is not necessarily limited thereto. For example, the "connection" used based on a circuit diagram may mean electrical connection, and the "connection" used based on a cross-sectional view and a plan view may mean physical connection.

[0043] Although the terms "first" and "second" etc. are used to describe various constituent elements, these constituent elements are not limited by these terms. These terms are only used to distinguish one constituent element from another constituent element. Therefore, within the technical spirit of the present disclosure, the first constituent element described below may be the second constituent element.

[0044] On the other hand, the present disclosure is not limited to the embodiments disclosed below, and can be implemented in various forms. In addition, each of the embodiments disclosed below can be implemented alone, or can be implemented in combination with at least one other embodiment.

[0045] Figure 1 The figure shows an embodiment of a display device. Figure 2 The diagram shows Figure 1 An embodiment of a scan driver and a light emitting driver is shown in FIG.

[0046] refer to Figure 1 The display device 100 according to the embodiment includes a pixel unit 110 (or panel), a timing controller 120, a scan driver 130, a data driver 140, a light emitting driver 150, and a power supply unit 160. The above configurations may be implemented as separate integrated circuits, and two or more of the above configurations may be integrated and implemented as one integrated circuit.

[0047] The pixel unit 110 may include pixels PX connected to first scan lines SL11, SL12, ... and SL1n, second scan lines SL21, SL22, ... and SL2n, third scan lines SL31, SL32, ... and SL3n, fourth scan lines SL41, SL42, ... and SL4n, data lines DL1, DL2, ... and DLm, first emission control lines (also referred to as first light-emitting control lines) EL11, EL12, ... and EL1n, second emission control lines (also referred to as second light-emitting control lines) EL21, EL22, ... and EL2n, and power lines PL1, PL2, PL3, PL4, PL5 and PL6 (where n and m are natural numbers greater than 0).

[0048] For example, the pixel PXij (see Figure 3 ) can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th fourth scan line SL4i, the i-th first emission control line EL1i, the i-th second emission control line EL2i and the j-th data line DLj (here, i is a positive integer less than or equal to n, and j is a positive integer less than or equal to m).

[0049] When the enabled first scan signal is supplied to the first scan lines SL11 to SL1n, the pixels PX may be selected in units of horizontal lines (for example, the pixels PX connected to the same scan line may be classified as one horizontal line (or pixel row)), and the pixels PX selected by the enabled first scan signal may receive a data signal from a data line (any one of DL1 to DLm) connected to the pixel. The pixel PX receiving the data signal may generate light of a predetermined brightness in response to a voltage of the data signal.

[0050] The scan driver 130 may receive a scan driving signal SCS from the timing controller 120. The scan driving signal SCS may include at least one scan start signal and a clock signal required to drive the scan driver 130. The scan driver 130 may generate a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal while shifting the scan start signal in response to the clock signal.

[0051] To this end, the scan driver 130 may include a first scan driver 132, a second scan driver 134, a third scan driver 136, and a fourth scan driver 138. Figure 2 as shown in .

[0052] The first scan driver 132 may receive the first scan start signal FLM1 and may generate a first scan signal by shifting the first scan start signal FLM1 in response to a clock signal. The first scan driver 132 may sequentially supply the first scan signal to the first scan lines SL11 to SL1n.

[0053] The second scan driver 134 may receive the second scan start signal FLM2 and may generate a second scan signal by shifting the second scan start signal FLM2 in response to the clock signal The second scan driver 134 may sequentially supply the second scan signal to the second scan lines SL21 to SL2n.

[0054] The third scan driver 136 may receive the third scan start signal FLM3 and may generate a third scan signal by shifting the third scan start signal FLM3 in response to the clock signal The third scan driver 136 may sequentially supply the third scan signal to the third scan lines SL31 to SL3n.

[0055] The fourth scan driver 138 may receive the fourth scan start signal FLM4 and may generate a fourth scan signal by shifting the fourth scan start signal FLM4 in response to the clock signal. The fourth scan driver 138 may sequentially supply the fourth scan signal to the fourth scan lines SL41 to SL4n.

[0056] The first scan signal, the second scan signal, the third scan signal, and the fourth scan signal may be set to a gate-on voltage so that the transistor included in the pixel PX may be turned on. For example, a low-level scan signal may be supplied to a P-type transistor, and a high-level scan signal may be supplied to an N-type transistor.

[0057] Thereafter, supplying an enabled first scan signal, an enabled second scan signal, an enabled third scan signal or an enabled fourth scan signal may mean that a gate-on voltage is supplied to the first scan line SL1, the second scan line SL2, the third scan line SL3 or the fourth scan line SL4 so that the transistor can be turned on.

[0058] In addition, supplying a disabled first scan signal, a disabled second scan signal, a disabled third scan signal or a disabled fourth scan signal may mean that a gate cut-off voltage is supplied to the first scan line SL1, the second scan line SL2, the third scan line SL3 or the fourth scan line SL4 so that the transistor can be cut off.

[0059] The data driver 140 may receive the output data Dout and the data driving signal DCS from the timing controller 120. The data driving signal DCS may include a sampling signal or a timing signal required to drive the data driver 140. The data driver 140 may generate a data signal based on the data driving signal DCS and the output data Dout. For example, the data driver 140 may generate an analog data signal based on the grayscale of the output data Dout. The data driver 140 may supply the data signal to the data lines DL1 to DLm in synchronization with the first scan signal.

[0060] The light emitting driver 150 may receive a light emitting driving signal (also referred to as an emission driving signal) ECS from the timing controller 120. The light emitting driving signal ECS may include a light emitting start signal and a clock signal required to drive the light emitting driver 150. The light emitting driver 150 may generate a first light emitting control signal (also referred to as a first emission control signal) and a second light emitting control signal (also referred to as a second emission control signal) while shifting the light emitting start signal in response to the clock signal.

[0061] To this end, the light emitting driver 150 may include a first light emitting driver 152 and a second light emitting driver 154. Figure 2 as shown in .

[0062] The first light emitting driver 152 may receive the first light emitting start signal EFLM1 and may generate a first light emitting control signal by shifting the first light emitting start signal EFLM1 in response to a clock signal. The first light emitting driver 152 may sequentially supply the first emission control signal to the first emission control lines EL11 to EL1n.

[0063] The second light emitting driver 154 may receive the second light emitting start signal EFLM2 and may generate a second light emitting control signal by shifting the second light emitting start signal EFLM2 in response to the clock signal The second light emitting driver 154 may sequentially supply the second light emitting control signal to the second light emitting control lines EL21 to EL2n.

[0064] Thereafter, supplying the disabled first emission control signal or the disabled second emission control signal may mean that a high voltage is supplied to the first emission control line EL1 or the second emission control line EL2 .

[0065] Thereafter, supplying the enabled first emission control signal or the enabled second emission control signal may mean that a low voltage is supplied to the first emission control line EL1 or the second emission control line EL2 .

[0066] exist Figure 2, the first light emitting driver 152 and the second light emitting driver 154 are shown to be connected to the first light emitting control line EL1 and the second light emitting control line EL2, respectively, but the embodiment is not limited thereto. For example, the first emission control line EL1 and the second emission control line EL2 may be driven by one light emitting driver.

[0067] The timing controller 120 may receive input data Din and a control signal CS from a host system through an interface. For example, the timing controller 120 may receive input data Din and a control signal CS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP) included in the host system. The control signal CS may include various signals including a clock signal.

[0068] The timing controller 120 may generate a scan driving signal SCS, a data driving signal DCS, and an emission driving signal ECS based on the control signal CS. The scan driving signal SCS, the data driving signal DCS, and the emission driving signal ECS may be supplied to the scan driver 130, the data driver 140, and the emission driver 150, respectively.

[0069] The timing controller 120 may rearrange the input data Din to match the specification of the display device 100. In addition, the timing controller 120 may correct the input data Din to generate the output data Dout, and may supply the output data Dout to the data driver 140. In an embodiment, the timing controller 120 may correct the input data Din in response to an optical measurement result measured during a process.

[0070] The power supply unit 160 may generate various power sources required to drive the display device 100. For example, the power supply unit 160 may generate first driving power VDD, second driving power VSS, reference power Vref, first initialization power Vint1, second initialization power Vint2, and bias power Vbias.

[0071] The first driving power VDD may be a power supply that supplies a driving current to the pixel PX. The second driving power VSS may be a power supply that receives a driving current from the pixel PX. During a period in which the pixel PX is set to emit light, the first driving power VDD may be set to a voltage higher than the voltage of the second driving power VSS.

[0072] The reference power Vref may be a power source for initializing a capacitor included in each pixel PX. For example, the reference power Vref may be a positive voltage. For example, the reference power Vref may have the same voltage level as the first driving power VDD, but the present disclosure is not limited thereto.

[0073] The first initialization power Vint1 and the second initialization power Vint2 may be power sources for initializing the pixel PX. For example, the first initialization power Vint1 may be power sources for initializing the driving transistor ( Figure 3 For example, the second initialization power Vint2 may be a power source for initializing the light emitting element LD (see Figure 3 )'s first electrode (or anode electrode).

[0074] The first initialization power Vint1 and the second initialization power Vint2 may be set to the same or different voltages depending on the resolution, inch, etc. of the panel. When the first initialization power Vint1 and the second initialization power Vint2 are set to the same voltage, the second initialization power Vint2 may be replaced by the first initialization power Vint1. The first initialization power Vint1 and the second initialization power Vint2 may be set to a voltage lower than the voltage of the first driving power VDD.

[0075] The bias power Vbias may be a power source for supplying a predetermined bias to the first electrode (or second electrode) of the driving transistor included in each of the pixels PX. For example, the bias power Vbias may be set to a positive voltage so that the driving transistor may be set to an on-bias state, but the present disclosure is not limited thereto. The bias power Vbias may be set to various voltages so that the characteristics of the driving transistor are constant.

[0076] The first driving power VDD, the second driving power VSS, the reference power Vref, the first initialization power Vint1, the second initialization power Vint2, and the bias power Vbias generated in the power supply unit 160 may be supplied to the first power line PL1, the second power line PL2, the third power line PL3, the fourth power line PL4, the fifth power line PL5, and the sixth power line PL6, respectively. The first power line PL1, the second power line PL2, the third power line PL3, the fourth power line PL4, the fifth power line PL5, and the sixth power line PL6 may be commonly connected to the pixel PX, but the embodiment of the present disclosure is not limited thereto.

[0077] In an embodiment, the first power line PL1 may be composed of a plurality of power lines, and each of the plurality of power lines may be connected to a different pixel PX. In an embodiment, the second power line PL2 may be composed of a plurality of power lines, and each of the plurality of power lines may be connected to a different pixel PX. In an embodiment, the third power line PL3 may be composed of a plurality of power lines, and each of the plurality of power lines may be connected to a different pixel PX. In an embodiment, the fourth power line PL4 may be composed of a plurality of power lines, and each of the plurality of power lines may be connected to a different pixel PX. In an embodiment, the fifth power line PL5 may be composed of a plurality of power lines, and each of the plurality of power lines may be connected to a different pixel PX. In an embodiment, the sixth power line PL6 may be composed of a plurality of power lines, and each of the plurality of power lines may be connected to a different pixel PX.

[0078] That is, in an embodiment of the present disclosure, the pixel PX can be connected to any one of the first power lines PL1, any one of the second power lines PL2, any one of the third power lines PL3, any one of the fourth power lines PL4, any one of the fifth power lines PL5, and any one of the sixth power lines PL6.

[0079] Figure 3 The diagram shows Figure 1 An embodiment of a pixel is shown in FIG. Figure 3 Pixels PXij disposed at the i-th horizontal line and the j-th vertical line are shown.

[0080] refer to Figure 3 , the pixel PXij according to the embodiment can be connected to the corresponding signal lines SL1i, SL2i, SL3i, SL4i, EL1i, EL2i and DLj. For example, the pixel PXij can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th fourth scan line SL4i, the i-th first emission control line EL1i, the i-th second emission control line EL2i and the j-th data line DLj. In the embodiment, the pixel PXij can be further connected to the first power line PL1, the second power line PL2, the third power line PL3, the fourth power line PL4, the fifth power line PL5 and the sixth power line PL6.

[0081] The pixel PXij according to the embodiment may include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0082] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2. For example, the first electrode (or anode electrode) of the light emitting element LD may be electrically connected to the first power line PL1 via the fifth transistor M5, the fifth node N5, the first transistor M1, the fourth node N4, and the eighth transistor M8, and the second electrode (or cathode electrode) of the light emitting element LD may be electrically connected to the second power line PL2. The light emitting element LD may generate light having a predetermined brightness in response to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0083] The light emitting element LD may be selected as an organic light emitting diode. In addition, the light emitting element LD may be selected as an inorganic light emitting diode such as a micro LED (light emitting diode) or a quantum dot light emitting diode. In addition, the light emitting element LD may be an element composed of a composite of an organic material and an inorganic material. Figure 3 , the pixel PXij is shown as including a single light emitting element LD. However, in another embodiment, the pixel PXij may include a plurality of light emitting elements LD, and the plurality of light emitting elements LD may be connected to each other in series, in parallel, or in series-parallel.

[0084] The pixel circuit may include a first transistor M1 (or a driving transistor), a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, a first capacitor C1, and a second capacitor C2.

[0085] The first electrode of the first transistor M1 may be connected to the first power line PL1 via the fourth node N4 and the eighth transistor M8, and the second electrode thereof may be connected to the first electrode of the light emitting element LD via the fifth node N5 and the fifth transistor M5. Here, "connection" includes the meaning of "electrical connection". The gate electrode of the first transistor M1 may be connected to the first node N1. The first transistor M1 may control the amount of current supplied from the first power line PL1 to the second power line PL2 via the light emitting element LD in response to the voltage of the first node N1.

[0086] The second transistor M2 may be connected between the data line DLj and the second node N2. In addition, the gate electrode of the second transistor M2 may be electrically connected to the first scan line SL1i. The second transistor M2 may be turned on when an enabled first scan signal GW (or a low voltage) is supplied to the first scan line SL1i, and may electrically connect the data line DLj and the second node N2.

[0087] The third transistor M3 may be connected between the second node N2 and the third node N3. In addition, the gate electrode of the third transistor M3 may be electrically connected to the first emission control line EL1i. The third transistor M3 may be turned on when the disabled first light emission control signal EM1 (or high voltage) is supplied to electrically connect the second node N2 and the third node N3.

[0088] The fourth transistor M4 may be connected between the second node N2 and the third power line PL3. In addition, the gate electrode of the fourth transistor M4 may be electrically connected to the second scan line SL2i. The fourth transistor M4 may be turned on when the enabled second scan signal GC (or high voltage) is supplied to the second scan line SL2i. When the fourth transistor M4 is turned on, the voltage of the reference power Vref is supplied to the second node N2.

[0089] The fifth transistor M5 may be connected between the fifth node N5 and the first electrode of the light emitting element LD. In addition, the gate electrode of the fifth transistor M5 may be electrically connected to the first light emitting control line EL1i. The fifth transistor M5 may be turned on when the enabled first light emitting control signal EM1 (or a low voltage) is supplied to the first light emitting control line EL1i, and may electrically connect the fifth node N5 and the first electrode of the light emitting element LD. The fifth transistor M5 may be alternately turned on and off with the third transistor M3. The fifth node N5 may refer to a common node between the first transistor M1 and the fifth transistor M5.

[0090] The sixth transistor M6 may be connected between the first node N1 and the fifth node N5. In addition, the gate electrode of the sixth transistor M6 may be electrically connected to the second scan line SL2i. The sixth transistor M6 may be turned on when an enabled second scan signal GC (or a high voltage) is supplied to the second scan line SL2i, and may electrically connect the first node N1 and the fifth node N5. When the sixth transistor M6 is turned on, the first transistor M1 may be diode-connected.

[0091] The seventh transistor M7 may be connected between the first node N1 and the fourth power line PL4. In addition, the gate electrode of the seventh transistor M7 may be electrically connected to the third scan line SL3i. The seventh transistor M7 may be turned on when the enabled third scan signal GI (or high voltage) is supplied to the third scan line SL3i. When the seventh transistor M7 is turned on, the voltage of the first initialization power Vint1 is supplied to the first node N1.

[0092] The eighth transistor M8 may be connected between the first power line PL1 and the fourth node N4. In addition, the gate electrode of the eighth transistor M8 may be electrically connected to the second emission control line EL2i. The eighth transistor M8 may be turned on when the enabled second light emission control signal EM2 (or low voltage) is supplied to the second light emission control line EL2i, and may electrically connect the first power line PL1 and the fourth node N4. The fourth node N4 may refer to a common node of the eighth transistor M8 and the first transistor M1.

[0093] The ninth transistor M9 may be connected between the first electrode of the light emitting element LD and the fifth power line PL5. In addition, the gate electrode of the ninth transistor M9 may be electrically connected to the fourth scan line SL4i. The ninth transistor M9 may be turned on when the enabled fourth scan signal GB (or low voltage) is supplied to the fourth scan line SL4i. When the ninth transistor M9 is turned on, the voltage of the second initialization power Vint2 is supplied to the first electrode of the light emitting element LD.

[0094] The tenth transistor M10 may be connected between the fourth node N4 and the sixth power line PL6. In addition, the gate electrode of the tenth transistor M10 may be electrically connected to the fourth scan line SL4i. The tenth transistor M10 may be turned on when the enabled fourth scan signal GB is supplied to the fourth scan line SL4i. When the tenth transistor M10 is turned on, the voltage of the bias power Vbias is supplied to the fourth node N4.

[0095] The first capacitor C1 may be connected between the first node N1 and the third node N3. The first capacitor C1 may be driven as a coupling capacitor. For example, the first capacitor C1 may change the voltage of the first node N1 in response to a change in the voltage of the third node N3. In addition, the first capacitor C1 may maintain the voltage of the first node N1 for a predetermined period (e.g., one frame period).

[0096] The second capacitor C2 may be connected between the first power line PL1 and the third node N3. The second capacitor C2 may store a voltage of the third node N3.

[0097] In an embodiment, the first transistor M1, the second transistor M2, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 may be formed as polycrystalline silicon semiconductor transistors. For example, the first transistor M1, the second transistor M2, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 may include a polycrystalline silicon semiconductor layer formed by a low temperature polycrystalline silicon (LTPS) process as an active layer (channel). In addition, the first transistor M1, the second transistor M2, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 may be P-type transistors (e.g., PMOS transistors). Accordingly, the gate-on voltage that turns on the first transistor M1, the second transistor M2, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 may be at a logic low level. Since the polycrystalline silicon semiconductor transistor has the advantage of fast response speed, it can be applied to switch elements that require fast switching.

[0098] In an embodiment, the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 may be formed by an oxide semiconductor transistor. For example, the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 may be an N-type oxide semiconductor transistor (e.g., an NMOS transistor), and may include an oxide semiconductor layer as an active layer. Accordingly, the gate-on voltage that turns on the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 may be at a logic high level.

[0099] The oxide semiconductor transistor can be processed at a low temperature and can have a charge mobility lower than that of a polysilicon semiconductor transistor. That is, the oxide semiconductor transistor can have excellent cut-off current characteristics. Therefore, when the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are formed as oxide semiconductor transistors, leakage current from the first node N1, the second node N2, and the third node N3 can be minimized, and thus the display quality can be improved.

[0100] In addition, in an embodiment, the P-type second transistor M2 and the N-type third transistor M3 may be connected in series between the data line DLj and the third node N3. That is, in an embodiment, the second transistor M2 and the third transistor M3 may be driven as switch transistors transmitting data signals.

[0101] When the P-type second transistor M2 is connected to the data line DLj, the data signal from the data line DLj can be stably transmitted to the second node N2 (and the third node N3). When the N-type third transistor M3 is connected to the third node N3, the leakage current from the third node N3 can be minimized. To this end, the third transistor M3 can be set to a conducting state before the second transistor M2 is turned on, and can be turned off after the second transistor M2 is turned off.

[0102] For example, when the third transistor M3 is removed from the pixel PXij and only the P-type second transistor M2 is included therein, display quality may be degraded due to leakage current from the third node N3.

[0103] For example, when the second transistor M2 is removed from the pixel PXij and only the N-type third transistor M3 is included therein, the voltage of the data signal from the data line DLj may not be transmitted to the third node N3 within a predetermined time (e.g., one horizontal period). In this case, the pixel PXij does not generate light of a desired brightness.

[0104] Figure 4 The diagram shows Figure 3 0 is a timing diagram of an embodiment of a pixel driving method shown in FIG.

[0105] refer to Figure 4 , one frame period may include at least one non-transmission segment NEP and at least one transmission segment EP.

[0106] During the non-emission section NEP, the disabled first emission control signal EM1 is supplied to the first emission control line EL1i. When the disabled first emission control signal EM1 is supplied to the first emission control line EL1i, the fifth transistor M5 is turned off and the third transistor M3 is turned on. When the fifth transistor M5 is turned off, the pixel PXij is set to a non-emission state.

[0107] During the first section T1 of the non-emission section NEP, the enabled third scan signal GI is supplied to the third scan line SL3i so that the seventh transistor M7 is turned on. During the first section T1, the voltage of the first node N1 may be initialized.

[0108] During the second section T2 of the non-emission section NEP, the enabled second scan signal GC is supplied to the second scan line SL2i so that the fourth transistor M4 and the sixth transistor M6 are turned on. During the second section T2, the threshold voltage of the first transistor M1 may be compensated.

[0109] During the third section T3 of the non-emission section NEP, the enabled first scan signal GW is supplied to the first scan line SL1i, so that the second transistor M2 is turned on. In addition, the disabled second light emitting control signal EM2 is supplied to the second light emitting control line EL2i, so that the eighth transistor M8 is turned off. During the third section T3, the voltage of the data signal can be supplied to the third node N3.

[0110] During the fourth section T4 of the non-emission section NEP, the enabled fourth scan signal GB is supplied to the fourth scan line SL4i, so that the ninth transistor M9 and the tenth transistor M10 are turned on. During the fourth section T4, the first electrode of the light emitting element LD may be initialized and the first transistor M1 may be set to a conduction bias state.

[0111] During the emission section EP, the enabled first emission control signal EM1 is supplied to the first emission control line EL1i, and the enabled second emission control signal EM2 is supplied to the second emission control line EL2i. Then, the fifth transistor M5 and the eighth transistor M8 are turned on so that the driving current can be supplied to the light emitting element LD.

[0112] FIG. 5A to FIG. 5E The diagram shows Figure 4 The timing diagram corresponds to the pixel operation process diagram.

[0113] refer to Figure 5A , first, during the non-emission section NEP, the disabled first emission control signal EM1 is supplied to the first emission control line EL1i, and thus, the fifth transistor M5 is turned off and the third transistor M3 is turned on.

[0114] When the fifth transistor M5 is turned off, the first transistor M1 and the light emitting element LD are electrically cut off, and therefore, the pixel PXij can be set to a non-emission state. When the third transistor M3 is turned on, the second node N2 and the third node N3 are electrically connected. The third transistor M3 can remain in a conductive state during the non-emission section NEP.

[0115] During the first section T1, the enabled third scan signal GI is supplied to the third scan line SL3i. When the enabled third scan signal GI is supplied to the third scan line SL3i, the seventh transistor M7 is turned on. When the seventh transistor M7 is turned on, the voltage of the first initialization power Vint1 is supplied to the first node N1, and thus, the first node N1 may be initialized to the voltage of the first initialization power Vint1. The voltage of the first initialization power Vint1 may be set to a voltage lower than the voltage of the first driving power VDD.

[0116] refer to Figure 5BDuring the second section T2, the enabled second scan signal GC is supplied to the second scan line SL2i. When the enabled second scan signal GC is supplied to the second scan line SL2i, the fourth transistor M4 and the sixth transistor M6 are turned on.

[0117] When the fourth transistor M4 is turned on, the voltage of the reference power Vref is supplied to the third node N3 via the second node N2 , and thus, the third node N3 (and the second node N2 ) may be initialized to the voltage of the reference power Vref.

[0118] When the sixth transistor M6 is turned on, the first node N1 and the fifth node N5 are electrically connected. When the first node N1 and the fifth node N5 are electrically connected, the first transistor M1 is diode-connected.

[0119] At the same time, during the second section T2, the enabled second emission control signal EM2 is supplied to the second emission control line EL2i, and therefore, the eighth transistor M8 remains in a turned-on state. Therefore, when the first transistor M1 is diode-connected, the voltage of the first drive power VDD can be supplied to the first node N1 from the first power line PL1 via the first transistor M1. In this case, a voltage obtained by subtracting the absolute threshold voltage of the first transistor M1 from the first drive power VDD can be applied to the first node N1.

[0120] During the second section T2, a voltage corresponding to the difference between the voltage of the reference power Vref and the voltage of the first node N1 may be stored in the first capacitor C1. For example, when the voltage of the reference power Vref is set to the same voltage as the voltage of the first driving power VDD, a voltage corresponding to the threshold voltage of the first transistor M1 may be stored in the first capacitor C1.

[0121] refer to Figure 5C , during the third section T3 , the disabled second emission control signal EM2 is supplied to the second emission control line EL2 i , and the enabled first scan signal GW is supplied to the first scan line SL1 i .

[0122] When the disabled second emission control signal EM2 is supplied to the second emission control line EL2i, the eighth transistor M8 is turned off. When the eighth transistor M8 is turned off, the electrical connection between the first power line PL1 and the fourth node N4 is blocked.

[0123] When the enabled first scan signal GW is supplied to the first scan line SL1i, the second transistor M2 is turned on. When the second transistor M2 is turned on, the voltage of the data signal is supplied to the second node N2 from the data line DLj. At this time, the voltage of the data signal is supplied to the second node N2 via the P-type second transistor M2 as a polycrystalline silicon semiconductor transistor, and therefore, can be stably supplied to the second node N2 within a predetermined time. The voltage of the data signal supplied to the second node N2 can be supplied to the third node N3 while charging the parasitic capacitor (not shown).

[0124] During the third section T3, the voltage of the third node N3 changes from the voltage of the reference power Vref to the voltage of the data signal. At this time, the change value of the voltage of the third node N3 can be transmitted to the first node N1 through the coupling of the first capacitor C1. Accordingly, during the third section T3, a voltage reflecting the voltage of the data signal and the threshold voltage of the first transistor M1 can be applied to the first node N1.

[0125] refer to Figure 5D During the fourth section T4, the disabled first scan signal GW is supplied to the first scan line SL1i, and therefore, the second transistor M2 is turned off. Even if the second transistor M2 is turned off, the third transistor M3 remains in the on state, so the voltage of the data signal transmitted to the second node N2 can be stably supplied to the third node N3. For example, during the fourth section T4, the voltage of the data signal of the second node N2 charged in the parasitic capacitor can be supplied to the third node N3.

[0126] During the fourth section T4, the enabled fourth scan signal GB is supplied to the fourth scan line SL4i. When the enabled fourth scan signal GB is supplied to the fourth scan line SL4i, the ninth transistor M9 and the tenth transistor M10 are turned on.

[0127] When the ninth transistor M9 is turned on, the voltage of the second initialization power Vint2 can be supplied from the fifth power line PL5 to the first electrode of the light emitting element LD. When the voltage of the second initialization power Vint2 is supplied to the first electrode of the light emitting element LD, the parasitic capacitor (not shown) of the light emitting element LD is discharged, and thus the black display capability can be improved.

[0128] When the tenth transistor M10 is turned on, the voltage of the bias power Vbias can be supplied from the sixth power line PL6 to the fourth node N4. When the voltage of the bias power Vbias is supplied to the fourth node N4, the first transistor M1 is initialized to a specific state (e.g., a biased on state), and thus an image with uniform brightness can be displayed.

[0129] refer to Figure 5E During the emission section EP, the enabled first emission control signal EM1 is supplied to the first emission control line EL1i, and the enabled second emission control signal EM2 is supplied to the second emission control line EL2i.

[0130] When the enabled first emission control signal EM1 is supplied to the first emission control line EL1i, the fifth transistor M5 is turned on. When the fifth transistor M5 is turned on, the first transistor M1 and the light emitting element LD are electrically connected.

[0131] When the enabled second emission control signal EM2 is supplied to the second emission control line EL2i, the eighth transistor M8 is turned on. When the eighth transistor M8 is turned on, the first power line PL1 and the first transistor M1 are electrically connected. Subsequently, a current path leading to the second power line PL2 via the first power line PL1, the first transistor M1, the fifth transistor M5 and the light emitting element LD is formed.

[0132] At this time, the first transistor M1 may control the amount of current supplied from the first power line PL1 to the second power line PL2 in response to the voltage of the first node N1, and thus, the light emitting element LD may emit light having predetermined brightness.

[0133] In an embodiment, one frame period may further include one or more non-emission sections NEP. This may be to effectively express low grayscale by reducing the emission section EP of the pixel PXij, or to smoothly blur the motion of the image. In addition, the non-emission section NEP may include multiple non-emission sections NEP, thereby driving the pixel PXij at a low driving frequency.

[0134] In the above embodiment, the voltage of the data signal can be transmitted from the data line DLj to the pixel PXij using the P-type second transistor M2 capable of high-speed driving. In addition, in an embodiment, the leakage current between the data line DLj and the pixel PXij can be prevented using the N-type third transistor M3. That is, in an embodiment, the switch transistor can be configured using the P-type second transistor M2 and the N-type third transistor M3, thereby improving the display quality.

[0135] Figure 6 The diagram shows Figure 1 An embodiment of a pixel is shown in FIG. Figure 7 The diagram shows Figure 1 The scanning driver and the light emitting driver are described in detail. Figure 6 and Figure 7 When Figure 2 and Figure 3 Duplicate description.

[0136] refer to Figure 6, the gate electrode of the seventh transistor M7 is electrically connected to the third scan line SL3i. Here, the third scan line SL3i may be the second scan line SL2i-1 disposed on the previous horizontal line. In this case, Figure 7 As shown in Figure 2 The third scan driver 136 shown in FIG. 1 is used to minimize the dead zone.

[0137] The gate electrodes of the ninth transistor M9 and the tenth transistor M10 are electrically connected to the fourth scan line SL4i. Here, the fourth scan line SL4i may be the first scan line SL1i+1 disposed on the next horizontal line. In this case, Figure 7 As shown in Figure 2 The fourth scan driver 138 shown in FIG. 1 is used to minimize the dead zone.

[0138] Although the above has been described with reference to the embodiments of the present disclosure, it will be understood by those skilled in the art that various modifications and changes may be made to the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A pixel comprising: A light emitting element connected between the first power line and the second power line; a first transistor connected between the first power line and the first electrode of the light emitting element and having a gate electrode connected to a first node; a second transistor connected between the data line and the second node and having a gate electrode electrically connected to the first scan line; a third transistor connected between the second node and the third node and having a gate electrode electrically connected to the first light emission control line; as well as The first capacitor is connected between the first node and the third node.

2. The pixel according to claim 1, wherein: The second transistor is a P-type transistor, and the third transistor is an N-type transistor.

3. The pixel according to claim 2, wherein: The second transistor is a polysilicon semiconductor transistor, and the third transistor is an oxide semiconductor transistor.

4. The pixel according to claim 1, wherein: The second transistor is turned on after the third transistor is turned on, and the third transistor is turned off after the second transistor is turned off.

5. The pixel according to any one of claims 1 to 4, wherein: First driving power is supplied to the first power line, and second driving power having a voltage value lower than that of the first driving power is supplied to the second power line.

6. The pixel according to claim 1, further comprising: a fourth transistor connected between the second node and a third power line supplied with a reference power and having a gate electrode electrically connected to the second scan line; a fifth transistor connected between the first transistor and the first electrode of the light emitting element and having a gate electrode electrically connected to the first light emission control line; as well as The second capacitor is connected between the first power line and the third node.

7. The pixel according to claim 6, wherein: The fourth transistor is an N-type transistor, and the fifth transistor is a P-type transistor.

8. The pixel according to claim 6, wherein: The third transistor and the fifth transistor are alternately turned on and off.

9. The pixel according to claim 6, further comprising: a sixth transistor connected between the first node and a common node between the first transistor and the fifth transistor and having a gate electrode electrically connected to the second scan line; a seventh transistor connected between the first node and a fourth power line supplied with the first initialization power and having a gate electrode electrically connected to the third scan line; an eighth transistor connected between the first power line and the first transistor and having a gate electrode connected to a second light emission control line; a ninth transistor connected between the first electrode of the light emitting element and a fifth power line supplied with a second initialization power and having a gate electrode electrically connected to a fourth scan line; as well as A tenth transistor is connected between a common node between the eighth transistor and the first transistor and a sixth power line supplied with bias power, and has a gate electrode electrically connected to the fourth scan line.

10. The pixel according to claim 9, wherein: The eighth transistor, the ninth transistor and the tenth transistor are P-type transistors, and The sixth transistor and the seventh transistor are N-type transistors.

Images