Silicon on insulator (SOI) wafer top silicon layer thinning method and SOI wafer
By grinding and chemical mechanical polishing processes on the top silicon layer of the SOI wafer, matching the polishing parameters according to the thickness difference value, the problem of uneven thickness of the top silicon layer of the SOI wafer is solved, and the thickness uniformity and stable device performance are improved.
Patent Information
- Application Number
- CN202411660772.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2025-02-18
AI Technical Summary
When the prior art thins the silicon on the top layer of the SOI wafer, the thickness is uneven and difficult to control, resulting in unstable device performance, inconsistent current density of local electronic channels, and uneven thermal effects.
A method for thinning the top silicon layer of the SOI wafer is provided, including grinding a top silicon layer of the SOI wafer and chemical mechanical polishing process. After the grinding process, the thickness difference between the edge region of the top silicon layer and the intermediate region is the first thickness A, and the thickness of the intermediate region is the second thickness B. Then, the chemical mechanical polishing process is matched according to the values of the first thickness A and the second thickness B, so that the thickness of the middle area of the top silicon layer after polishing is C, and B-C satisfies: 2.5A≤B-C≤10A.
Through this thinning method, the thickness uniformity of the silicon layer on the top layer of the SOI wafer can be effectively controlled, ensuring that the final thickness difference is less than 0.2μm, and improving the stability of device performance.
Smart Images
Figure CN119480634A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of semiconductor technology, and in particular to a method for thinning a top silicon layer of an SOI wafer and an SOI wafer. Background Art
[0002] Silicon on insulator (SOI) technology has become one of the mainstream products in most electronic materials fields. The core feature of this special silicon-based semiconductor manufacturing technology is to form a thin top layer of silicon on the insulator. This structure makes SOI devices perform well in many aspects, such as low power consumption, radiation resistance, and high speed. As the integration of automotive-grade SOI material on-board chips becomes higher and higher, the high uniformity of the thickness of the top silicon layer becomes particularly important.
[0003] BESOI (Bond and Etch-back SOI) technology mainly manufactures SOI wafers by bonding and thinning. First, two silicon wafers are bonded together, and then the top silicon is obtained by back thinning to form an SOI structure. The control of the thickness and uniformity of the top silicon film is the core key technology of BESOI. At present, the back grinding (Grinding) and chemical mechanical polishing (CMP) are the key processes in BESOI technology wafer manufacturing. Grinding thins the top silicon of the wafer to a certain thickness to form an SOI structure. Chemical mechanical polishing eliminates the stress damage caused by back grinding, improves the uniformity of the wafer, and obtains a wafer with high flatness and low roughness. However, when thinning the top silicon of the SOI wafer, there is a problem that the thickness is uneven and difficult to control, resulting in unstable device performance, inconsistent current density of local electron channels, uneven thermal effects, and even line width changes. Summary of the invention
[0004] The object of the present invention is to provide a method for thinning the top silicon layer of an SOI wafer and an SOI wafer, so as to solve one or more problems in the prior art.
[0005] In order to solve the above problems, the present invention provides a method for thinning the top silicon layer of a SOI wafer, comprising:
[0006] Providing an SOI wafer, wherein the SOI wafer comprises a substrate silicon layer, a buried oxide layer and a top silicon layer stacked in sequence from bottom to top;
[0007] performing a grinding process on the top silicon layer, wherein after the grinding process, the difference between the thickness of the edge region of the top silicon layer and the middle region of the top silicon layer is a first thickness A, and the middle region of the top silicon layer has a second thickness B; and
[0008] A chemical mechanical polishing process is performed on the top silicon layer. When the chemical mechanical polishing process is performed on the top silicon layer, the chemical mechanical polishing process is matched according to the values of the first thickness A and the second thickness B. After performing the chemical mechanical polishing process, the thickness of the middle area of the top silicon layer is C, and BC satisfies: 2.5A≤BC≤10A.
[0009] Optionally, in the method for thinning the top silicon layer of a SOI wafer, after the grinding process is performed, the thickness of the top silicon layer gradually decreases from the edge position to the center position and becomes concave.
[0010] Optionally, in the method for thinning the top silicon layer of a SOI wafer, the grinding process is performed using a dual-axis grinder.
[0011] Optionally, in the method for thinning the top silicon layer of a SOI wafer, when performing the chemical mechanical polishing process, a removal rate of an edge region of the top silicon layer is greater than a removal rate of a middle region of the top silicon layer.
[0012] Optionally, in the method for thinning the top silicon layer of a SOI wafer, after performing the chemical mechanical polishing process, the thickness range of the top silicon layer is less than 0.2 μm.
[0013] Optionally, in the method for thinning the top silicon layer of a SOI wafer, the thickness of the substrate silicon layer is 772 μm to 777 μm.
[0014] Optionally, in the method for thinning the top silicon layer of a SOI wafer, the composite deflection angle of the substrate silicon layer and the top silicon layer is 0.1° to 0.5°, and the thickness range is less than 0.4 μm.
[0015] Optionally, in the method for thinning the top silicon layer of a SOI wafer, the thickness of the buried oxide layer is greater than 0.2 μm and less than 2 μm.
[0016] The present invention also provides an SOI wafer, and the SOI wafer is obtained by using the method described in any of the above items.
[0017] Optionally, in the SOI wafer, the thickness range of the top silicon layer of the SOI wafer is less than 0.2 μm.
[0018] In summary, the method for thinning the top silicon layer of a SOI wafer provided by the present invention includes: providing an SOI wafer, the SOI wafer including a substrate silicon layer, a buried oxide layer and a top silicon layer stacked in sequence from bottom to top; performing a grinding process on the top silicon layer, after the grinding process, the difference in thickness between the edge region of the top silicon layer and the middle region of the top silicon layer is a first thickness A, and the middle region of the top silicon layer has a second thickness B; and performing a chemical mechanical polishing process on the top silicon layer, when performing the chemical mechanical polishing process on the top silicon layer, matching the chemical mechanical polishing process according to the values of the first thickness A and the second thickness B, after the chemical mechanical polishing process is performed, the thickness of the middle region of the top silicon layer is C, and BC satisfies: 2.5A≤BC≤10A. The thickness uniformity of the top silicon layer of the SOI wafer obtained by the thinning method provided by the present invention is effectively controlled. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 A flow chart of a method for thinning the top silicon layer of a SOI wafer provided in an embodiment of the present invention;
[0020] Figure 2 Schematic diagram of the structure corresponding to step S1 in an embodiment of the present invention;
[0021] Figure 3 Schematic diagram of the structure corresponding to step S2 in an embodiment of the present invention;
[0022] Figure 4 Schematic diagram of the structure corresponding to step S3 in an embodiment of the present invention;
[0023] Figure 5 Schematic diagram of the positions of the middle area and the edge area in an embodiment of the present invention;
[0024] The descriptions of the reference numerals are as follows:
[0025] 10-substrate silicon layer; 20-buried oxide layer; 30-top silicon layer; 40-oxide layer;
[0026] 100-middle area; 200-edge area. DETAILED DESCRIPTION
[0027] The following is a further detailed description of the SOI wafer top silicon layer thinning method and SOI wafer proposed in the present invention in conjunction with the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are all in non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis required to be shown in each drawing is different, and sometimes different proportions are used. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, for example, an element described as "above" another element will now be below the element. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third" and the like in the specification are only used to distinguish between various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between various components, elements, steps, etc.
[0028] See also Figure 1 The embodiment of the present invention provides a method for thinning the top silicon layer of an SOI wafer, comprising the following steps:
[0029] S1, providing an SOI wafer, wherein the SOI wafer comprises a substrate silicon layer, a buried oxide layer and a top silicon layer stacked in sequence from bottom to top;
[0030] S2, performing a grinding process on the top silicon layer, after which the difference in thickness between the edge region of the top silicon layer and the middle region of the top silicon layer is a first thickness A, and the middle region of the top silicon layer has a second thickness B; and
[0031] S3, performing a chemical mechanical polishing process on the top silicon layer. When performing the chemical mechanical polishing process on the top silicon layer, the chemical mechanical polishing process is matched according to the values of the first thickness A and the second thickness B. After performing the chemical mechanical polishing process, the thickness of the middle area of the top silicon layer is C, and BC satisfies: 2.5A≤BC≤10A.
[0032] The method for thinning the top silicon layer of an SOI wafer provided in an embodiment of the present invention matches the chemical mechanical polishing process according to the values of the first thickness and the second thickness when performing a chemical mechanical polishing process on the top silicon layer, so that the thickness BC of the top silicon layer removed by the chemical mechanical polishing process satisfies: 2.5A≤BC≤10A. In this way, the thickness uniformity of the final top silicon layer can be effectively controlled.
[0033] The following combination Figure 2 to Figure 4 The above steps are described in further detail.
[0034] First, execute step S1, see Figure 2 , providing an SOI wafer, the SOI wafer comprising a substrate silicon layer 10, a buried oxide layer 20 and a top silicon layer 30 stacked in sequence from bottom to top. The substrate silicon layer 10 and the top silicon layer 30 are isolated and bonded together by the buried oxide layer 20. In addition, the back side of the substrate silicon layer 10, that is, the side away from the top silicon layer 30, may also have an oxide layer 40.
[0035] The buried oxide layer 20 can be formed by performing a thermal oxidation process and / or a plasma enhanced chemical vapor deposition (PECVD) process on the surface of the substrate silicon layer 10 and / or the top silicon layer 30. In this embodiment, preferably, a highly dense silicon dioxide interface layer is first formed by a thermal dry oxygen oxidation process, and then a relatively loose silicon dioxide layer is prepared by a wet oxygen oxidation process. Preferably, the thickness of the buried oxide layer 20 formed is greater than 0.2 μm and less than 2 μm.
[0036] The diameter of the substrate silicon layer 10 and the top silicon layer 30 may be 200 mm or 300 mm, the thickness of the substrate silicon layer 10 may be 772 μm to 777 μm, the composite deflection angle of the substrate silicon layer 10 and the top silicon layer 30 is 0.1° to 0.5°, and the thickness range is less than 0.4 μm, but the present application is not limited thereto. It can be understood that the composite deflection angle represents the degree of alignment of the substrate silicon layer 10 and the top silicon layer 30 during bonding. If the deflection angle of the substrate silicon layer 10 relative to the top silicon layer 30 in the X direction is X0, and the deflection angle relative to the top silicon layer 30 in the Y direction is Y0, then the composite deflection angle is equal to (X0 2 +Y0 2 ) 1 / 2 .
[0037] In this embodiment, after the substrate silicon layer 10 and the top silicon layer 30 are bonded together, the bonding wafer may be subjected to a reinforcement heat treatment, the reinforcement temperature is 900-1250°C, the time is 0.5-3h, and the atmosphere is an oxygen- or hydrogen-containing inert gas (Ar, N2, He, etc.); and the bonding wafer may be subjected to an edge chamfering treatment and an etching treatment, the edge chamfering treatment is used to remove part of the unbonded area of the top silicon layer 30, and the edge etching treatment is used to eliminate edge damage. The SOI wafer as described in step S1 is obtained by the reinforcement heat treatment, the edge chamfering treatment, and the edge etching treatment.
[0038] Next, execute step S2, see Figure 3, a grinding process is performed on the top silicon layer 30. After the grinding process, the thickness of the edge area of the top silicon layer is greater than the thickness of the middle area of the top silicon layer, the middle area of the top silicon layer has a second thickness B, and the edge area of the top silicon layer has a third thickness D. The difference between the thickness of the edge area of the top silicon layer and the middle area of the top silicon layer is the first thickness A, A=DB.
[0039] Although "middle" and "edge" are not restrictive, it should be understood that the edge area is relative to the middle area. The middle area refers to the area passing through the center of the silicon wafer, and the edge area refers to the area on the surface of the silicon wafer excluding the middle area, and the edge area surrounds the middle area. In practical applications, the size of the area occupied by the middle area and the edge area can be defined artificially, but the relative position relationship between the two remains unchanged. As an example, Figure 5 As shown in , when the radius R of the top silicon layer 30 is 150nm, the middle area 100 may be a circular area with a radius of 10nm and an axis of the top silicon layer 30 as the center, and the edge area 200 may be a circumferential area 140nm to 147nm away from the axis of the top silicon layer 30.
[0040] Since generally, when a wafer is subjected to a grinding process, the removal rate of the middle region of the wafer is greater than the removal efficiency of the edge region, a suitable grinding process can be adopted so that after the grinding process is performed, the thickness of the top silicon layer 30 gradually decreases from the edge position to the center position and becomes concave. The concave shape of the top silicon layer 30 is helpful for controlling the morphology of the top silicon layer 30 when the top silicon layer 30 is subsequently polished. Specifically, the concave shape of the top silicon layer 30 can complement the pressure value (pressure gradually increases from the edge position to the center position) in the subsequent polishing, thereby helping to control the thickness uniformity of the top silicon layer 30.
[0041] Optionally, the grinding process is completed using a biaxial grinder, through which the removal rate of the middle area of the top silicon layer 30 can be greater than the removal rate of the edge area of the top silicon layer 30, so that the thickness of the top silicon layer 30 gradually decreases from the edge position to the center position and becomes concave. However, the present application is not limited to this, and any grinding tool that can make the top silicon layer 30 concave after grinding is within the protection scope of the present application.
[0042] Next, execute step S3, see Figure 4, a chemical mechanical polishing process is performed on the top silicon layer 30. When the chemical mechanical polishing process is performed, the removal rate of the edge region of the top silicon layer is greater than the removal rate of the middle region of the top silicon layer. In this way, the edge region of the top silicon layer 30 can be removed faster than the middle region, so that the thickness uniformity of the top silicon layer 30 can be effectively controlled.
[0043] During the polishing process, when the polishing conditions at each position of the top silicon layer 30 are the same, the pressure applied by the polishing disk to the edge area of the top silicon layer 30 is greater than the pressure applied to the middle area of the top silicon layer 30. Therefore, when the chemical mechanical polishing process is performed, the removal rate of the edge area of the top silicon layer 30 is greater than the removal rate of the middle area of the top silicon layer 30.
[0044] Assume that after the grinding process is performed, the difference in thickness between the edge region and the middle region of the top silicon layer 30 is a first thickness A, the thickness of the middle region of the top silicon layer 30 is a second thickness B, and after the chemical mechanical polishing process is performed, the thickness of the top silicon layer 30 is a third thickness C. In this embodiment, when the chemical mechanical polishing process is performed on the top silicon layer 30, the chemical mechanical polishing process is matched according to the values of the first thickness A and the second thickness B, so that the thickness BC of the top silicon layer 30 removed by the chemical mechanical polishing process satisfies: 2.5A≤BC≤10A. By performing this chemical mechanical polishing process matching, the thickness extreme difference value of the top silicon layer 30 after the chemical mechanical polishing process is performed can be less than 0.2μm, that is, the difference between the maximum thickness and the minimum thickness of the top silicon layer 30 is less than 0.2μm.
[0045] The embodiment of the present invention further provides an SOI wafer, which is obtained by using the method provided by the embodiment of the present invention. Therefore, the thickness range of the top silicon layer 30 of the SOI wafer provided by the embodiment of the present invention is less than 0.2 μm.
[0046] In a specific example, two silicon wafers are provided as a device wafer and a support wafer, respectively, so as to serve as the top silicon layer 30 and the substrate silicon layer 10 of the SOI wafer after bonding, respectively. The thickness of the support wafer is 775 μm, and the thickness extreme value (TTV) is 0.2 μm. The device wafer and the support wafer after thermal oxidation are bonded, and thermal reinforcement treatment is performed after bonding. The reinforcement temperature is 950°C and the time is 2 hours. The reinforced wafer is chamfered and edge etched to obtain an SOI wafer; the thickness extreme value (thickness difference between the edge area and the center area) of the top silicon layer 30 obtained after grinding is 1 μm, and the thickness of the center area is 8 μm. Chemical mechanical polishing is performed, and the chemical mechanical polishing process is matched according to the thickness distribution after grinding. The thickness of the center area of the top silicon layer 30 after polishing is controlled to be 3 μm, and the thickness extreme value of the top silicon layer 30 after polishing is 0.15 μm.
[0047] In another specific example, two silicon wafers are provided as a device wafer and a support wafer respectively, the thickness of the support wafer is 775um, and the TTV is 0.2μm. The device wafer and the support wafer after thermal oxidation are bonded, and then thermally reinforced at a temperature of 950°C for 2 hours. The reinforced wafer is chamfered and edge-etched. The thickness range of the top silicon layer 30 obtained after grinding is 2μm, and the thickness of the central area is 6μm; chemical mechanical polishing is performed, and the CMP process is matched according to the thickness distribution after grinding. The thickness of the top silicon center area after polishing is controlled to be 3μm, and the thickness range of the top silicon layer 30 after polishing is 0.5μm.
[0048] In another specific example, two silicon wafers are provided as a device wafer and a support wafer respectively, the thickness of the support wafer is 775μm, and the TTV is 0.2um. The device wafer and the support wafer after thermal oxidation are bonded, and thermal reinforcement treatment is performed after bonding. The reinforcement temperature is 950°C and the time is 2h. The reinforced wafer is chamfered and edge etched. The thickness range of the top silicon layer 30 obtained after grinding is 0.5μm, and the thickness of the central area is 8μm. Chemical mechanical polishing is performed, and the CMP process is matched according to the thickness distribution after grinding. The thickness of the central area of the top silicon layer 30 after polishing is controlled to be 2μm, and the thickness range of the top silicon layer 30 after polishing is 0.4μm.
[0049] In summary, the method for thinning the top silicon layer of a SOI wafer provided in an embodiment of the present invention includes: providing an SOI wafer, the SOI wafer including a substrate silicon layer, a buried oxide layer and a top silicon layer stacked in sequence from bottom to top; performing a grinding process on the top silicon layer, after the grinding process, the difference in thickness between the edge region of the top silicon layer and the middle region of the top silicon layer is a first thickness A, and the middle region of the top silicon layer has a second thickness B; and performing a chemical mechanical polishing process on the top silicon layer, when performing the chemical mechanical polishing process on the top silicon layer, matching the chemical mechanical polishing process according to the values of the first thickness A and the second thickness B, after the chemical mechanical polishing process is performed, the thickness of the middle region of the top silicon layer is C, and BC satisfies: 2.5A≤BC≤10A. The SOI wafer obtained by the thinning method provided in an embodiment of the present invention has the thickness uniformity of the top silicon layer effectively controlled.
[0050] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for thinning the top silicon layer of a SOI wafer, characterized in that: include: Providing an SOI wafer, wherein the SOI wafer comprises a substrate silicon layer, a buried oxide layer and a top silicon layer stacked in sequence from bottom to top; performing a grinding process on the top silicon layer, wherein after the grinding process, the difference between the thickness of the edge region of the top silicon layer and the middle region of the top silicon layer is a first thickness A, and the middle region of the top silicon layer has a second thickness B; and A chemical mechanical polishing process is performed on the top silicon layer. When the chemical mechanical polishing process is performed on the top silicon layer, the chemical mechanical polishing process is matched according to the values of the first thickness A and the second thickness B. After performing the chemical mechanical polishing process, the thickness of the middle area of the top silicon layer is C, and BC satisfies: 2.5A≤BC≤10A.
2. The method for thinning the top silicon layer of a SOI wafer according to claim 1, characterized in that: After the grinding process is performed, the thickness of the top silicon layer gradually decreases from the edge position to the center position and becomes concave.
3. The method for thinning the top silicon layer of a SOI wafer according to claim 1, characterized in that: The grinding process is completed using a double-axis grinding machine.
4. The method for thinning the top silicon layer of a SOI wafer according to claim 1, characterized in that: When the chemical mechanical polishing process is performed, a removal rate of the edge region of the top silicon layer is greater than a removal rate of the middle region of the top silicon layer.
5. The method for thinning the top silicon layer of a SOI wafer according to claim 1, characterized in that: After the chemical mechanical polishing process is performed, the thickness difference of the top silicon layer is less than 0.2 μm.
6. The method for thinning the top silicon layer of a SOI wafer according to claim 1, characterized in that: The thickness of the substrate silicon layer is 772 μm to 777 μm.
7. The method for thinning the top silicon layer of a SOI wafer according to claim 1, characterized in that: The composite deflection angle of the substrate silicon layer and the top silicon layer is 0.1° to 0.5°, and the thickness extreme difference is less than 0.4 μm.
8. The method for thinning the top silicon layer of a SOI wafer according to claim 1, characterized in that: The thickness of the buried oxide layer is greater than 0.2 μm and less than 2 μm.
9. A SOI wafer, characterized in that: The SOI wafer is obtained by the method according to any one of claims 1 to 8.
10. The SOI wafer according to claim 9, characterized in that: The thickness difference of the top silicon layer of the SOI wafer is less than 0.2 μm.