Message forwarding method and device, computer device, readable storage medium and program product
By hashing the source address and type of request and response messages, and selecting appropriate memory cores for processing, the problem of limited intermediate device performance is solved, and efficient message forwarding is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHINA TELECOM CLOUD TECH CO LTD
- Filing Date
- 2024-12-03
- Publication Date
- 2026-06-05
AI Technical Summary
When intermediate devices handle complex network service interactions, their performance is affected, leading to a decrease in traffic packet forwarding efficiency.
By hashing the source address information of the request message, matching memory cores are selected for processing. Appropriate memory cores are selected for processing the response message type and encrypted message, respectively, thus avoiding thread synchronization overhead and achieving parallel execution.
It improves the performance of intermediate devices and packet forwarding efficiency, avoids a single memory core becoming a bottleneck, and achieves efficient forwarding of traffic packets.
Smart Images
Figure CN119484469B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of message processing, and in particular to a message forwarding method, apparatus, computer equipment, readable storage medium, and program product. Background Technology
[0002] With the development of Internet technology, networks increasingly need to perform various business interactions to achieve resource sharing. Currently, an intermediate device is usually introduced between networks to process and forward traffic packets. For example, intranet devices often access SD-WAN (Software-Defined Wide Area Network) through EDGE (Edge Devices).
[0003] However, with the diversification of business, the interaction resources are becoming more and more complex, and the intermediate devices will require more processor resources, which will affect the performance of the intermediate devices to some extent, thereby affecting the forwarding efficiency of traffic packets. Summary of the Invention
[0004] Therefore, it is necessary to provide a message forwarding method, apparatus, computer equipment, computer-readable storage medium, and computer program product that can improve message forwarding efficiency in response to the above-mentioned technical problems.
[0005] In a first aspect, this application provides a message forwarding method, comprising: when a first object sends a request message to a second object, obtaining source address information of the request message; performing hash processing on the source address information to obtain a first hash value of the source address information; selecting a first memory core that matches the first hash value from a plurality of first candidate memory cores used for message processing of the request message; performing message processing on the request message through the first memory core to obtain a first target message, and forwarding the first target message to the second object.
[0006] In one embodiment, the method further includes: when the second object returns a response message to the first object in response to the request message, performing type identification on the response message to obtain a second message type of the response message; when the second message type is an address translation message, obtaining the target port number of the response message; selecting a second memory core that matches the target port number from a plurality of first candidate memory cores; performing message processing on the response message through the second memory core to obtain a second target message, and sending the second target message to the first object.
[0007] In one embodiment, the method further includes: when the second message type is an encrypted message, obtaining the number of memory cores among a plurality of second candidate memory cores used for message processing of the response message; selecting a third memory core from the plurality of second candidate memory cores based on the number of memory cores; decrypting the response message using the third memory core to obtain a decrypted message; hashing the target address information of the decrypted message to obtain a second hash value of the target address information; selecting a fourth memory core from the plurality of first candidate memory cores that matches the second hash value; processing the decrypted message using the fourth memory core to obtain a third target message; and sending the third target message to the first object.
[0008] In one embodiment, the request message includes at least one sub-message, and the method further includes: determining the target sub-message that is ranked first among the sub-messages; and if the target sub-message exists in the message cache list, reading the target sub-message and other sub-messages other than the target sub-message from the message cache list.
[0009] In one embodiment, the method further includes: performing business complexity analysis on the first object and the second object respectively to obtain the first business complexity of the first object and the second business complexity of the second object; determining the number of first candidate memory cores matching the first business complexity and the number of second candidate memory cores matching the second business complexity; and determining a plurality of first candidate memory cores matching the number of first candidate memory cores and a plurality of second candidate memory cores matching the number of second candidate memory cores.
[0010] In one embodiment, the request message is processed by the first memory core to obtain the target message, including: identifying the type of the request message by the first memory core to obtain the first message type of the request message; and processing the request message based on the message processing method that matches the first message type to obtain the target message.
[0011] Secondly, this application also provides a message forwarding apparatus, comprising: an information acquisition module, configured to acquire source address information of a request message when a first object sends a request message to a second object; a hash processing module, configured to perform hash processing on the source address information to obtain a first hash value of the source address information; a memory core determination module, configured to select a first memory core that matches the first hash value from a plurality of first candidate memory cores used for message processing of the request message; and a message processing module, configured to perform message processing on the request message through the first memory core to obtain a first target message, and forward the first target message to the second object.
[0012] Thirdly, this application also provides a computer device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to perform the following steps: when a first object sends a request message to a second object, it obtains the source address information of the request message; performs hash processing on the source address information to obtain a first hash value of the source address information; selects a first memory core that matches the first hash value from a plurality of first candidate memory cores used for message processing of the request message; processes the request message through the first memory core to obtain a first target message, and forwards the first target message to the second object.
[0013] Fourthly, this application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, performs the following steps: when a first object sends a request message to a second object, obtaining the source address information of the request message; performing hash processing on the source address information to obtain a first hash value of the source address information; selecting a first memory core that matches the first hash value from a plurality of first candidate memory cores used for message processing of the request message; performing message processing on the request message through the first memory core to obtain a first target message, and forwarding the first target message to the second object.
[0014] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps: when a first object sends a request message to a second object, obtaining source address information of the request message; performing hash processing on the source address information to obtain a first hash value of the source address information; selecting a first memory core that matches the first hash value from a plurality of first candidate memory cores used for message processing of the request message; performing message processing on the request message through the first memory core to obtain a first target message, and forwarding the first target message to the second object.
[0015] The aforementioned message forwarding method, apparatus, computer device, computer-readable storage medium, and computer program product are applied to intermediate devices respectively connected to a first object and a second object. When the first object sends a request message to the second object, the intermediate device first obtains the source address information of the request message. The source address information is then hashed to obtain a first hash value. Next, among multiple first candidate memory cores used for message processing of the request message, a first memory core matching the first hash value is selected. The request message is then processed through the first memory core to obtain a first target message, which is then forwarded to the second object. In other words, this application uses hashing of address information to select the memory core for message processing. Due to the consistency of the hash function, the request message and response message will generate the same hash value, thus ensuring that the request message and response message are processed by the same memory core. Furthermore, each memory core can maintain its own message session information without needing to synchronize with other memory cores, effectively avoiding the overhead of thread synchronization. This not only improves the performance of intermediate devices, but also enables parallel execution of message forwarding, thereby improving the efficiency of message forwarding. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a diagram illustrating the application environment of a message forwarding method in one embodiment;
[0018] Figure 2 This is a flowchart illustrating a message forwarding method in one embodiment;
[0019] Figure 3 This is a schematic diagram illustrating the selection of the first memory core in one embodiment;
[0020] Figure 4 This is a schematic diagram of node chain forwarding in one embodiment;
[0021] Figure 5 This is a schematic diagram of adding a node in one embodiment;
[0022] Figure 6 This is a schematic diagram of the forwarding process of a response message in one embodiment;
[0023] Figure 7 This is a schematic diagram of the port number matching process in one embodiment;
[0024] Figure 8 This is a schematic diagram illustrating the process of decrypting a response message in one embodiment.
[0025] Figure 9 This is a schematic diagram illustrating the selection of a third memory core in one embodiment;
[0026] Figure 10 This is a schematic diagram of the LAN-side packet scheduling process in one embodiment;
[0027] Figure 11 This is a schematic diagram of the message cache reading process in one embodiment;
[0028] Figure 12 This is a schematic diagram of the memory core allocation process in one embodiment;
[0029] Figure 13 This is a flowchart illustrating a message forwarding method in a specific embodiment;
[0030] Figure 14 This is a structural block diagram of a message forwarding device in one embodiment;
[0031] Figure 15 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0032] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0033] The message forwarding method provided in this application embodiment can be applied to, for example, Figure 1 The diagram illustrates an SD-WAN network environment. Intermediate device 102 is connected to both first object 104 and second object 106. The intermediate device can be a gateway device, such as an EDGE gateway. First object 104 can refer to a terminal device on the LAN (Local Area Network) side, such as a network device within an enterprise. Second object 106 can refer to the network control center on the WAN (Wide Area Network) side. First object 104 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and IoT devices. Second object 106 can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services.
[0034] Specifically, when the first object 104 sends a request message to the second object 106, the intermediate device 102 first obtains the source address information of the request message. The source address information is hashed to obtain a first hash value. Among multiple first candidate memory cores used for message processing of the request message, a first memory core matching the first hash value is selected. The request message is processed using the first memory core to obtain a first destination message, which is then forwarded to the second object 106.
[0035] In one exemplary embodiment, such as Figure 2 As shown, a message forwarding method is provided, which is applied to... Figure 1 Taking intermediate device 102 as an example, the explanation includes:
[0036] Step S202: When the first object sends a request message to the second object, obtain the source address information of the request message.
[0037] In this context, a request message refers to a traffic message sent from the first object to the second object, also known as upstream traffic. The source address information refers to the source IP (Internet Protocol Address) address of the request message, which is the IP address of the first object.
[0038] For example, when the first object sends a request message to the second object, the gateway device will first obtain the source IP address of the request message, which is the IP address of the first object.
[0039] In one example, the gateway device can be a multi-core device, meaning it can contain multiple memory cores. In this embodiment, for the first object, the gateway device can have one fixed message receiving memory core and multiple first candidate memory cores for processing request messages initiated by the first object. Similarly, for the second object, the gateway device will also have one fixed message receiving memory core and multiple second candidate memory cores for processing response messages returned by the second object. It should be noted that the message receiving memory core is only used to receive request or response messages and does not participate in subsequent message processing. That is, the message receiving memory core corresponding to the first object in the gateway device will first receive the request message sent by the first object to the second object and obtain the source IP address of the request message.
[0040] In one instance, each memory core can have its own timer to periodically release resources, such as memory, so that memory can be used more effectively and the overhead of the gateway device can be reduced.
[0041] In one example, the packet receiving memory core can receive packets via polling using the DPDK (Data Plane Development Kit). DPDK polling means that when using DPDK for network packet processing, the packet receiving memory core continuously checks for new packets, thereby reducing the overhead of interrupt handling and improving packet processing efficiency.
[0042] Step S204: Hash the source address information to obtain the first hash value of the source address information.
[0043] Hash processing is a process of transforming an input of arbitrary length into an output of fixed length using a hash algorithm. In this embodiment, it refers to transforming the source address information into a fixed-length value, namely the first hash value, using a hash algorithm.
[0044] For example, after obtaining the source address information of a request packet, the packet receiving memory core of the gateway device can use a preset hash algorithm to hash the source address information to obtain a hash value. This hash value is then used for subsequent traffic packet scheduling, that is, scheduling the request packet to the corresponding memory core for processing.
[0045] Step S206: Among the multiple first candidate memory cores used for message processing of request messages, select the first memory core that matches the first hash value.
[0046] In this context, the first candidate memory core refers to the memory core that can be used to process request messages, or in other words, these first candidate memory cores are used to process the various request messages initiated by the first object. There can be multiple first candidate memory cores. The first memory core is the memory core that ultimately processes the request messages.
[0047] For example, after the message receiving memory core calculates the first hash value of the request message, it can further perform memory core matching based on the first hash value to select the first memory core that matches the first memory core from multiple first candidate memory cores corresponding to the first object, and use it for subsequent message processing of the request message.
[0048] Figure 3The diagram illustrates the selection of the first memory core. Here, `first_worker_index` is the memory core number of the first candidate memory core among multiple candidate memory cores. Assuming the packet receiving memory core is CPU1, and the multiple candidate memory cores are CPU2, CPU3...CPU11, then `first_worker_index` is the number of CPU2. It should be noted that the memory core number can be set arbitrarily; this embodiment does not impose any restrictions on this. `first_worker_index` is assigned to `next_worker_index`. Next, the first hash value is moduloed by the LAN-side thread count `len(lan_workers)`, which is 10 in this example. Finally, the value of `next_worker_index` is added to obtain the number of the first memory core to which the request packet is sent. After calculating the number, CPU1 performs traffic scheduling, that is, it schedules the request packet to the memory core with that number.
[0049] It should be noted that in this embodiment, a node-based chain forwarding mechanism can be used in the memory kernel to implement packet forwarding, that is, each operation is written as a node, such as route lookup, traffic scheduling, NAT (Network Address Translation), etc. Figure 4 As shown, in this embodiment, the nodes sequentially handle packet reception, route lookup, NAT translation, and packet transmission. In addition, a packet verification node can be deployed after receiving a packet to verify the MAC address of the request packet, ensuring that the request packet requires forwarding by the gateway device. The next node is determined based on fields in the packet. Taking NAT translation as an example, assuming the request packet is an IPv4 packet requiring NAT translation, it will be passed to the IPv4 node for processing, followed by route lookup to determine the next-hop address. After NAT translation, the packet is then sent.
[0050] In one example, such as Figure 5 As shown, the request packet enters the first memory core, which is called traffic enqueueing. The first memory core will then perform traffic dequeueing. At this point, a node can be added to the node chain to receive the traffic and forward it to the next node. This added node can be called the traffic integer node. It can be configured before route lookup.
[0051] Step S208: Process the request message through the first memory core to obtain the first target message, and forward the first target message to the second object.
[0052] The first target message refers to the message obtained after processing the request message.
[0053] For example, after completing traffic shaping, the first memory core can perform processing operations such as route lookup, NAT translation, and packet inspection on the request packet to obtain a final target packet. The gateway device will then send this target packet to the second object.
[0054] In this embodiment, when the first object sends a request message to the second object, the gateway device first obtains the source address information of the request message. The source address information is then hashed to obtain a first hash value. Next, among multiple first candidate memory cores used for message processing of the request message, a first memory core matching the first hash value is selected. The request message is then processed by the first memory core to obtain a first target message, which is then forwarded to the second object. In other words, this embodiment uses hashing of the address information to select the memory core for message processing. Due to the consistency of the hash function, the request message and response message will generate the same hash value, ensuring that the request message and response message are processed by the same memory core. This also means that each memory core can maintain its own message session information without needing to synchronize with other memory cores, effectively avoiding the overhead of thread synchronization. This not only improves the performance of the intermediate device but also enables parallel execution of message forwarding, thereby improving the efficiency of message forwarding.
[0055] In one exemplary embodiment, such as Figure 6 As shown, the message forwarding method also includes:
[0056] Step S602: When the second object returns a response message to the first object in response to the request message, the response message is type-identified to obtain the second message type of the response message.
[0057] A response message is a message returned by a second object to a first object after the second object receives the first object's request message. The response message contains the second object's processing result of the request message, or downlink traffic. Second message types include address translation messages and encrypted messages. Address translation messages are NAT messages, while encrypted messages are IPsec (Internet Protocol Security) messages, which are messages encrypted using IPsec.
[0058] For example, when the second object returns a response message to the first object in response to the request message, the gateway device will first identify the message type of the response message in order to match the corresponding message scheduling rules.
[0059] In one example, the gateway device's message receiving memory core for the second object can continuously receive response messages sent by the second object through DPDK polling mode and identify the message type of the response message.
[0060] In one example, the message receiving memory core can identify the message type of a response message by its destination port or message protocol number. For instance, if the response message is a UDP (User Datagram Protocol) message with a destination port number of 500 or 4500, or if the message protocol number is 50, then the response message can be considered an IPsec message. Otherwise, it is a NAT message. Of course, in practical applications, other message type identification rules can be defined, and this embodiment does not impose any restrictions on this.
[0061] Step S604: When the second message type is an address translation message, obtain the target port number of the response message.
[0062] For example, such as Figure 7 As shown, when the receiving memory core identifies the response packet as an Address Translation (NAT) packet, it can directly schedule the response packet to multiple first-candidate memory cores for processing, i.e., NAT translation. Considering that the IP address of the packet is translated during NAT translation—meaning the destination IP address in the response packet is actually the public IP address of the gateway device, not the IP address of the first target—if the memory core is directly determined based on the IP address, all response packets would be sent to the same memory core undergoing NAT translation, making that memory core a bottleneck. The port number is also translated, and each packet has a unique source and destination port number. By using the port number to determine which memory core to send to, finer-grained packet forwarding can be achieved, preventing a single memory core from becoming a bottleneck.
[0063] In one example, when the first memory core performs NAT translation on request packets, it evenly distributes the available ports of the gateway device's public IP address to each first candidate memory core. For instance, a public IP address typically has 65535 ports (from 0 to 65535), but some of these ports (such as 0 to 1023) are reserved for the system or well-known services and are therefore not used for general data transmission. The remaining ports (from 1024 to 65535) can be used for NAT translation. In this example, these available ports are evenly distributed among the candidate memory cores processing LAN-side packets. Assuming there are 10 candidate memory cores, each candidate memory core can obtain (65535 - 1024) / 10 = 6451 ports. Each candidate memory core is assigned a specific range of ports; for example, CPU2's port range is 1024 + 6451 * 1 = 7475, i.e., from 1024 to 7475. Similarly, the port range of CPU3 is 1024 + 6451*2 = 13926, that is, from 1025 to 13926, and so on. Thus, when a response message arrives, the receiving memory core determines which candidate memory core should handle the NAT reverse translation of the message based on the destination port number. For example, if the destination port number is 12000, it falls within the port range of CPU3, so the response message will be scheduled to CPU3 for processing. Of course, in practical applications, other port range definition rules can be defined according to actual needs; this embodiment does not impose such restrictions.
[0064] Step S606: Select a second memory core that matches the target port number from multiple first candidate memory cores.
[0065] The second memory core refers to the memory core that matches the target port number. In one example, the memory core that performs anti-NAT translation on the response message should be the same as the memory core that performs NAT translation on the request message; that is, the second memory core and the first memory core should be the same memory core.
[0066] For example, after the message receiving memory core obtains the target port number of the response message, it can match among multiple first candidate memory cores to filter out the memory core that matches the target port number.
[0067] Step S608: Process the response message through the second memory core to obtain the second target message, and send the second target message to the first object.
[0068] The second target message refers to the message obtained after processing the response message, such as the message after NAT translation of the response message.
[0069] For example, the message receiving memory core schedules the response message to the second memory core, which then processes the response message, such as performing route lookup and NAT translation, to obtain the second target message. The second target message is then sent to the first object.
[0070] In this embodiment, it can be seen that the traffic packets of the first object and the traffic packets of the second object are separated. That is, the uplink traffic on the LAN side and the downlink traffic on the WAN side are separated, effectively avoiding bottlenecks caused by a single memory core processing bidirectional traffic packets, which would lead to a decrease in the performance of the gateway device. Moreover, by matching port numbers, it is further ensured that response packets and request packets can be processed by the same memory core, realizing symmetrical packet forwarding and improving packet forwarding efficiency.
[0071] In one exemplary embodiment, such as Figure 8 As shown, the message forwarding method also includes:
[0072] Step S802: When the second message type is an encrypted message, obtain the number of memory cores of multiple second candidate memory cores used for message processing of the response message.
[0073] The second candidate memory core refers to the memory core used to process the response message returned by the second object. The number of memory cores refers to the total number of second candidate memory cores.
[0074] For example, when the gateway device's message receiving memory core identifies the response message as an encrypted message, i.e., an IPsec message, it will first obtain the total number of memory cores of multiple second candidate memory cores used to process the response message, and then use this information to filter the third memory core.
[0075] Step S804: Based on the number of memory cores, select a third memory core from multiple second candidate memory cores.
[0076] The third memory core refers to the memory core that performs decryption processing on the response message.
[0077] For example, such as Figure 9As shown, the packet receiving memory core introduces a counter, ipsec_thread, which automatically increments after each packet scheduling. `first_worker_index` is the memory core number of the first memory core among multiple second-candidate memory cores. `number_of_wan` is the number of memory cores processing WAN-side packets, i.e., the total number of second-candidate memory cores. The increment of 1 in the initial assignment of `next_worker_index` ignores the packet receiving memory core and uses it to receive response packets. Finally, the counter is moduloed by the WAN-side thread count `len(wan_workers)`, and then added to the initialized `next_worker_index` to determine the number of the next memory core to be scheduled to, i.e., the third memory core number.
[0078] Step S806: The response message is decrypted using the third memory core to obtain the decrypted message.
[0079] Among them, the decrypted message refers to the message obtained after decrypting the response message using IPsec.
[0080] For example, the message receiving memory core schedules the response message to the third memory core, where the third memory core performs traffic scheduling, traffic shaping, and IPsec decryption processing to obtain the decrypted message.
[0081] Step S808: Hash the target address information of the decrypted message to obtain the second hash value of the target address information.
[0082] The target address information refers to the target IP address of the decrypted message, which is the IP address of the first object. The second hash value is the hash value obtained after hashing the target address information.
[0083] For example, after decrypting the response message, message scheduling on the LAN side is required. Figure 10 As shown, since it is symmetrical to the request message, the target address information is used for hash calculation in this embodiment. This ensures that request messages and response messages on the same data stream can be scheduled to the same memory core.
[0084] Step S810: Select the fourth memory core that matches the second hash value from multiple first candidate memory cores.
[0085] For example, the gateway device selects a fourth memory core from multiple first candidate memory cores that matches the second hash value. It should be noted that the second hash value should be the same as the first hash value, therefore the fourth memory core and the first memory core should be the same memory core.
[0086] In step S812, the decrypted message is processed by the fourth memory core to obtain the third target message, and then the third target message is sent to the first object.
[0087] The third target message refers to the message obtained after processing the decrypted message, such as message inspection and session processing.
[0088] For example, the third memory core sends the decrypted message to the fourth memory core on the LAN side, where the fourth memory core processes the decrypted message to obtain the processed third target message. This third target message is then sent to the first object.
[0089] In this embodiment, when the response message is an IPsec message, a memory core is first selected on the WAN side for decryption, and then the target IP is hashed to select a memory core that matches the request message on the LAN side. This ensures that request and response messages on the same data stream can be scheduled to the same memory core, thus improving the efficiency of message forwarding.
[0090] In one exemplary embodiment, such as Figure 11 As shown, the message forwarding method also includes:
[0091] Step S1102: Determine the target sub-message that is ranked first among all sub-messages.
[0092] Step S1104: If the target sub-packet exists in the message cache list, read the target sub-packet and other sub-packets other than the target sub-packet from the message cache list.
[0093] A request message includes at least one sub-message; it can also be understood as an array of sub-messages, each representing a request. The target sub-message is the first sub-message. The message cache list is a list used to record cached messages; it can also be a cache area or a cache such as a cache buffer.
[0094] For example, when the message receiving memory core receives an array of request messages, it first extracts the first sub-message from the array and checks if the first sub-message exists in the message cache list. If it exists, it indicates a cache hit, meaning the first sub-message has been cached. Since the messages in the array are processed consecutively, messages after the first sub-message are also likely to be cached in the message cache list. The message receiving memory core can then directly read the target sub-message and other sub-messages from the message cache list. This means that this group of request messages will benefit from the cache hit of the first sub-message, achieving higher processing performance. If the first sub-message does not exist in the message cache list, it indicates a cache miss, meaning the first sub-message has not been cached. In this case, the message receiving memory core can use the first message for preheating, that is, loading the data of the first sub-message into the message cache list so that subsequent accesses to other messages in the array can utilize the acceleration effect of the message cache list. Once the first packet is warmed up in the packet cache list, subsequent accesses to other packets in the array are also likely to hit the cache due to the correlation or pattern of the packets. In this way, the processing performance of the remaining packets in the array can directly reach its limit, thereby improving the efficiency of requesting packet reading and thus improving the overall packet forwarding efficiency.
[0095] In one exemplary embodiment, such as Figure 12 As shown, the message forwarding method also includes:
[0096] Step S1202: Perform business complexity analysis on the first object and the second object respectively to obtain the first business complexity of the first object and the second business complexity of the second object.
[0097] The first level of service complexity characterizes the complexity of the services that the first object, i.e., the LAN side, needs to perform. The second level of service complexity characterizes the complexity of the services that the first object, i.e., the WAN side, needs to perform.
[0098] For example, when allocating candidate memory cores to the first object and the second object, the gateway device can first perform a business complexity analysis on both, that is, analyze the complexity of the business that the first object and the second object need to perform, so as to allocate an appropriate number of candidate memory cores.
[0099] Step S1204: Determine the number of first candidate memory cores that match the first level of business complexity and the number of second candidate memory cores that match the second level of business complexity.
[0100] The number of first candidate memory cores refers to the number of first candidate memory cores, while the number of second candidate memory cores refers to the number of second candidate memory cores.
[0101] For example, after analyzing the business complexity of the first object and the second object, the gateway device can match the number of memory cores, that is, query the number of candidate memory cores matching the first business complexity and the number of candidate memory cores matching the second business complexity. It can be understood that a table mapping the business complexity to the number of candidate memory cores can be pre-configured in the gateway device. Thus, the gateway device can directly query this table to determine the number of candidate memory cores configured for the first and second objects.
[0102] For example, suppose the first object, i.e., the LAN side, needs to handle route lookup, packet inspection, NAT translation, etc., for request packets, which is more complex than the second object, i.e., the WAN side. In this case, a larger number of candidate memory cores can be allocated to the first object. For instance, when the gateway device is an 18-core device, the first object can have 11 first candidate memory cores, while the second object can have 6 second candidate memory cores.
[0103] Step S1206: Determine a plurality of first candidate memory cores that match the number of first candidate memory cores, and a plurality of second candidate memory cores that match the number of second candidate memory cores.
[0104] For example, after the gateway device determines the number of first candidate memory cores and the number of second candidate memory cores, it can configure the corresponding number of first candidate memory cores and second candidate memory cores.
[0105] In this embodiment, by analyzing the business complexity of the first object and the second object, the number of memory cores is determined, thereby configuring an appropriate number of memory cores for the first object and the second object for packet scheduling and packet processing, which further improves the packet forwarding efficiency.
[0106] In an exemplary embodiment, processing a request message to obtain a target message using a first memory core includes: identifying the type of the request message using the first memory core to obtain a first message type of the request message; and processing the request message based on a message processing method that matches the first message type to obtain the target message.
[0107] The first message type refers to the message type of the request message, including NAT messages and IPsec messages. Message processing methods include NAT translation and IPsec encryption.
[0108] For example, refer to Figure 2When processing a request message, the first memory core can first identify the message type based on message fields such as the destination IP address, i.e., whether the request message is a NAT message or an IPsec message. If the request message is a NAT message, the first memory core can perform NAT translation before sending it. If the request message is an IPsec message, the first memory core can perform IPsec encryption before sending it.
[0109] In this embodiment, the type of the request message is identified to determine the corresponding message processing method, thereby ensuring the accuracy of message processing.
[0110] In one specific embodiment, such as Figure 13 As shown, Figure 13 The diagram illustrates packet forwarding. The EDGE gateway device is an 18-core device, meaning it has 18 CPUs (memory cores). EDGE allocates 11 CPUs (CPU1 to CPU11) to the LAN-side devices and 6 CPUs (CPU12 to CPU18) to the WAN-side networks, based on the complexity of the services provided by each device.
[0111] When the first object, i.e., the LAN-side device, sends a request message to the second object, i.e., the WAN-side network, CPU1, acting as the message receiving memory core, receives the request message and hashes its source IP address to obtain a hash value. This hash value is then used to determine the next CPU to be scheduled for the request message, which can be any one of CPU2 to CPU11. This CPU then performs NAT translation or IPsec encryption on the request message to obtain the target message. This CPU then forwards the target message to the WAN-side network.
[0112] When the WAN side network returns a corresponding response packet to the LAN side device, CPU12, as the packet receiving memory core, receives the response packet. First, it identifies the packet type. If the response packet is a NAT packet, NAT packet scheduling is performed, meaning the response packet is scheduled to CPU2 through CPU11 for NAT translation based on the destination port number. The CPUs processing the response packet and the request packet are the same. If the response packet is an IPsec packet, CPU12 will schedule the response packet to any one of CPUs 13 through CPU18 for IPsec decryption. The decrypted packet is then scheduled to CPU2 through CPU11 for LAN-side service processing.
[0113] In this embodiment, when the LAN-side device sends a request message to the WAN-side network, the EDGE gateway device first obtains the source address information of the request message. The source address information is then hashed to obtain a first hash value. Next, among the multiple CPUs used to process the request message, a first CPU matching the first hash value is selected. This first CPU processes the request message to obtain a first target message, which is then forwarded to the WAN-side network. In other words, this embodiment uses hashing of the address information to select the CPU for message processing. Due to the consistency of the hash function, the request message and response message will generate the same hash value, ensuring that the request message and response message are processed by the same CPU. This also means that each CPU can maintain its own message session information without needing to synchronize with other CPUs, effectively avoiding the overhead of thread synchronization. This not only improves the performance of the EDGE gateway device but also enables parallel execution of message forwarding, thereby improving message forwarding efficiency.
[0114] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0115] Based on the same inventive concept, this application also provides a packet forwarding apparatus for implementing the packet forwarding method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more packet forwarding apparatus embodiments provided below can be found in the limitations of the packet forwarding method described above, and will not be repeated here.
[0116] In one exemplary embodiment, such as Figure 14As shown, a message forwarding device is provided, including: an information acquisition module 1402, used to acquire source address information of a request message when a first object sends a request message to a second object; a hash processing module 1404, used to perform hash processing on the source address information to obtain a first hash value of the source address information; a memory core determination module 1406, used to select a first memory core that matches the first hash value from a plurality of first candidate memory cores used for message processing of the request message; and a message processing module 1408, used to perform message processing on the request message through the first memory core to obtain a first target message, and forward the first target message to the second object.
[0117] In one embodiment, the apparatus is further configured to: when the second object returns a response message to the first object in response to the request message, perform type identification on the response message to obtain a second message type of the response message; when the second message type is an address translation message, obtain the target port number of the response message; select a second memory core that matches the target port number from a plurality of first candidate memory cores; process the response message through the second memory core to obtain a second target message, and send the second target message to the first object.
[0118] In one embodiment, the apparatus is further configured to: when the second message type is an encrypted message, obtain the number of memory cores among a plurality of second candidate memory cores used for message processing of the response message; based on the number of memory cores, select a third memory core from the plurality of second candidate memory cores; decrypt the response message using the third memory core to obtain a decrypted message; hash the target address information of the decrypted message to obtain a second hash value of the target address information; select a fourth memory core from the plurality of first candidate memory cores that matches the second hash value; process the decrypted message using the fourth memory core to obtain a third target message; and send the third target message to the first object.
[0119] In one embodiment, the request message includes at least one sub-message, and the apparatus is further configured to: determine the target sub-message that is ranked first among the sub-messages; and if the target sub-message exists in the message cache list, read the target sub-message and other sub-messages other than the target sub-message from the message cache list.
[0120] In one embodiment, the apparatus is further configured to: perform business complexity analysis on the first object and the second object respectively to obtain a first business complexity of the first object and a second business complexity of the second object; determine the number of first candidate memory cores matching the first business complexity and the number of second candidate memory cores matching the second business complexity; and determine a plurality of first candidate memory cores matching the number of first candidate memory cores and a plurality of second candidate memory cores matching the number of second candidate memory cores.
[0121] In one embodiment, the message processing module 1408 is further configured to: identify the type of the request message through the first memory core to obtain the first message type of the request message; and process the request message based on the message processing method that matches the first message type to obtain the target message.
[0122] Each module in the aforementioned message forwarding device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.
[0123] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 15 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores message forwarding data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a message forwarding method.
[0124] Those skilled in the art will understand that Figure 15 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0125] In an exemplary embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to perform the following steps: when a first object sends a request message to a second object, obtaining source address information of the request message; performing hash processing on the source address information to obtain a first hash value of the source address information; selecting a first memory core that matches the first hash value from a plurality of first candidate memory cores used for message processing of the request message; performing message processing on the request message through the first memory core to obtain a first target message; and forwarding the first target message to the second object.
[0126] In one embodiment, when the processor executes the computer program, it further performs the following steps: when the second object returns a response message to the first object in response to the request message, it performs type identification on the response message to obtain a second message type of the response message; when the second message type is an address translation message, it obtains the target port number of the response message; from a plurality of first candidate memory cores, it selects a second memory core that matches the target port number; through the second memory core, it processes the response message to obtain a second target message, and sends the second target message to the first object.
[0127] In one embodiment, when the processor executes the computer program, it further performs the following steps: when the second message type is an encrypted message, it obtains the number of memory cores among a plurality of second candidate memory cores for message processing of the response message; based on the number of memory cores, it selects a third memory core from the plurality of second candidate memory cores; it decrypts the response message using the third memory core to obtain a decrypted message; it hashes the target address information of the decrypted message to obtain a second hash value of the target address information; it selects a fourth memory core from a plurality of first candidate memory cores that matches the second hash value; it processes the decrypted message using the fourth memory core to obtain a third target message, and sends the third target message to the first object.
[0128] In one embodiment, when the processor executes the computer program, it further performs the following steps: determining the target sub-packet that is ranked first among the sub-packets; and if the target sub-packet exists in the packet cache list, reading the target sub-packet and other sub-packets besides the target sub-packet from the packet cache list.
[0129] In one embodiment, when the processor executes the computer program, it further performs the following steps: performing business complexity analysis on the first object and the second object respectively to obtain the first business complexity of the first object and the second business complexity of the second object; determining the number of first candidate memory cores matching the first business complexity and the number of second candidate memory cores matching the second business complexity; and determining a plurality of first candidate memory cores matching the number of first candidate memory cores and a plurality of second candidate memory cores matching the number of second candidate memory cores.
[0130] In one embodiment, when the processor executes the computer program, it further performs the following steps: using a first memory core to identify the type of the request message and obtain a first message type of the request message; and processing the request message based on a message processing method that matches the first message type to obtain a target message.
[0131] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon. When the computer program is executed by a processor, it performs the following steps: when a first object sends a request message to a second object, it obtains the source address information of the request message; it performs hash processing on the source address information to obtain a first hash value of the source address information; it selects a first memory core that matches the first hash value from a plurality of first candidate memory cores used for message processing of the request message; it processes the request message through the first memory core to obtain a first target message, and forwards the first target message to the second object.
[0132] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: when the second object returns a response message to the first object in response to the request message, the response message is type-identified to obtain a second message type of the response message; when the second message type is an address translation message, the target port number of the response message is obtained; from a plurality of first candidate memory cores, a second memory core matching the target port number is selected; the response message is processed through the second memory core to obtain a second target message, and the second target message is sent to the first object.
[0133] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: when the second message type is an encrypted message, obtaining the number of memory cores among a plurality of second candidate memory cores for message processing of the response message; based on the number of memory cores, selecting a third memory core from the plurality of second candidate memory cores; decrypting the response message using the third memory core to obtain a decrypted message; hashing the target address information of the decrypted message to obtain a second hash value of the target address information; selecting a fourth memory core from a plurality of first candidate memory cores that matches the second hash value; processing the decrypted message using the fourth memory core to obtain a third target message; and sending the third target message to the first object.
[0134] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: determining the target sub-packet that is ranked first among the sub-packets; and, if the target sub-packet exists in the packet cache list, reading the target sub-packet and other sub-packets besides the target sub-packet from the packet cache list.
[0135] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: performing business complexity analysis on the first object and the second object respectively to obtain the first business complexity of the first object and the second business complexity of the second object; determining the number of first candidate memory cores matching the first business complexity and the number of second candidate memory cores matching the second business complexity; and determining a plurality of first candidate memory cores matching the number of first candidate memory cores and a plurality of second candidate memory cores matching the number of second candidate memory cores.
[0136] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: using a first memory core to identify the type of the request message and obtain a first message type of the request message; and processing the request message based on a message processing method that matches the first message type to obtain a target message.
[0137] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps: when a first object sends a request message to a second object, obtaining source address information of the request message; hashing the source address information to obtain a first hash value of the source address information; selecting a first memory core that matches the first hash value from a plurality of first candidate memory cores used for message processing of the request message; processing the request message through the first memory core to obtain a first target message; and forwarding the first target message to the second object.
[0138] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: when the second object returns a response message to the first object in response to the request message, the response message is type-identified to obtain a second message type of the response message; when the second message type is an address translation message, the target port number of the response message is obtained; from a plurality of first candidate memory cores, a second memory core matching the target port number is selected; the response message is processed through the second memory core to obtain a second target message, and the second target message is sent to the first object.
[0139] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: when the second message type is an encrypted message, obtaining the number of memory cores among a plurality of second candidate memory cores for message processing of the response message; based on the number of memory cores, selecting a third memory core from the plurality of second candidate memory cores; decrypting the response message using the third memory core to obtain a decrypted message; hashing the target address information of the decrypted message to obtain a second hash value of the target address information; selecting a fourth memory core from a plurality of first candidate memory cores that matches the second hash value; processing the decrypted message using the fourth memory core to obtain a third target message; and sending the third target message to the first object.
[0140] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: determining the target sub-packet that is ranked first among the sub-packets; and, if the target sub-packet exists in the packet cache list, reading the target sub-packet and other sub-packets besides the target sub-packet from the packet cache list.
[0141] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: performing business complexity analysis on the first object and the second object respectively to obtain the first business complexity of the first object and the second business complexity of the second object; determining the number of first candidate memory cores matching the first business complexity and the number of second candidate memory cores matching the second business complexity; and determining a plurality of first candidate memory cores matching the number of first candidate memory cores and a plurality of second candidate memory cores matching the number of second candidate memory cores.
[0142] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: using a first memory core to identify the type of the request message and obtain a first message type of the request message; and processing the request message based on a message processing method that matches the first message type to obtain a target message.
[0143] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.
[0144] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.
[0145] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.
[0146] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A message forwarding method, characterized in that, The method includes: When the first object sends a request message to the second object, the source address information of the request message is obtained; The source address information is hashed to obtain a first hash value of the source address information; Among a plurality of first candidate memory cores used for message processing of the request message, a first memory core that matches the first hash value is selected. The request message is processed by the first memory core to obtain a first target message, and the first target message is forwarded to the second object. When the second object returns a response message to the first object in response to the request message, the response message is type-identified to obtain the second message type of the response message; When the second message type is an encrypted message, obtain the number of memory cores of multiple second candidate memory cores used for message processing of the response message; Based on the number of memory cores, a third memory core is selected from the plurality of second candidate memory cores; The response message is decrypted using the third memory core to obtain a decrypted message; The target address information of the decrypted message is hashed to obtain a second hash value of the target address information; wherein the second hash value is the same as the first hash value; From the plurality of first candidate memory cores, a fourth memory core that matches the second hash value is selected; wherein, the fourth memory core and the first memory core are the same memory core; The decrypted message is processed by the fourth memory core to obtain a third target message, which is then sent to the first object.
2. The method according to claim 1, characterized in that, The method further includes: When the second message type is an address translation message, obtain the target port number of the response message; From the plurality of first candidate memory cores, a second memory core that matches the target port number is selected, wherein the second memory core and the first memory core are the same memory core; The response message is processed by the second memory core to obtain a second target message, which is then sent to the first object.
3. The method according to claim 1, characterized in that, The request message includes at least one sub-message, and the method further includes: Determine the target sub-message that is ranked first among all the described sub-messages; If the target sub-packet exists in the message cache list, read the target sub-packet and other sub-packets other than the target sub-packet from the message cache list.
4. The method according to claim 1, characterized in that, The method further includes: Business complexity analysis is performed on the first object and the second object respectively to obtain the first business complexity of the first object and the second business complexity of the second object; Determine the number of first candidate memory cores that match the complexity of the first business and the number of second candidate memory cores that match the complexity of the second business; A plurality of first candidate memory cores matching the number of the first candidate memory cores and a plurality of second candidate memory cores matching the number of the second candidate memory cores are determined.
5. The method according to claim 1, characterized in that, The step of processing the request message through the first memory core to obtain the target message includes: The request message is identified by the first memory core to obtain the first message type of the request message; Based on the message processing method that matches the first message type, the request message is processed to obtain the target message.
6. A message forwarding device, characterized in that, The device includes: The information acquisition module is used to acquire the source address information of the request message when the first object sends a request message to the second object; The hash processing module is used to perform hash processing on the source address information to obtain the first hash value of the source address information; The memory core determination module is used to select a first memory core that matches the first hash value from a plurality of first candidate memory cores used for message processing of the request message; The message processing module is configured to process the request message using the first memory core to obtain a first target message, and forward the first target message to the second object; when the second object returns a response message to the first object in response to the request message, the module performs type identification on the response message to obtain a second message type of the response message; when the second message type is an encrypted message, the module obtains the number of memory cores among multiple second candidate memory cores used for processing the response message; and based on the number of memory cores, selects a third memory core from the multiple second candidate memory cores. The response message is decrypted using the third memory core to obtain a decrypted message. The target address information of the decrypted message is hashed to obtain a second hash value of the target address information, wherein the second hash value is the same as the first hash value. A fourth memory core matching the second hash value is selected from the plurality of first candidate memory cores, wherein the fourth memory core is the same memory core as the first memory core. The decrypted message is processed using the fourth memory core to obtain a third target message, and the third target message is sent to the first object.
7. The apparatus according to claim 6, characterized in that, The message processing module is also used for: When the second message type is an address translation message, obtain the target port number of the response message; From the plurality of first candidate memory cores, a second memory core that matches the target port number is selected, wherein the second memory core and the first memory core are the same memory core; The response message is processed by the second memory core to obtain a second target message, which is then sent to the first object.
8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.