Bidirectional electrostatic protection semiconductor device and manufacturing method thereof

Abstract

The invention discloses a bidirectional electrostatic protection semiconductor device and a manufacturing method thereof. The bidirectional electrostatic protection semiconductor device comprises an epitaxial layer; the first P-type well region, the first N-type well region, the second P-type well region, the second N-type well region and the third P-type well region are sequentially distributed at the upper part of the epitaxial layer; the first MOS structure is positioned between the first P-type well region and the first N-type well region and comprises a first source region, a first drain region and a first gate region; the second MOS structure is positioned between the second P-type well region and the second N-type well region and comprises a second source region, a second drain region and a second gate region; a first P + injection region in the second P-type well region and a second P + injection region in the third P-type well region, the first P + injection region, the second source region and the second gate region are all connected to an anode, and the second P + injection region, the first source region and the first gate region are all connected to a cathode. According to the bidirectional electrostatic protection semiconductor device, by adding the MOS structure, the trigger voltage of the device is reduced, and the electrostatic protection capability is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a bidirectional electrostatic protection semiconductor device and a manufacturing method thereof. Background Art

[0002] ESD (Electro-Static discharge) is an objective natural phenomenon that accompanies the entire product cycle. ESD is not easily perceived by the human body, but it can pose a serious threat to integrated circuit products. During the manufacturing, packaging, testing and application stages of the chip, its external environment and internal structure will accumulate a certain amount of charge and will be threatened by static electricity at any time. Therefore, in chip design, it is necessary to place ESD protection devices on each pin. LDMOS (laterally-diffused metal-oxide semiconductor) or SCR (Silicon Controlled Rectifier) ​​structures are often used as ESD protection devices.

[0003] ESD protection devices with SCR structures are often used to protect ordinary I / O (input / output) ports of chips, but traditional thyristor structures usually have higher trigger voltages and lower holding voltages. A higher trigger voltage will cause the circuit to break down prematurely, and when the holding voltage is low, it may be lower than the power supply voltage or the port operating voltage. In this way, the thyristor may enter a latched state after being triggered by mistake, causing the chip to burn. In addition, the I / O ports of some chips can transmit positive and negative symmetrical level signals. For such ports that can transmit positive and negative symmetrical level signals, ESD protection devices also need to have bidirectional protection capabilities. Usually, a symmetrical SCR structure is selected for ESD protection. Such devices generate higher heat when discharging current, which can easily damage the ESD protection device or even burn the chip. Therefore, the current SCR structure electrostatic protection device has poor electrostatic protection capabilities. Summary of the invention

[0004] In view of the above problems, an object of the present invention is to provide a bidirectional electrostatic protection semiconductor device and a manufacturing method thereof to solve the problems in the prior art.

[0005] According to one aspect of the present invention, a bidirectional electrostatic protection semiconductor device is provided, comprising: an epitaxial layer stacked above a substrate; a first P-type well region, a second P-type well region, and a third P-type well region distributed at intervals, all extending from the surface of the epitaxial layer to the inside and separated from the substrate; a first N-type well region located between the first P-type well region and the second P-type well region and in contact with the first P-type well region; a second N-type well region located between the second P-type well region and the third P-type well region and in contact with the second P-type well region; a first MOS structure located between the first P-type well region and the first The second MOS structure is located between the second P-type well region and the second N-type well region, including a first source region, a first drain region and a first gate region; the second MOS structure is located between the second P-type well region and the second N-type well region, including a second source region, a second drain region and a second gate region; a first P+ injection region is distributed on one side of the second P-type well region close to the first N-type well region; and a second P+ injection region is distributed in the third P-type well region, wherein the first P+ injection region, the second source region and the second gate region are all connected to the anode, and the second P+ injection region, the first source region and the first gate region are all connected to the cathode.

[0006] Optionally, the first source region is a first N+ injection region, the first drain region is a second N+ injection region, the first N+ injection region is located in the first P-type well region, and the second N+ injection region is located between the first P-type well region and the first N-type well region; the second source region is a third N+ injection region, the second drain region is a fourth N+ injection region, the third N+ injection region is located in the second P-type well region, and the fourth N+ injection region is located between the second P-type well region and the second N-type well region.

[0007] Optionally, when the bidirectional electrostatic protection semiconductor device receives an electrostatic pulse of a positive voltage, the thyristor structure composed of the first P+ injection region, the second P-type well region, the first N-type well region, the first P-type well region and the first source region is turned on to form a first forward current discharge path from the anode to the cathode; when the bidirectional electrostatic protection semiconductor device receives an electrostatic pulse of a negative voltage, the thyristor structure composed of the second P+ injection region, the third P-type well region, the epitaxial layer, the second N-type well region, the second P-type well region and the second source region is turned on to form a first reverse current discharge path from the cathode to the anode.

[0008] Optionally, the bidirectional electrostatic protection semiconductor device also includes: a buried layer, located at the bottom of the epitaxial layer, in contact with the substrate, and having the same doping type as the first N-type well region and the second N-type well region; a deep N-well region, located below the first N-type well region and the second N-type well region, connecting the first N-type well region and the second N-type well region to the buried layer, wherein the doping concentration of the first source region, the first drain region, the second source region and the second drain region is the largest among all N-type doping regions, and the doping concentration of the buried layer is second only to the doping concentration of the first source region, the first drain region, the second source region and the second drain region.

[0009] Optionally, when the bidirectional electrostatic protection semiconductor device receives an electrostatic pulse of a positive voltage, the thyristor structure composed of the first P+ injection region, the second P-type well region, the buried layer, the first P-type well region and the first source region is turned on to form a second forward current discharge path from the anode to the cathode; when the bidirectional electrostatic protection semiconductor device receives an electrostatic pulse of a negative voltage, the thyristor structure composed of the second P+ injection region, the third P-type well region, the epitaxial layer, the buried layer, the second P-type well region and the second source region is turned on to form a second reverse current discharge path from the cathode to the anode.

[0010] Optionally, when the bidirectional electrostatic protection semiconductor device receives an electrostatic pulse with a positive voltage, the first forward current discharge path is opened before the second forward current discharge path, and the current on the first forward current discharge path is smaller than the current on the second forward current discharge path; when the bidirectional electrostatic protection semiconductor device receives an electrostatic pulse with a negative voltage, the first reverse current discharge path is opened before the second reverse current discharge path, and the current on the first reverse current discharge path is smaller than the current on the second reverse current discharge path.

[0011] Optionally, the second N-type well region and the third P-type well region are both annular regions, the first P-type well region, the first N-type well region and the second P-type well region are all located inside the annular region formed by the second N-type well region, the annular region formed by the third P-type well region is located outside the annular region formed by the second N-type well region, and the bidirectional electrostatic protection semiconductor device is a single-finger structure.

[0012] Optionally, the bidirectional electrostatic protection semiconductor device also includes: a third P+ injection region, located on a side of the first P-type well region away from the first N-type well region; a fourth P+ injection region, located on a side of the third P-type well region in the annular area close to the first P-type well region; and a field oxide layer distributed between each N+ injection region and each P+ injection region of the bidirectional electrostatic protection semiconductor device.

[0013] Optionally, the deep N-well region below the first N-type well region and the deep N-well region below the second N-type well region are separated from each other.

[0014] Optionally, the bidirectional electrostatic protection semiconductor device also includes: a fifth P+ injection region and a fifth N+ injection region, which are located inside the first P-type well region and on the same side of the first MOS structure, and the fifth N+ injection region is electrically connected to the first drain region; a sixth P+ injection region and a sixth N+ injection region, which are located inside the second P-type well region and on the same side of the second MOS structure, and the sixth N+ injection region is electrically connected to the second drain region.

[0015] According to another aspect of the present invention, a method for manufacturing a bidirectional electrostatic protection semiconductor device is provided, comprising: forming a substrate and an epitaxial layer stacked on the substrate; forming a first P-type well region, a second P-type well region, and a third P-type well region extending inward from the surface of the epitaxial layer and spaced apart from the substrate; forming a first N-type well region in contact with the first P-type well region between the first P-type well region and the second P-type well region, and forming a second N-type well region in contact with the second P-type well region between the second P-type well region and the third P-type well region; forming a first MO located between the first P-type well region and the first N-type well region S structure, the first MOS structure includes a first source region, a first drain region and a first gate region, forming a second MOS structure located between the second P-type well region and the second N-type well region, the second MOS structure includes a second source region, a second drain region and a second gate region; forming a first P+ injection region distributed on one side of the second P-type well region close to the first N-type well region and a second P+ injection region distributed in the third P-type well region, wherein the first P+ injection region, the second source region and the second gate region are all connected to the anode, and the second P+ injection region, the first source region and the first gate region are all connected to the cathode.

[0016] According to another aspect of the present invention, there is provided an integrated circuit, comprising: the above-mentioned bidirectional electrostatic protection semiconductor device.

[0017] The bidirectional electrostatic protection semiconductor device and the manufacturing method thereof provided by the present invention embed a GGNMOS structure on the basis of the SCR structure, and reduce the avalanche breakdown voltage and the trigger voltage of the device through the high-concentration source and drain region in the GGNMOS structure. In addition, by embedding the GGNMOS structure in the regions respectively connected to the anode and the cathode, a first forward current discharge path and a first reverse current discharge path are formed, so that the device has a bidirectional electrostatic protection capability. And the electrostatic protection in both directions can have a lower avalanche breakdown voltage and a holding voltage, thereby improving the electrostatic protection capability of the bidirectional electrostatic protection semiconductor device.

[0018] Furthermore, by alternating the first P-type well region, the first N-type well region, the second P-type well region, the second N-type well region and the third P-type well region and the position setting of the GGNMOS, the device has asymmetry in the layout of the single-finger structure. That is, the discharge paths of the current from the anode to the cathode of the device and from the cathode to the anode are different, and the forward current discharge path and the reverse current discharge path do not overlap. The electric field generated inside the well region is small, the heat generated is small, and the protection performance of the device is good. The bidirectional electrostatic protection semiconductor device can be used under relatively small operating voltage conditions (for example, ±5V).

[0019] Furthermore, a heavily doped buried layer is formed at the bottom of the epitaxial layer of the bidirectional electrostatic protection semiconductor device, so that the current can also pass through the bottom of the semiconductor device through the buried layer. Therefore, on the basis of the original SCR lateral current discharge path (the first forward current discharge path and the first reverse current discharge path), a longitudinal SCR current discharge path (the second forward current discharge path and the second reverse current discharge path) can be formed. The longitudinal SCR current discharge path is close to the bottom of the device, and the current discharge path is long, which can increase the holding voltage of the device. And because the buried layer is heavily doped, the longitudinal SCR current discharge path gradually becomes the dominant current discharge path, realizing current discharge inside the device and avoiding the accumulation of discharge heat on the surface of the device. In addition, the heavily doped buried layer also makes the on-resistance of the longitudinal SCR current discharge path smaller, and the on-resistance of the overall device is reduced by adding the buried layer.

[0020] Furthermore, a P+ injection region and an N+ injection region are arranged near the GGNMOS, and the N+ injection region is connected to the drain region of the GGNMOS through metal. The N+ injection region and the drain region of the GGNMOS are electrically connected to each other to maintain a low avalanche breakdown voltage and a low holding voltage. By setting a P+ injection region with a higher concentration, the doping concentration of the local area below the floating P+ injection region is increased, thereby inhibiting the current from passing through the device surface, that is, inhibiting the discharge current from passing through the lateral SCR current discharge path (the first forward current discharge path and the first reverse current discharge path). The longitudinal SCR current discharge path is further promoted to become the dominant current discharge path, and the on-resistance of the device is further reduced while maintaining a low avalanche breakdown voltage and trigger voltage, and the clamping voltage of the device is reduced, effectively avoiding the risk of premature breakdown of the internal circuit due to excessive clamping voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0022] Figure 1a and Figure 1b A cross-sectional schematic diagram and an equivalent circuit diagram of a conventional bidirectional electrostatic protection semiconductor device are shown respectively;

[0023] Figure 2 A schematic cross-sectional view of a bidirectional electrostatic protection semiconductor device according to a first embodiment of the present invention is shown;

[0024] Figure 3 A schematic cross-sectional view of a bidirectional electrostatic protection semiconductor device according to a second embodiment of the present invention is shown;

[0025] Figure 4a and Figure 4b Equivalent circuit diagrams of the bidirectional electrostatic protection semiconductor device according to the embodiment of the present invention when receiving an electrostatic pulse of a positive voltage and an electrostatic pulse of a negative voltage are respectively shown;

[0026] Figure 5a-5d Schematic cross-sectional views of various stages of a method for manufacturing a bidirectional electrostatic protection semiconductor device according to a first embodiment of the present invention are shown. DETAILED DESCRIPTION

[0027] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0028] When describing the structure of a device, when a layer or a region is referred to as being "on" or "above" another layer or another region, it may mean being directly above the other layer or another region, or having other layers or regions between it and the other layer or another region. Furthermore, if the device is turned over, the layer or the region will be "below" or "beneath" the other layer or another region. In this application, the term "semiconductor structure" refers to the collective term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.

[0029] Unless otherwise specified below, the various layers or regions of the semiconductor device may be composed of materials known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si and Ge. The gate conductor and electrode layer may be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of the various conductive materials.

[0030] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.

[0031] Figure 1a and Figure 1b A cross-sectional schematic diagram and an equivalent circuit diagram of a conventional bidirectional electrostatic protection semiconductor device are shown respectively.

[0032] like Figure 1aAs shown, it is a conventional bidirectional SCR structure electrostatic protection device. The bidirectional electrostatic protection semiconductor device 100 is a layout symmetrical structure, including a P-type doped substrate 101 (P-SUB), a P-type doped epitaxial layer 102 (P-EPI), an N-type doped deep N-well region 103 (DNW), a P-type well region 104 (PW1), an N-type well region 106 (NW), a P-type well region 105 (PW2), a P-type well region 107 (PW3) and a P-type well region 108 (PW4). The P-type well region 107 (PW3) and the P-type well region 108 (PW4) can be connected to form a ring region in a top view, so the P-type well region 107 (PW3) and the P-type well region 108 (PW4) can be a whole, surrounding the internal structure. The epitaxial layer 102 is located above the substrate 101, and the deep N-well region 103 extends from the surface of the epitaxial layer 102 to the inside, and is separated from the substrate 101. The P-type well region 104, the N-type well region 106, and the P-type well region 105 can be sequentially distributed in the deep N-well region 103, and the extension depths of the P-type well region 104, the N-type well region 106, and the P-type well region 105 are less than the extension depth of the deep N-well region 103. There is a P+ injection region in each of the P-type well region 107 and the P-type well region 108, namely, the P+ injection region 111 and the P+ injection region 114. When the P-type well region 107 and the P-type well region 108 are a whole, the P+ injection region 111 and the P+ injection region 114 can also be a whole. A P+ injection region and an N+ injection region are formed in each of the P-type well region 104 and the P-type well region 105, for example, a P+ injection region 112 and an N+ injection region 121 are formed in the P-type well region 104, and a P+ injection region 113 and an N+ injection region 122 are formed in the P-type well region 105. Each P+ implantation region and each N+ implantation region are located at the upper part of their respective well regions, and have substantially the same doping concentration. Each implantation region is sequentially separated by field oxide layers, namely, field oxide layer 181, field oxide layer 182, field oxide layer 183, field oxide layer 184, field oxide layer 185, field oxide layer 186, and field oxide layer 187.

[0033] Furthermore, the P+ injection region 113 and the N+ injection region 122 are connected to the anode, and the P+ injection region 112, the N+ injection region 121, the P+ injection region 111 and the P+ injection region 114 are all connected to the cathode. The equivalent SCR circuit of the bidirectional electrostatic protection semiconductor device 100 is composed of P+ injection, PW, NW and N+ injection. Figure 1b As shown, the well resistance of the P-type well region 105 is equivalent to Rpw2, the P+ injection region 113, the P-type well region 105, the N-type well region 106 and the P-type well region 104 are equivalent to a PNP transistor, and the well resistance of the P-type well region 104 is equivalent to Rpw1. The N+ injection region 122, the P-type well region 105 and the N-type well region 106 are equivalent to a parasitic transistor NPNR, and the N-type well region 106, the P-type well region 104 and the N+ injection region 121 are equivalent to a parasitic transistor NPNL. The equivalent circuit of the entire semiconductor is shown in FIG. Figure 1b , that is, the resistor Rpw2, the PNP transistor and the resistor Rpw1 are connected in series between the anode and the cathode, and the NPNR transistor and the NPNL transistor are connected in series between the anode and the cathode. The base of the NPNR transistor is connected to the connection node of the resistor Rpw2 and the PNP transistor, the base of the NPNL transistor is connected to the connection node of the resistor Rpw2 and the PNP transistor, and the base of the PNP transistor is connected to the connection node of the NPNR transistor and the NPNL transistor.

[0034] When the positive ESD pulse reaches the anode of the semiconductor device, the reverse biased PN junction composed of the N-type well region 106 and the P-type well region 104 will undergo avalanche breakdown, thereby generating a large number of carriers, which will continuously flow through the parasitic well resistor Rpw1 on the P-type well region 104, causing the voltage drop Vbe between the base and emitter of the lateral parasitic NPNL transistor to increase. Until Vbe is greater than 0.7V, the lateral parasitic transistor NPNL is triggered and works in the amplification region, and the amplified collector current will flow into the base region of the parasitic transistor PNP, and finally the parasitic transistor PNP is turned on. At this time, the parasitic transistor NPNL and the parasitic transistor PNP form an effective positive feedback, and a low-resistance positive SCR lateral current discharge path (the path shown by the solid arrow in the figure) is formed. When the negative ESD pulse reaches the cathode of the semiconductor device, the reverse biased PN junction composed of the N-type well region 106 and the P-type well region 105 will undergo avalanche breakdown, thereby generating a large number of carriers, which will continuously flow through the parasitic well resistor Rpw2 on the P-type well region 105, causing the voltage drop Vbe between the base and the emitter of the lateral parasitic NPNR transistor to increase. Until Vbe is greater than 0.7V, the lateral parasitic transistor NPNR is triggered and works in the amplification region, and the amplified collector current will flow into the base region of the parasitic transistor PNP, and finally the parasitic transistor PNP is turned on. At this time, the parasitic transistor NPNR forms an effective positive feedback with the parasitic transistor PNP, and a low-resistance reverse SCR lateral current discharge path (the path shown by the dotted arrow in the figure) is formed. Thus, ESD protection can be achieved in both forward and reverse directions.

[0035] However, due to the symmetry of the layout, the forward current discharge path and the reverse current discharge path overlap. The forward current discharge path will flow under the N+ injection area 122, causing a larger electric field between the N+ injection area 122 and the P-type well area 105. Similarly, the reverse current discharge path will cause a larger electric field to be generated between the N+ injection area 121 and the P-type well area 104, thereby generating a larger amount of heat. Large amounts of heat may cause the device to break down prematurely, and when one side breaks down, the other side will also break down, thereby damaging the device. Moreover, the semiconductor device uses a deep N-well area 103 as an isolation well. Since the doping concentration of the deep N-well area 103 is low and its ability to attract electrons is weak, the discharge current will flow through the P-type well area 104, the N-type well area 106, and the P-type well area 105, that is, Figure 1a and Figure 1b The lateral SCR current discharge path shown in FIG. 1 shows a lower holding voltage of the device. The avalanche breakdown voltage between the well regions is higher, and the trigger voltage of the device is higher.

[0036] In order to improve the above problems, the embodiment of the present invention provides an asymmetric low trigger voltage bidirectional SCR electrostatic protection device, namely Figure 2 and Figure 3 The bidirectional electrostatic protection semiconductor device 200 shown in the embodiment. The bidirectional electrostatic protection semiconductor device 200 is based on the traditional bidirectional electrostatic protection semiconductor device 100, and the traditional bidirectional electrostatic protection semiconductor device 100 is deformed in structure and layout, and a GGNMOS structure is embedded to reduce the avalanche breakdown voltage and trigger voltage of the device, so that the avalanche breakdown voltage and trigger voltage of the device are basically consistent with those of GGNMOS, and the heat generated in the current discharge path can be reduced through the asymmetric layout, thereby improving the electrostatic protection capability of the device. Figure 2-Figure 5d Provide a detailed introduction.

[0037] Figure 2 FIG. 4 is a schematic cross-sectional view of a bidirectional electrostatic protection semiconductor device according to a first embodiment of the present invention.

[0038] like Figure 2 As shown, the bidirectional electrostatic protection semiconductor device 200 of this embodiment includes: a substrate 201, an epitaxial layer 203 located above the substrate 201, a first P-type well region 205 located at the upper part of the epitaxial layer 203, a first N-type well region 206, a second P-type well region 207, a second N-type well region 208 and a third P-type well region 209. The substrate 201 is usually P-type doped (P-SUB), and the epitaxial layer 203 can be P-type doped or N-type doped. In this embodiment, the epitaxial layer 203 is, for example, P-type doped (P-EPI). The P-type well regions are all P-type doped, and the N-type well regions are all N-type doped. In this embodiment, the first P-type well region 205 (PW1), the second P-type well region 207 (PW2) and the third P-type well region 209 (PW3) are distributed in sequence, and all extend from the surface of the epitaxial layer 203 to the inside, and are separated from the substrate 201. The first N-type well region 206 (NW1) is located between the first P-type well region 205 and the second P-type well region 207, and is in contact with the first P-type well region 205. The second N-type well region 208 (NW2) is located between the second P-type well region 207 and the third P-type well region 209, and is in contact with the second P-type well region 207. The doping concentrations of the first P-type well region 205, the first N-type well region 206, the second P-type well region 207, the second N-type well region 208, and the third P-type well region 209 are similar, and the extension depths can be the same.

[0039] The bidirectional electrostatic protection semiconductor device 200 of this embodiment also includes a first MOS structure and a second MOS structure, and the first MOS structure and the second MOS structure are, for example, GGNMOS (Gate Grounded NMOS) structures. This embodiment reduces the avalanche breakdown voltage and holding voltage of the device by setting GGNMOS, and can promote the formation of the SCR current discharge path. The first MOS structure is located between the first P-type well region 205 and the first N-type well region 206, and includes a first source region, a first drain region and a first gate region 231. The first source region is, for example, a first N+ injection region 221, and the first drain region is, for example, a second N+ injection region 222. The first N+ injection region 221 is located in the first P-type well region 205, and the second N+ injection region 222 is located between the first P-type well region 205 and the first N-type well region 206. The first gate region 231 is located on the surface of the first P-type well region 205 between the first N+ injection region 221 and the second N+ injection region 222. The first gate region 231 is, for example, stacked by a multi-layer structure, and the multi-layer structure may include a field plate layer. The second MOS structure is located between the second P-type well region 207 and the second N-type well region 208, and includes a second source region, a second drain region and a second gate region 232. The second source region is, for example, the third N+ injection region 223, and the second drain region is the fourth N+ injection region 224. The third N+ injection region 223 is located in the second P-type well region 207, and the fourth N+ injection region 224 is located between the second P-type well region 207 and the second N-type well region 208. The second gate region 232 is located on the surface of the second P-type well region 207 between the third N+ injection region 223 and the fourth N+ injection region 224. The second gate region 232 is, for example, formed by stacking a multi-layer structure, and the multi-layer structure may include a field plate layer.

[0040] Further, a first P+ injection region 211 is distributed in the second P-type well region 207, a second P+ injection region 212 is distributed in the third P-type well region 209, and the first P+ injection region 211 is located on the side of the second P-type well region 207 close to the first N-type well region 206. A third P+ injection region 213 may also be distributed in the first P-type well region 205, and the third P+ injection region 213 is located on the side of the first P-type well region 205 away from the first N-type well region 206. Each N+ injection region and each P+ injection region are formed on the upper part of their respective well regions, and can be formed by injecting from the surface of the well region to the inside. In this embodiment, the doping concentration of all P+ injection regions can be the same, and the doping concentration of all N+ injection regions can be the same. Moreover, among all regions with P-type doping (including well regions, injection regions, epitaxial layers, and substrates, etc.), the doping concentration of the P+ injection region is the largest, and among all regions with N-type doping (including well regions, injection regions, deep N-well regions, and buried layers, etc.), the doping concentration of the N+ injection region is also the largest. The doping concentration of the P+ injection region and the doping concentration of the N+ injection region may also be the same. In addition, a plurality of field oxide layers, such as field oxide layer 282, field oxide layer 283, field oxide layer 284, field oxide layer 285, field oxide layer 286, and field oxide layer 287, are distributed between the gaps between each N+ injection region and each P+ injection region.

[0041] Furthermore, multiple injection regions can be connected by metal to form the cathode and anode of the device. In this embodiment, the first P+ injection region 211, the second source region (the third N+ injection region 223) and the second gate region 232 are all connected to the anode, and the second P+ injection region 212, the third P+ injection region 213, the first source region (the first N+ injection region 221) and the first gate region 231 are all connected to the cathode. When an electrostatic pulse comes, due to the presence of the GGNMOS structure, the doping concentration of the drain region is relatively large, and the avalanche breakdown voltage between the drain region and the P-type well region is relatively small, so that the GGNMOS structure will transfer the avalanche breakdown surface from the original N-type well region to the P-type well region to the drain region to the P-type well region of the MOS structure, thereby reducing the avalanche breakdown voltage and trigger voltage of the device. Therefore, under the influence of the GGNMOS structure, when a positive voltage electrostatic pulse comes, a forward current discharge path will be formed from the first P+ injection area 211 to the first N+ injection area 221. Similarly, when a negative voltage electrostatic pulse comes, a reverse current discharge path will be formed from the second P+ injection area 212 to the third N+ injection area 223. Therefore, in this embodiment, by embedding the GGNMOS structure in the SCR structure, the formation of a lateral current discharge path can be promoted, and the avalanche breakdown voltage and holding voltage of the device can be reduced. In addition, the bidirectional electrostatic protection semiconductor device 200 of this embodiment adopts an asymmetric structure. Due to the presence of GGNMOS, the positive and reverse current discharge paths will not overlap, the electric field generated in the well area is small, the heat is low, and it is not easy to damage the circuit.

[0042] Further, in this embodiment, the second N-type well region 208 and the third P-type well region 209 may both be ring-shaped regions. Figure 2What is shown is a cross-sectional view of the device. When viewed from a top view, the second N-type well regions 208 on the left and right sides are interconnected to form an annular region, and the third P-type well regions 209 on the left and right sides are also interconnected to form an annular region. Then, the first P-type well region 205, the first N-type well region 206, and the second P-type well region 207 are all located inside the annular region formed by the second N-type well region 208, and the annular region formed by the third P-type well region 209 is located outside the annular region formed by the second N-type well region 208. Then the fourth P+ injection region 214 can be located on one side of the third P-type well region 209 in the annular region close to the first P-type well region 205. Then, the field oxide layer 281, the field oxide layer 282, the field oxide layer 283, the first gate layer 231, the field oxide layer 284, the field oxide layer 285, the second gate layer 232, the field oxide layer 286 and the field oxide layer 287 sequentially separate the fourth P+ injection area 214, the third P+ injection area 213, the first N+ injection area 221, the second N+ injection area 222, the first P+ injection area 211, the third N+ injection area 223, the fourth N+ injection area 224 and the second P+ injection area 212. When the third P-type well area 209 is a ring area, the fourth P+ injection area 214 and the second P+ injection area 212 can also be connected as a whole. In this embodiment, the bidirectional electrostatic protection semiconductor device 200 can be a single-finger structure with an asymmetric layout. Of course, in other embodiments, it can also be improved based on the above-mentioned single-finger structure to realize a dual-finger or multi-finger structure. The current discharge path and principle of the dual-finger or multi-finger structure are the same as Figure 2 The same as shown, both Figure 2 As the basis.

[0043] Specifically, in Figure 2In the bidirectional electrostatic protection semiconductor device 200, when a positive electrostatic pulse comes, a positive voltage is generated on the anode, and an avalanche breakdown occurs between the second N+ injection region 222 and the first P-type well region 205. In the bidirectional electrostatic protection semiconductor device 200, a PNP parasitic transistor PNP1 is formed by the first P+ injection region 211, the second P-type well region 207, the epitaxial layer 203, the first N-type well region 206 and the first P-type well region 205. And an NPN parasitic transistor NPN1 is formed by the first N-type well region 206, the first P-type well region 205 and the first N+ injection region 221. A parasitic well resistor R1 is generated in the second P-type well region 207, and a well resistor R2 is generated in the first P-type well region 205. The avalanche breakdown voltage raises the voltage across the resistor R2, raises the voltage drop between the base and emitter of NPN1, turns on NPN1, and thus raises the base current of PNP1, and PNP1 is also turned on. Thus, when the bidirectional electrostatic protection semiconductor device 200 receives an electrostatic pulse of a positive voltage, the PNPN thyristor structure composed of the first P+ injection region 211, the second P-type well region 207, the first N-type well region 206, the first P-type well region 205 and the first source region (the first N+ injection region 221) is turned on to form a first forward current discharge path from the anode to the cathode, that is, Figure 2 The solid arrow shows a first forward current discharge path P1.

[0044] Similarly, when a negative electrostatic pulse comes, a negative voltage is generated on the anode, and an avalanche breakdown occurs between the fourth N+ injection region 224 and the second P-type well region 207. In the bidirectional electrostatic protection semiconductor device 200, a PNP parasitic transistor PNP2 is formed by the second P+ injection region 212, the third P-type well region 209, the epitaxial layer 203, the second N-type well region 208 and the second P-type well region 207. And an NPN parasitic transistor NPN3 is formed by the second N-type well region 208, the second P-type well region 207 and the third N+ injection region 223. A parasitic well resistor R3 is generated in the third P-type well region 209, and a well resistor R4 is generated in the second P-type well region 205. The avalanche breakdown voltage raises the voltage across the resistor R4, raises the voltage drop between the base and emitter of NPN3, turns on NPN3, and thus raises the base current of PNP2, and PNP2 is also turned on. Therefore, when the bidirectional electrostatic protection semiconductor device 200 receives an electrostatic pulse of negative voltage, the PNPN thyristor structure composed of the second P+ injection region 212, the third P-type well region 209, the epitaxial layer 203, the second N-type well region 208, the second P-type well region 207 and the second source region (the third N+ injection region 223) is turned on to form a first reverse current discharge path from the cathode to the anode, that is, Figure 2 The first reverse current discharge path P3 is shown by the dashed arrow.

[0045] In other embodiments, Figure 2The bidirectional electrostatic protection semiconductor device 200 also includes a buried layer 202 and a deep N-well region 204. The buried layer 202 is located at the bottom of the epitaxial layer 203 and is in contact with the substrate 201. The doping type of the buried layer 202 (NBL) is the same as the doping type of the first N-type well region 206 and the second N-type well region 208, and the doping concentration of the buried layer 202 is greater than the doping concentration of the first N-type well region 206 and the second N-type well region 208. For example, the doping concentration of the buried layer 202 is second only to the one with the larger doping concentration between the P+ injection region and the N+ injection region. That is, the doping concentration of the buried layer 202 is second only to the injection region with the highest doping concentration. The deep N-well region 204 (DNW) is located below the first N-type well region 206 and the second N-type well region 208, connecting the first N-type well region 206 and the second N-type well region 208 to the buried layer 202. Figure 2 In the embodiment, the deep N-well region 204 below the first N-type well region 206 and the deep N-well region 204 below the second N-type well region 208 are separated from each other. That is, the first P-type well region 205 to the third P-type well region 209 are separated by the epitaxial layer 203 and the buried layer 202. The first N-type well region 206 and the second N-type well region 208 can be formed inside the corresponding deep N-well region 204. The buried layer 202 and the deep N-well region 204 can provide internal and external isolation for the device, so that the device has a good electrostatic protection effect. Since a heavily doped buried layer 202 is formed in the epitaxial layer 203, the buried layer 202 has a strong attraction for electrons, which can guide the current from the top of the device to flow deeper into the device or even to the bottom of the device, thereby reducing the current accumulation on the surface of the device, so an additional longitudinal SCR current discharge path will be formed.

[0046] Specifically, when a positive electrostatic pulse comes, a positive voltage is generated on the anode, and an avalanche breakdown occurs between the second N+ injection region 222 and the first P-type well region 205. In the bidirectional electrostatic protection semiconductor device 200, a PNP parasitic transistor PNP1 is formed by the first P+ injection region 211, the second P-type well region 207, the epitaxial layer 203, the buried layer 202, the epitaxial layer 203 and the first P-type well region 205. An NPN parasitic transistor NPN2 is formed by the buried layer 202, the epitaxial layer 203, the first P-type well region 205 and the first N+ injection region 221. Therefore, when the bidirectional electrostatic protection semiconductor device 200 receives an electrostatic pulse of positive voltage, the PNPN thyristor structure composed of the first P+ injection region 211, the second P-type well region 207, the buried layer 202, the first P-type well region 205 and the first source region (the first N+ injection region 221) can be turned on to form a second forward current discharge path from the anode to the cathode, that is, Figure 2 The second forward current discharge path P2 is shown by the solid arrow. The first current discharge path P1 is a transverse path, and the second current discharge path P2 is a longitudinal path.

[0047] Similarly, when a negative electrostatic pulse comes, a negative voltage is generated on the anode, and an avalanche breakdown occurs between the fourth N+ injection region 224 and the second P-type well region 207. In the bidirectional electrostatic protection semiconductor device 200, a PNP parasitic transistor PNP2 is formed by the second P+ injection region 212, the third P-type well region 209, the epitaxial layer 203, the buried layer 202, the epitaxial layer 203 and the second P-type well region 207. And an NPN parasitic transistor NPN4 is formed by the buried layer 202, the epitaxial layer 203, the second P-type well region 207 and the third N+ injection region 223. Therefore, when the bidirectional electrostatic protection semiconductor device 200 receives an electrostatic pulse of negative voltage, the PNPN thyristor structure composed of the second P+ injection region 212, the third P-type well region 209, the epitaxial layer 203, the buried layer 202, the second P-type well region 207 and the second source region (the third N+ injection region 223) is turned on to form a second reverse current discharge path from the cathode to the anode, that is, Figure 2 The first reverse current discharge path P4 is shown by the dotted arrow. Among them, the first current discharge path P1 is a lateral path, and the second current discharge path P2 is a longitudinal path. Therefore, by setting the buried layer 202 and the deep N-well region 204, a longitudinal current discharge path is added on the basis of the original lateral current discharge path, and bidirectional current discharge can be achieved. Thereby, the current discharge path is extended and the holding voltage of the device is improved. On the basis of the GGNMOS structure making the trigger voltage lower, the holding voltage is increased, and the heat generated is small, and the protection performance of the device is improved.

[0048] Further, in this embodiment, when the bidirectional electrostatic protection semiconductor device 200 receives an electrostatic pulse of a positive voltage, the first forward current discharge path P1 is opened before the second forward current discharge path P2. After opening, since the buried layer has a heavily doped type, the base current amplification factor of the parasitic transistor NPN2 is less than that of the parasitic transistor NPN1, so the current on the first forward current discharge path P1 is less than the current on the second forward current discharge path P2, so that the second forward current discharge path P2 becomes the dominant current discharge path, and the current path is extended, so the device has a higher maintenance voltage. Similarly, when the bidirectional electrostatic protection semiconductor device 200 receives an electrostatic pulse of a negative voltage, the first reverse current discharge path P3 is opened before the second reverse current discharge path P4, and the current on the first reverse current discharge path P3 is less than the current on the second reverse current discharge path P4. Since the second longitudinal forward current discharge path P2 and the second reverse current discharge path P4 become the dominant paths, current discharge is achieved inside the device, avoiding the concentration of discharge heat on the device surface, improving heat distribution, and increasing the failure current of the device.

[0049] However, due to the presence of GGNMOS, the first forward current discharge path P1 and the first reverse current discharge path P3 are opened first, and the on-resistance on the path is relatively large. Moreover, the simultaneous existence of paths P1 and P2 will also cause the on-resistance of the device to have a characteristic from large to small. A large on-resistance will cause the clamping voltage to be too large, reducing the protection effect of the semiconductor device on the internal circuit. Therefore, on the basis of the first embodiment, a floating P+ injection region and an N+ injection region with the same potential as the drain region of the GGNMOS can be added, that is, the second embodiment of the present application.

[0050] Figure 3 FIG. 4 is a schematic cross-sectional view of a bidirectional electrostatic protection semiconductor device according to a second embodiment of the present invention.

[0051] like Figure 3 As shown, the bidirectional electrostatic protection semiconductor device 200 of this embodiment is Figure 2 On the basis of all structures, it also includes: a fifth P+ injection region 215 and a fifth N+ injection region 225, a sixth P+ injection region 216 and a sixth N+ injection region 226. The fifth P+ injection region 215 and the fifth N+ injection region 225 are both located inside the first P-type well region 205 and on the same side of the first MOS structure. In the first P-type well region 205, the third P+ injection region 213, the first N+ injection region 221, the second N+ injection region 222, and the fifth P+ injection region 215 are distributed in sequence, and the fifth N+ injection region 225 is located at the junction of the first P-type well region 205 and the first N-type well region 206. Moreover, the fifth N+ injection region 215 and the first drain region (the second N+ injection region 222) are electrically connected from the outside through metal, so that the fifth N+ injection region 215 and the first drain region are at the same potential, and the fifth P+ injection region is floating. Similarly, the sixth P+ injection region 216 and the sixth N+ injection region 226 are both located inside the second P-type well region 207 and on the same side of the second MOS structure. In the second P-type well region 207, the first P+ injection region 211, the third N+ injection region 223, the fourth N+ injection region 224, and the sixth P+ injection region 216 are sequentially distributed, and the sixth N+ injection region 226 is located at the junction of the second P-type well region 207 and the second N-type well region 208. Moreover, the sixth N+ injection region 216 and the second drain region (the third N+ injection region 223) are electrically connected from the outside through metal, so that the sixth N+ injection region 216 and the second drain region are at the same potential, and the sixth P+ injection region is floating. Each injection region is separated by a field oxide layer. In this embodiment, the field oxide layer is uniformly represented by 280.

[0052] Due to the existence of the fifth N+ injection region and the sixth N+ injection region, which are at the same potential as the first drain region and the second drain region, the avalanche breakdown voltage between the N+ injection region and the P-type well region is still small, and does not affect the forward and reverse current discharge paths. That is, in FIG4, the first forward current discharge path P1, the second forward current discharge path P2, the first reverse current discharge path P3 and the second reverse current discharge path P4 are Figure 2 The embodiments are the same, and the working principles are the same, which will not be repeated here. However, due to the presence of the floating fifth P+ injection area 215 and the sixth P+ injection area 216, the doping concentration of the local area below the fifth P+ injection area 215 and the sixth P+ injection area 216 is relatively high, which will inhibit the flow of current, and inhibit the current from flowing from the first forward current discharge path P1 and the first reverse current discharge path P3, that is, the lateral current discharge path is inhibited, and the current flows more from the longitudinal current discharge path. That is, due to the effect of the floating P+ injection area, electrons are more easily attracted by the heavily doped buried layer 202 at the bottom, further inhibiting the formation of the lateral paths P1 and P3 and promoting the formation of the longitudinal paths P2 and P4 at the same time. The longitudinal paths P2 and P4 become the main discharge paths of the device, respectively, reducing the on-resistance. The higher doping concentration of the buried layer 202 will also make the device have a lower on-resistance, and the clamping voltage of the device will also be reduced, thereby achieving effective protection of the internal circuit. Therefore, in this embodiment, by setting the N+ injection region and the P+ injection region, the on-resistance of the device can be further reduced without changing the avalanche breakdown voltage and trigger voltage of the device, thereby achieving better electrostatic protection.

[0053] In addition, in this embodiment, the deep N-well region 204 is a whole, that is, the deep N-well region 204 below the first N-type well region 206 and the second N-type well region 208 are interconnected, and the first P-type well region 205 and the second P-type well region 207 are also located inside the deep N-well region 204. The deep N-well region 204 and the buried layer 202 together realize the internal and external isolation of the device.

[0054] Figure 4a and Figure 4b Equivalent circuit diagrams of the bidirectional electrostatic protection semiconductor device according to the embodiment of the present invention when receiving an electrostatic pulse of a positive voltage and an electrostatic pulse of a negative voltage are respectively shown.

[0055] Figure 4a is an equivalent circuit diagram of a bidirectional electrostatic protection semiconductor device according to an embodiment of the present invention when receiving an electrostatic pulse of a positive voltage. Figure 2 and Figure 3 It is applicable to all semiconductor devices. Figure 4aIn the figure, R1 represents the well resistance of the second P-type well region 207, and R2 represents the well resistance of the first P-type well region 205. The first P+ injection region 211, the second P-type well region 207, the first N-type well region 206 and the first P-type well region 205 form a PNP parasitic transistor PNP1. The first N-type well region 206, the first P-type well region 205 and the first N+ injection region 221 form an NPN parasitic transistor NPN1. The buried layer 202, the first P-type well region 205 and the first N+ injection region 221 form an NPN parasitic transistor NPN2. The resistor R1, the transistor PNP1 and the resistor R2 are connected in series between the anode and the cathode, and the transistor NPN1 and the transistor NPN2 are connected in parallel between the base and the cathode of the transistor PNP1. Thus, the first forward current discharge path P1 and the second forward current discharge path P2 shown in the figure can be formed. However, due to Figure 3 In the embodiment, a fifth P+ injection region is added, so Figure 3 In the equivalent circuit corresponding to the embodiment, the current on the second forward current discharge path P2 is larger. Figure 2 and Figure 3 In the corresponding equivalent circuit, the currents on the P1 and P2 paths are different. Figure 4b is an equivalent circuit diagram of a bidirectional electrostatic protection semiconductor device according to an embodiment of the present invention when receiving an electrostatic pulse of a negative voltage. Figure 2 and Figure 3 It is applicable to all semiconductor devices. Figure 4b In the figure, R3 represents the well resistance of the third P-type well region 209, and R4 represents the well resistance of the second P-type well region 207. The second P+ injection region 212, the third P-type well region 209, the second N-type well region 208 and the second P-type well region 207 form a PNP parasitic transistor PNP2. The second N-type well region 208, the second P-type well region 207 and the third N+ injection region 223 form an NPN parasitic transistor NPN3. The buried layer 202, the second P-type well region 207 and the third N+ injection region 223 form an NPN parasitic transistor NPN4. The resistor R3, the transistor PNP2 and the resistor R4 are connected in series between the anode and the cathode, and the transistor NPN3 and the transistor NPN4 are connected in parallel between the base and the cathode of the transistor PNP2. Thus, the first reverse current discharge path P3 and the second reverse current discharge path P4 shown in the figure can be formed. However, due to Figure 3 In the embodiment, a sixth P+ injection region is added, so Figure 3 In the equivalent circuit corresponding to the embodiment, the current on the second reverse current discharge path P4 is larger. Figure 2 and Figure 3 In the corresponding equivalent circuit, the currents on the P3 and P4 paths are different.

[0056] The present invention also provides a method for manufacturing a bidirectional electrostatic protection semiconductor device, which specifically includes the following steps: forming a substrate and an epitaxial layer stacked on the substrate; forming a first P-type well region, a second P-type well region and a third P-type well region that are spaced and extend from the surface of the epitaxial layer to the inside and are separated from the substrate; forming a first N-type well region in contact with the first P-type well region between the first P-type well region and the second P-type well region, and forming a second N-type well region in contact with the second P-type well region between the second P-type well region and the third P-type well region; forming a first MOS structure located between the first P-type well region and the first N-type well region, the first MOS structure including a first source region, a first drain region and a first gate region, forming a second MOS structure located between the second P-type well region and the second N-type well region, the second MOS structure including a second source region, a second drain region and a second gate region; forming a first P+ injection region distributed on one side of the second P-type well region close to the first N-type well region and a second P+ injection region distributed in the third P-type well region. The first P+ injection region, the second source region and the second gate region are all connected to the anode, and the second P+ injection region, the first source region and the first gate region are all connected to the cathode.

[0057] Figure 5a-5d Schematic cross-sectional views of various stages of a method for manufacturing a bidirectional electrostatic protection semiconductor device according to a first embodiment of the present invention are shown. Figure 5a-5d The process steps to produce Figure 2 The bidirectional electrostatic protection semiconductor device shown in the figure is used to further enhance the electrostatic protection capability of the semiconductor device. Figure 5a-5d A method for manufacturing a bidirectional electrostatic protection semiconductor device according to a first embodiment of the present application is introduced.

[0058] like Figure 5a As shown, first, a substrate 201 having a first doping type and a buried layer 202 having a second doping type located above the substrate 201 are formed. Specifically, the substrate 201 is, for example, a P-type doped silicon substrate P-SUB. A buried layer 202 is formed above the substrate 201, and the buried layer 202 is an N-type doped layer structure NBL. Next, an epitaxial layer is formed above the substrate 201, and the epitaxial layer 203 covers the buried layer 202. The epitaxial layer 203 can be N-type doped or P-type doped, and the P-type doped epitaxial layer 203 (P-EPI) is taken as an example here. Then, a well region is implanted along the surface of the epitaxial layer 201 to form a deep N-well region 204 (DPW) having a P-type doping type extending from the surface of the epitaxial layer 203 to the inside and extending to the surface of the buried layer 202, for example, it can be a plurality of deep N-well regions 204 separated from each other.

[0059] Furthermore, if Figure 5bAs shown, a first N-type well region 206 and a second N-type well region 208 having a P-type doping type extending from the surface to the inside and separated from the buried layer 102 are formed in the deep N-well region 204. A first P-type well region 205, a second P-type well region 207 and a third P-type well region 209 having a P-type doping type extending from the surface of the epitaxial layer 203 to the inside and separated from the buried layer 202 are formed.

[0060] Then, if Figure 5c As shown, a plurality of spaced field oxide layers are formed on the upper part and outside of the epitaxial layer 203. Specifically, field oxygen isolation is performed on the surface of the epitaxial layer 203, that is, a plurality of mutually isolated field oxide layers are formed, such as field oxide layer 281, field oxide layer 282, field oxide layer 283, field oxide layer 284, field oxide layer 285, field oxide layer 286 and field oxide layer 287. The field oxide layer is formed by conventional processes, for example, an oxide layer is deposited on the surface of the epitaxial layer 203, a hard mask is deposited, etching is performed using the mask, and finally field oxygen is grown at a high temperature, and then the hard mask is removed. The specific process will not be described in detail.

[0061] Then, if Figure 5d As shown, a first gate layer 231 and a second gate layer 232 are formed, and the first gate layer 231 and the second gate layer 232 may include a polysilicon field plate layer. Then, a plurality of P+ injection regions and N+ injection regions are formed with the plurality of field oxide layers as intervals and are located in each well region. Specifically, P+ or N+ injection is performed in each well region along the gaps of the plurality of field oxide layers to form a plurality of P+ injection regions or N+ injection regions.

[0062] Further, the anode and cathode of the semiconductor device are formed, such as Figure 5d , each injection region is connected by metal to form a cathode and an anode, thereby forming Figure 2 The semiconductor structure shown.

[0063] In addition, the present invention also provides an integrated circuit, which includes the bidirectional electrostatic protection semiconductor device described in any of the above embodiments.

[0064] In summary, the bidirectional electrostatic protection semiconductor device and its manufacturing method and integrated circuit of the embodiment of the present invention are adopted, and the GGNMOS structure is embedded on the basis of the SCR structure, and the avalanche breakdown voltage of the device and the trigger voltage of the device are reduced by the high-concentration source and drain region in the GGNMOS structure. Moreover, by embedding the GGNMOS structure in the areas respectively connected to the anode and the cathode, the first forward current discharge path and the first reverse current discharge path are formed, so that the device has a bidirectional electrostatic protection capability. And the electrostatic protection in both directions can have a lower avalanche breakdown voltage and a holding voltage, thereby improving the electrostatic protection capability of the bidirectional electrostatic protection semiconductor device. Moreover, by the alternating arrangement of the first P-type well region, the first N-type well region, the second P-type well region, the second N-type well region and the third P-type well region and the position setting of the GGNMOS, the device has asymmetry in the layout of the single-finger structure. That is, the discharge paths of the current from the anode to the cathode of the device and from the cathode to the anode are different, and the forward current discharge path and the reverse current discharge path do not overlap. The electric field generated inside the well region is small, the heat generated is small, and the protection performance of the device is good. The bidirectional electrostatic protection semiconductor device can be used under a relatively low working voltage (eg ±5 V). In addition, based on the semiconductor device with a single-finger structure, the device layout can be modified into a double-finger structure or a multi-finger structure to expand the protection range of the semiconductor device.

[0065] Furthermore, a heavily doped buried layer is formed at the bottom of the epitaxial layer of the bidirectional electrostatic protection semiconductor device, so that the current can also pass through the bottom of the semiconductor device through the buried layer. Therefore, on the basis of the original SCR lateral current discharge path (the first forward current discharge path and the first reverse current discharge path), a longitudinal SCR current discharge path (the second forward current discharge path and the second reverse current discharge path) can be formed. The longitudinal SCR current discharge path is close to the bottom of the device, and the current discharge path is long, which can increase the holding voltage of the device. And because the buried layer is heavily doped, the longitudinal SCR current discharge path gradually becomes the dominant current discharge path, realizing current discharge inside the device and avoiding the accumulation of discharge heat on the surface of the device. In addition, the heavily doped buried layer also makes the on-resistance of the longitudinal SCR current discharge path smaller, and the on-resistance of the overall device is reduced by adding the buried layer.

[0066] Furthermore, a P+ injection region and an N+ injection region are arranged near the GGNMOS, and the N+ injection region is connected to the drain region of the GGNMOS through metal. The N+ injection region and the drain region of the GGNMOS are electrically connected to each other to maintain a low avalanche breakdown voltage and a low holding voltage. By setting a P+ injection region with a higher concentration, the doping concentration of the local area below the floating P+ injection region is increased, thereby inhibiting the current from passing through the device surface, that is, inhibiting the discharge current from passing through the lateral SCR current discharge path (the first forward current discharge path and the first reverse current discharge path). The longitudinal SCR current discharge path is further promoted to become the dominant current discharge path, and the on-resistance of the device is further reduced while maintaining a low avalanche breakdown voltage and trigger voltage, and the clamping voltage of the device is reduced, effectively avoiding the risk of premature breakdown of the internal circuit due to excessive clamping voltage.

[0067] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A bidirectional electrostatic protection semiconductor device, comprising: epitaxial layers, stacked on top of the substrate; A first P-type well region, a second P-type well region and a third P-type well region are spaced apart from each other and extend from the surface of the epitaxial layer to the inside thereof and are spaced apart from the substrate; a first N-type well region, located between the first P-type well region and the second P-type well region, and in contact with the first P-type well region; a second N-type well region, located between the second P-type well region and the third P-type well region, and in contact with the second P-type well region; A first MOS structure, located between the first P-type well region and the first N-type well region, includes a first source region, a first drain region and a first gate region; a second MOS structure, located between the second P-type well region and the second N-type well region, comprising a second source region, a second drain region and a second gate region; A first P+ implantation region, distributed on one side of the second P-type well region close to the first N-type well region; as well as A second P+ implantation region is distributed in the third P-type well region, The first P+ injection region, the second source region and the second gate region are all connected to the anode, and the second P+ injection region, the first source region and the first gate region are all connected to the cathode.

2. The bidirectional electrostatic protection semiconductor device according to claim 1, wherein: The first source region is a first N+ injection region, the first drain region is a second N+ injection region, the first N+ injection region is located in the first P-type well region, and the second N+ injection region is located between the first P-type well region and the first N-type well region; The second source region is a third N+ injection region, the second drain region is a fourth N+ injection region, the third N+ injection region is located in the second P-type well region, and the fourth N+ injection region is located between the second P-type well region and the second N-type well region.

3. The bidirectional electrostatic protection semiconductor device according to claim 1, wherein: When the bidirectional electrostatic protection semiconductor device receives an electrostatic pulse of a positive voltage, the thyristor structure consisting of the first P+ injection region, the second P-type well region, the first N-type well region, the first P-type well region and the first source region is turned on to form a first forward current discharge path from the anode to the cathode; When the bidirectional electrostatic protection semiconductor device receives an electrostatic pulse of a negative voltage, the thyristor structure composed of the second P+ injection area, the third P-type well area, the epitaxial layer, the second N-type well area, the second P-type well area and the second source area is turned on to form a first reverse current discharge path from the cathode to the anode.

4. The bidirectional electrostatic protection semiconductor device according to claim 3, further comprising: a buried layer, located at the bottom of the epitaxial layer, in contact with the substrate, and having the same doping type as the first N-type well region and the second N-type well region; A deep N-type well region is located below the first N-type well region and the second N-type well region, connecting the first N-type well region and the second N-type well region to the buried layer, Among them, the doping concentrations of the first source region, the first drain region, the second source region and the second drain region are the highest among all N-type doping regions, and the doping concentration of the buried layer is second only to the doping concentrations of the first source region, the first drain region, the second source region and the second drain region.

5. The bidirectional electrostatic protection semiconductor device according to claim 4, wherein: When the bidirectional electrostatic protection semiconductor device receives an electrostatic pulse of a positive voltage, the thyristor structure consisting of the first P+ injection region, the second P-type well region, the buried layer, the first P-type well region and the first source region is turned on to form a second forward current discharge path from the anode to the cathode; When the bidirectional electrostatic protection semiconductor device receives an electrostatic pulse of negative voltage, the thyristor structure composed of the second P+ injection area, the third P-type well area, the epitaxial layer, the buried layer, the second P-type well area and the second source area is turned on to form a second reverse current discharge path from the cathode to the anode.

6. The bidirectional electrostatic protection semiconductor device according to claim 5, wherein: When the bidirectional electrostatic protection semiconductor device receives an electrostatic pulse of a positive voltage, the first forward current discharge path is opened before the second forward current discharge path, and the current on the first forward current discharge path is smaller than the current on the second forward current discharge path; When the bidirectional electrostatic protection semiconductor device receives an electrostatic pulse of a negative voltage, the first reverse current discharge path is opened before the second reverse current discharge path, and the current on the first reverse current discharge path is smaller than the current on the second reverse current discharge path.

7. The bidirectional electrostatic protection semiconductor device according to claim 1, wherein: The second N-type well region and the third P-type well region are both annular regions, the first P-type well region, the first N-type well region and the second P-type well region are all located inside the annular region formed by the second N-type well region, the annular region formed by the third P-type well region is located outside the annular region formed by the second N-type well region, and the bidirectional electrostatic protection semiconductor device is a single-finger structure.

8. The bidirectional electrostatic protection semiconductor device according to claim 7, further comprising: A third P+ injection region is located in the first P-type well region on a side away from the first N-type well region; A fourth P+ injection region is located on one side of the third P-type well region in the annular region close to the first P-type well region; The field oxide layer is distributed between each N+ injection region and each P+ injection region of the bidirectional electrostatic protection semiconductor device.

9. The bidirectional electrostatic protection semiconductor device according to claim 4, wherein: The deep N-well region below the first N-type well region and the deep N-well region below the second N-type well region are separated from each other.

10. The bidirectional electrostatic protection semiconductor device according to claim 6, further comprising: a fifth P+ implantation region and a fifth N+ implantation region, located inside the first P-type well region and on the same side of the first MOS structure, the fifth N+ implantation region being electrically connected to the first drain region; The sixth P+ implantation region and the sixth N+ implantation region are located inside the second P-type well region and on the same side of the second MOS structure, and the sixth N+ implantation region is electrically connected to the second drain region.

11. A method for manufacturing a bidirectional electrostatic protection semiconductor device, comprising: forming a substrate and an epitaxial layer stacked on the substrate; forming a first P-type well region, a second P-type well region and a third P-type well region extending inward from the surface of the epitaxial layer and spaced apart from the substrate; forming a first N-type well region in contact with the first P-type well region between the first P-type well region and the second P-type well region, and forming a second N-type well region in contact with the second P-type well region between the second P-type well region and the third P-type well region; forming a first MOS structure located between the first P-type well region and the first N-type well region, the first MOS structure including a first source region, a first drain region and a first gate region, and forming a second MOS structure located between the second P-type well region and the second N-type well region, the second MOS structure including a second source region, a second drain region and a second gate region; forming a first P+ implantation region distributed in the second P-type well region and close to one side of the first N-type well region, and a second P+ implantation region distributed in the third P-type well region, The first P+ injection region, the second source region and the second gate region are all connected to the anode, and the second P+ injection region, the first source region and the first gate region are all connected to the cathode.

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