Voltage level converter
By designing a voltage level converter combining multi-transistor and resistive components, the problem of excessive cross-voltage transistors during high voltage conversion in the prior art is solved, and the cross-voltage reduction and component stress avoidance are achieved.
Patent Information
- Application Number
- CN202311128960.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-22
- Filing Date
- 2023-09-04
- Publication Date
- 2025-02-25
AI Technical Summary
When existing voltage level converters convert high voltages to low voltages, they may cause the transverse voltage to be subjected to transistor components exceeding the upper process limit, increasing the stress of the components.
A voltage level converter is designed to control the operating state and impedance of the transistor by using a combination of multiple transistors and resistor elements, thereby reducing the span voltage imposed by the first transistor. The specific implementation includes: the first transistor and the second transistor are medium voltage P-type transistors, the third transistor and the fourth transistor are high voltage P-type transistors, the fifth transistor and the sixth transistor are high voltage N-type transistors, and the voltage is adjusted through the reverse gate and resistor network.
The span voltage applied to the first transistor with a medium voltage is effectively reduced, making it lower than the upper process limit, avoiding the generation of component stress, and simultaneously achieving high voltage to low voltage conversion.
Smart Images
Figure CN119512291A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to voltage level conversion, and more particularly to a voltage level converter for converting a high voltage into a low voltage. Background Art
[0002] Generally speaking, a voltage level converter used to convert a high voltage into a low voltage usually uses a low-voltage transistor element with a lower voltage tolerance at its input stage, which may cause the voltage across the transistor element (e.g., 28.6 volts) to exceed the process upper limit (e.g., 27.5 volts), thereby increasing the element stress. This problem needs to be further resolved. Summary of the invention
[0003] Therefore, the present invention proposes a voltage level converter to effectively solve the above problems encountered in the prior art.
[0004] A preferred specific embodiment according to the present invention is a voltage level converter. In this embodiment, the voltage level converter is used to convert a high voltage into a low voltage. The voltage level converter includes: a first transistor, one end of which is coupled to a first node and a control end of which is controlled by a second input voltage, wherein the first node is coupled to a digital operation voltage; a second transistor, one end of which is coupled to the first node and a control end of which is controlled by a first input voltage, wherein the first input voltage and the second input voltage have opposite polarities; a third transistor, one end of which is coupled to the other end of the first transistor, the other end of which is coupled to a second node and a control end of which is controlled by a reference voltage, wherein the second node is coupled to a second output voltage; a fourth transistor, one end of which is coupled to the other end of the second transistor, the other end of which is coupled to a second node and a control end of which is controlled by a reference voltage, wherein the second node is coupled to a second output voltage; and a fourth transistor, one end of which is coupled to the other end of the second transistor, the other end of which is coupled to a second node and a control end of which is controlled by a reference voltage. The other end is coupled to the third node and its control end is controlled by a reference voltage, wherein the third node is coupled to the first output voltage, wherein the first output voltage and the second output voltage have opposite polarities to each other; a fifth transistor, one end of which is coupled to the second node, the other end of which is coupled to the fourth node, and its control end is coupled to the third node and controlled by the first output voltage; and a sixth transistor, one end of which is coupled to the third node, the other end of which is coupled to the fourth node, and its control end is coupled to the second node and controlled by the second output voltage, wherein the fourth node is coupled to a low-voltage operating voltage and the low-voltage operating voltage is lower than the digital operating voltage.
[0005] In one embodiment, the voltage level converter further includes: a reverse gate coupled between a digital operating voltage and a digital ground voltage, for generating a second input voltage to a control terminal of the first transistor according to a first input voltage, wherein the digital ground voltage is lower than the digital operating voltage and the low voltage operating voltage is lower than the digital ground voltage.
[0006] In one embodiment, the first transistor and the second transistor are P-type transistors with medium voltage, the third transistor and the fourth transistor are P-type transistors with high voltage, and the fifth transistor and the sixth transistor are N-type transistors with high voltage.
[0007] In one embodiment, the substrate terminal of the third transistor, the substrate terminal of the fourth transistor, and the first node are all coupled to the fifth node.
[0008] In one embodiment, the voltage level converter further includes: a first resistor coupled between the second node and the fifth transistor; and a second resistor coupled between the third node and the sixth transistor.
[0009] In one embodiment, the voltage level converter further includes: a seventh transistor, one end of which is coupled to the second node, the other end of which is coupled to the fifth transistor and the control end of which is also coupled to the second node; and an eighth transistor, one end of which is coupled to the third node, the other end of which is coupled to the sixth transistor and the control end of which is also coupled to the third node.
[0010] In one embodiment, the seventh transistor and the eighth transistor are N-type transistors with high voltage.
[0011] In one embodiment, the first input voltage and the first output voltage have opposite polarities and the first input voltage is higher than the first output voltage.
[0012] In one embodiment, the second input voltage and the second output voltage have opposite polarities and the second input voltage is higher than the second output voltage.
[0013] In one embodiment, when the second input voltage transitions to a high potential, the voltage between the first transistor and the third transistor is pulled to a low potential, and the substrate and source of the third transistor with a high voltage are reverse biased, causing the critical voltage value of the third transistor to increase, resulting in the third transistor being turned off due to increased impedance, thereby reducing the cross-voltage borne by the first transistor with a medium voltage. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 FIG. 4 is a schematic diagram of a voltage level converter in a preferred embodiment of the present invention.
[0015] Figure 2 FIG. 4 is a schematic diagram of a voltage level converter in another preferred embodiment of the present invention.
[0016] Figure 3 FIG. 4 is a schematic diagram of a voltage level converter in another preferred embodiment of the present invention.
[0017] Figure 4 FIG. 4 is a schematic diagram of a voltage level converter in another preferred embodiment of the present invention.
[0018] Figure 5 This is a timing diagram of the voltage level converter of the present invention effectively reducing the cross-voltage of the first transistor.
[0019] Description of main component symbols:
[0020] 1…Voltage Level Converter
[0021] 2…Voltage Level Converter
[0022] 3…Voltage Level Converter
[0023] 4…Voltage Level Converter
[0024] M1…first transistor
[0025] M2…Second transistor
[0026] M3…the third transistor
[0027] M4…the fourth transistor
[0028] M5…the fifth transistor
[0029] M6…the sixth transistor
[0030] M7…the seventh transistor
[0031] M8…the eighth transistor
[0032] NOT...Reverse lock
[0033] IP…First input voltage
[0034] IN…Second input voltage
[0035] OUTP…First output voltage
[0036] OUTN…Second output voltage
[0037] DVDD…Digital operating voltage
[0038] DGND…Digital ground voltage
[0039] NAVDD…Low voltage operation
[0040] N1…first node
[0041] N2…Second node
[0042] N3…the third node
[0043] N4…The fourth node
[0044] N5…The fifth node
[0045] VB…reference voltage
[0046] R1…First resistor
[0047] R2…Second resistor
[0048] VDS…cross voltage
[0049] VA…Voltage between the first transistor and the third transistor
[0050] t1…time
[0051] t2…time DETAILED DESCRIPTION
[0052] A preferred embodiment of the present invention is a voltage level converter, which is used to convert a received high voltage into a low voltage and then output it. Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a voltage level converter 1 in this embodiment.
[0053] like Figure 1 As shown, the voltage level converter 1 includes a gate NOT and a first transistor M1 to a sixth transistor M6. The gate NOT is coupled between a digital operating voltage DVDD and a digital ground voltage DGND. A receiving end of the gate NOT receives a first input voltage IP and an output end of the gate NOT is coupled to a control end of the first transistor M1. The gate NOT is used to generate a second input voltage IN to the control end of the first transistor M1 according to the first input voltage IP. The digital ground voltage DGND is lower than the digital operating voltage DVDD and the low voltage operating voltage NAVDD is lower than the digital ground voltage DGND.
[0054] One end of the first transistor M1 is coupled to the first node N1 and its control end is controlled by the second input voltage IN. The first node N1 is coupled to the digital operation voltage DVDD. One end of the second transistor M2 is coupled to the first node N1 and its control end is controlled by the first input voltage IP. The first input voltage IP and the second input voltage IN have opposite polarities.
[0055] One end of the third transistor M3 is coupled to the other end of the first transistor M1, the other end of the third transistor M3 is coupled to the second node N2, and the control end of the third transistor M3 is controlled by the reference voltage VB. The second node N2 is coupled to the second output voltage OUTN. One end of the fourth transistor M4 is coupled to the other end of the second transistor M2, the other end of the third transistor M4 is coupled to the third node N3, and the control end of the third transistor M3 is controlled by the reference voltage VB. The third node N3 is coupled to the first output voltage OUTP. The first output voltage OUTP and the second output voltage OUTN have opposite polarities.
[0056] One end of the fifth transistor M5 is coupled to the second node N2, the other end thereof is coupled to the fourth node N4, and the control end thereof is coupled to the third node N3 and is controlled by the first output voltage OUTP. One end of the sixth transistor M6 is coupled to the third node N3, the other end thereof is coupled to the fourth node N4, and the control end thereof is coupled to the second node N2 and is controlled by the second output voltage OUTN. The fourth node N4 is coupled to the low voltage operation voltage NAVDD, and the low voltage operation voltage NAVDD is lower than the digital operation voltage DVDD.
[0057] It should be noted that the first input voltage IP and the first output voltage OUTP have opposite polarities and are higher than the first output voltage OUTP. The second input voltage IN and the second output voltage OUTN have opposite polarities and are higher than the second output voltage OUTN.
[0058] In practical applications, the first transistor M1 and the second transistor M2 are P-type transistors with medium voltage (MV), the third transistor M3 and the fourth transistor M4 are P-type transistors with high voltage (HV), and the fifth transistor M5 and the sixth transistor M6 are N-type transistors with high voltage (HV), but not limited thereto. For example, the digital operating voltage DVDD is 2.3 to 3.6 volts, the digital ground voltage DGND is 0 volts, and the low voltage operating voltage NAVDD is -20 to -30 volts, but not limited thereto.
[0059] In another embodiment, compared to Figure 1 The voltage level converter 1 in Figure 2 The voltage level converter 2 shown has the following features: the substrate terminal of the third transistor M3, the substrate terminal of the fourth transistor M4 and the first node N1 in the voltage level converter 2 are all coupled to the fifth node N5, that is, the fifth node N5 is also coupled to the digital operating voltage DVDD, but not limited thereto.
[0060] In another embodiment, compared to Figure 2 The voltage level converter 2 in Figure 3 The voltage level converter 3 shown further includes a first resistor R1 and a second resistor R2. The first resistor R1 is coupled between the second node N2 and the fifth transistor M5. The second resistor R2 is coupled between the third node N3 and the sixth transistor M6, but not limited thereto.
[0061] In yet another embodiment, compared to Figure 2 The voltage level converter 2 in Figure 4The voltage level converter 4 shown further includes a seventh transistor M7 and an eighth transistor M8. One end of the seventh transistor M7 is coupled to the second node N2, the other end thereof is coupled to the fifth transistor M5, and the control end thereof is also coupled to the second node N2. One end of the eighth transistor M8 is coupled to the third node N3, the other end thereof is coupled to the sixth transistor M6, and the control end thereof is also coupled to the third node N3. In practical applications, the seventh transistor M7 and the eighth transistor M8 are N-type transistors with high voltage, but are not limited thereto.
[0062] Please also refer to Figure 5 At time t1, the second input voltage IN starts to transition from a low potential (e.g., 0 volts) to a high potential (e.g., 3 volts), and the second output voltage OUTN starts to transition from a high potential (e.g., 3 volts) to a low potential (e.g., -25 volts). At this time, the voltage VA between the first transistor M1 with a medium voltage (MV) and the third transistor M3 with a high voltage (HV) starts to be pulled from a high potential (e.g., 3 volts) to a low potential (e.g., -14.8 volts), so that the substrate and the source of the third transistor M3 are reverse biased, thereby increasing the charge in its depletion region and causing its threshold voltage (VTH) to rise, and the third transistor M3 is turned off due to increased impedance, so that the cross-voltage VDS (e.g., -17.8 volts) borne by the first transistor M1 with a medium voltage (MV) can be reduced to be lower than the process upper limit, but the invention is not limited thereto.
[0063] Compared to the prior art, the voltage level converter proposed in the present invention can convert high voltage into low voltage while reducing the voltage across the first transistor with medium voltage (e.g. -17.8 volts) to be lower than the process upper limit (e.g. 27.5 volts) and effectively avoid the generation of device stress.
Claims
1. A voltage level converter for converting a high voltage into a low voltage, characterized in that: The voltage level converter comprises: A first transistor, one terminal of which is coupled to a first node and a control terminal of which is controlled by a second input voltage, wherein the first node is coupled to a digital operation voltage; A second transistor, one end of which is coupled to the first node and a control end of which is controlled by a first input voltage, wherein the first input voltage and the second input voltage have opposite polarities; A third transistor, one end of which is coupled to the other end of the first transistor, another end of which is coupled to a second node, and a control end of which is controlled by a reference voltage, wherein the second node is coupled to a second output voltage; a fourth transistor, one end of which is coupled to the other end of the second transistor, the other end of which is coupled to a third node, and a control end of which is controlled by the reference voltage, wherein the third node is coupled to the first output voltage, wherein the first output voltage and the second output voltage have opposite polarities; a fifth transistor, one end of which is coupled to the second node, the other end of which is coupled to the fourth node, and a control end of which is coupled to the third node and is controlled by the first output voltage; and A sixth transistor has one end coupled to the third node, another end coupled to the fourth node and a control end coupled to the second node and is controlled by the second output voltage, wherein the fourth node is coupled to a low voltage operation voltage and the low voltage operation voltage is lower than the digital operation voltage.
2. The voltage level converter according to claim 1, wherein: Also includes: The reverse gate is coupled between the digital operating voltage and the digital ground voltage to generate the second input voltage to the control terminal of the first transistor according to the first input voltage, wherein the digital ground voltage is lower than the digital operating voltage and the low voltage operating voltage is lower than the digital ground voltage.
3. The voltage level converter according to claim 1, wherein: The first transistor and the second transistor are P-type transistors with medium voltage, the third transistor and the fourth transistor are P-type transistors with high voltage, and the fifth transistor and the sixth transistor are N-type transistors with high voltage.
4. The voltage level converter according to claim 3, wherein: The substrate terminal of the third transistor, the substrate terminal of the fourth transistor and the first node are all coupled to a fifth node.
5. The voltage level converter according to claim 4, wherein: Also includes: A first resistor is coupled between the second node and the fifth transistor; as well as The second resistor is coupled between the third node and the sixth transistor.
6. The voltage level converter according to claim 4, wherein: Also includes: a seventh transistor, one end of which is coupled to the second node, the other end of which is coupled to the fifth transistor, and the control end of which is also coupled to the second node; as well as An eighth transistor has one terminal coupled to the third node, another terminal coupled to the sixth transistor, and a control terminal also coupled to the third node.
7. The voltage level converter according to claim 6, wherein: The seventh transistor and the eighth transistor are N-type transistors with high voltage.
8. The voltage level converter according to claim 1, wherein: The first input voltage has an opposite polarity to the first output voltage and is higher than the first output voltage.
9. The voltage level converter according to claim 1, wherein: The second input voltage has an opposite polarity to the second output voltage and is higher than the second output voltage.
10. The voltage level converter according to claim 3, wherein: When the second input voltage transitions to a high potential, the voltage between the first transistor and the third transistor is pulled to a low potential, and the substrate and source of the third transistor with a high voltage are reverse biased, causing the critical voltage value of the third transistor to increase, resulting in the third transistor being turned off due to increased impedance, thereby reducing the cross-voltage borne by the first transistor with a medium voltage.