Data storage method, device, and electronic device in direct mode

Abstract

The embodiments of the present application provide a data storage method, device, electronic device and computer-readable storage medium in a pass-through mode, which relates to the field of video transmission technology. The method includes: receiving the pixel value and first address information of a first pixel; determining the first physical storage address of the first pixel in the memory, the first target stripe to which the first pixel belongs, and the target matrix corresponding to the first target stripe; determining the first target address block to which the first physical storage address belongs, the first position of the identifier of the first target address block in the initial address block matrix, and the second position of the first physical storage address in the first target address block; determining the second target address block corresponding to the first position in the target matrix corresponding to the first target stripe, and storing the pixel value of the first pixel in the physical storage address corresponding to the second position in the second target address block. The embodiments of the present application improve the efficiency of data transmission in the pass-through mode and reduce the consumption of physical resources.

Description

Technical Field

[0001] The present application relates to the field of video transmission technology. Specifically, the present application relates to a data storage method, device, electronic device and computer-readable storage medium in a pass-through mode. Background Art

[0002] In traditional video interaction, video data occupies a large amount of backbone bus bandwidth and Double Data Rate SDRAM (DDR) resources. Therefore, direct transmission of video data between the generating and consuming ends without passing through the backbone bus has become a requirement for more and more chips.

[0003] Since the order in which the generator writes data to the memory is different from the order in which the consumer reads data from the memory, the existing video pass-through mode suffers from low video data transmission efficiency and large physical resource usage. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to solve the problems of low efficiency in transmitting video data and large physical resource usage in the prior art video transmission in video pass-through mode.

[0005] According to a first aspect of an embodiment of the present application, a data storage method in a pass-through mode is provided, the method comprising:

[0006] receiving pixel information of a first pixel of a target video sent by a first device, the pixel information including a pixel value and first address information indicating a logical storage address of the first pixel in a memory; wherein a video frame in the target video has a width of w pixels and a height of h pixels, respectively; and each video frame is divided into a plurality of continuous strips having a width of w pixels and a height of m pixels;

[0007] Determining, based on the first address information, a first physical storage address of the first pixel in the memory; wherein the memory includes t*k*m physical storage addresses, and the physical storage addresses of the memory are divided into m*t consecutive address blocks, where t is w / k rounded up; wherein k*m is the number of pixels read by the second device in a single data read operation in the memory, wherein a single data read operation includes m column-wise read operations performed on m rows of pixels, and the number of pixels read in a single column-wise read operation is k pixels in a row;

[0008] determining a first target stripe to which the first pixel belongs;

[0009] Obtain a target matrix corresponding to the first target strip; wherein the target matrix corresponding to the first strip of the target video is an initial address block matrix, and the target matrix corresponding to a non-first strip is a second matrix obtained by performing matrix transformation on the first matrix. The first matrix is ​​the target matrix corresponding to the previous strip, the initial address block matrix is ​​an m*t matrix, and the element values ​​of the m*t elements are identifiers of the m*t address blocks. The second matrix is ​​an m*t matrix obtained by sorting the elements in the transposed matrix of the first matrix in order of the number of rows in which the elements are located, and then sequentially slicing the sorted elements.

[0010] Determine a first target address block to which the first physical storage address belongs in the memory;

[0011] Determine a first position of the identifier of the first target address block in the initial address block matrix and a second position of the first physical storage address within the first target address block;

[0012] A second target address block corresponding to the first position in the target matrix corresponding to the first target stripe is determined, and a pixel value of the first pixel is stored in a physical storage address corresponding to the second position in the second target address block.

[0013] According to a second aspect of an embodiment of the present application, a data storage device in a pass-through mode is provided, the device comprising:

[0014] a receiving module, configured to receive pixel information of a first pixel of a target video sent by a first device, the pixel information including a pixel value and first address information indicating a logical storage address of the first pixel in a memory; wherein a video frame in the target video has a width of w pixels and a height of h pixels, respectively; and each video frame is divided into a plurality of continuous strips having a width of w pixels and a height of m pixels;

[0015] an address translation module, configured to determine, based on the first address information, a first physical storage address of the first pixel in the memory; wherein the memory includes t*k*m physical storage addresses, and the physical storage addresses of the memory are divided into m*t consecutive address blocks, where t is w / k rounded up; and wherein k*m is the number of pixels read by the second device in a single data read operation in the memory, wherein a single data read operation includes m column-wise read operations performed on m rows of pixels, and the number of pixels read in a single column-wise read operation is k pixels in a row;

[0016] A target matrix acquisition module is configured to determine a first target stripe to which the first pixel belongs; and obtain a target matrix corresponding to the first target stripe; wherein the target matrix corresponding to the first stripe of the target video is an initial address block matrix, and the target matrix corresponding to a non-first stripe is a second matrix obtained by performing matrix transformation on the first matrix. The first matrix is ​​the target matrix corresponding to the previous stripe, the initial address block matrix is ​​an m*t matrix, and the element values ​​of the m*t elements are identifiers of the m*t address blocks. The second matrix is ​​an m*t matrix obtained by sorting the elements in the transposed matrix of the first matrix in order of the number of rows in which the elements are located, and then sequentially slicing the sorted elements.

[0017] A storage module is configured to determine a first target address block to which the first physical storage address belongs in a memory; determine a first position of an identifier of the first target address block in the initial address block matrix, and a second position of the first physical storage address within the first target address block; determine a second target address block corresponding to the first position in a target matrix corresponding to the first target stripe, and store a pixel value of the first pixel in a physical storage address corresponding to the second position in the second target address block.

[0018] According to a third aspect of an embodiment of the present application, an electronic device is provided, which includes a memory, a processor, and a computer program stored in the memory, and when the processor executes the program, the steps of the method provided in the first aspect are implemented.

[0019] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method provided in the first aspect are implemented.

[0020] According to the fifth aspect of the embodiment of the present application, a computer program product is provided, which includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. When the processor of a computer device reads the computer instructions from the computer-readable storage medium, the processor executes the computer instructions, so that the computer device performs the steps of implementing the method provided in the first aspect.

[0021] The beneficial effects of the technical solution provided by the embodiments of the present application are:

[0022] By receiving pixel information sent by the first device, a pixel value of the pixel to be stored and first address information of the pixel to be stored are obtained, where the first address information can represent the logical storage address designated for the pixel; based on the first address information, a first physical storage address corresponding to the pixel to be stored in the memory can be determined; by determining the target stripe described by the first pixel in the video, a target matrix corresponding to the target stripe can be determined. Based on the first target address block described by the first physical storage address in the memory and the first position of the first target address block in the initial address block matrix, a second target address block corresponding to the first position in the target matrix can be determined; and based on the first physical storage address at the second position within the first target address block, the pixel to be stored is stored in the second position of the second target address block. Since the target matrix of the non-first strip is obtained after matrix transformation based on the target matrix of the previous strip, the order in which the address blocks in the target matrix of the non-first strip are read by row is the order in which the address blocks in the target matrix of the previous strip are read by column, which ensures that when the pixels to be read are stored in the memory, the pixels at the corresponding positions in the memory have been read by the second device. Therefore, the embodiment of the present application does not require the second device to read all the pixels in the memory before writing the pixels to the memory, thereby improving the efficiency of video data transmission and reducing the space occupied by physical resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments of the present application.

[0024] Figure 1 A schematic diagram of the data storage system architecture in the pass-through mode provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of a flow chart of a data storage method in a direct mode provided in an embodiment of the present application;

[0026] Figure 3 A schematic diagram of stripe size and memory size provided in an embodiment of the present application;

[0027] Figure 4 A schematic diagram of a write rule for a first device and a read rule for a second device provided in an embodiment of the present application;

[0028] Figure 5 A schematic diagram of a matrix conversion process provided in an embodiment of the present application;

[0029] Figure 6 A schematic diagram of a pixel storage process provided in an embodiment of the present application;

[0030] Figure 7A schematic diagram of a logical storage address in a video frame provided in an embodiment of the present application;

[0031] Figure 8 A schematic diagram of a logical storage address in a video frame provided in an embodiment of the present application;

[0032] Figure 9 A schematic structural diagram of a data storage device in a pass-through mode provided in an embodiment of the present application;

[0033] Figure 10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0035] Those skilled in the art will understand that, unless otherwise stated, the singular forms "a", "an", "said", and "the" used herein may also include plural forms. It should be further understood that the terms "including" and "comprising" used in the embodiments of the present application mean that the corresponding features can be implemented as the presented features, information, data, steps, operations, elements, and / or components, but do not exclude implementation as other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the present technical field. It should be understood that when we say that an element is "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element, or it can refer to the element and the other element establishing a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used here can include wireless connection or wireless coupling. The term "and / or" used here indicates at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or as "B", or as "A and B".

[0036] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0037] First, several terms involved in this application are introduced and explained:

[0038] Double Data Rate SDRAM (DDR) is characterized by a large number of traces, high speed, and complex operation. During video interaction, video data will occupy a large amount of backbone bus bandwidth and DDR resources.

[0039] An image signal processor (ISP) is a specialized digital signal processor that processes raw image data captured by a digital camera sensor and converts it into high-quality images. When the ISP writes video data to memory, it writes the data row by row, based on the order of the physical addresses in the memory.

[0040] The Video Processing Unit (VPU) is a new core engine for video processing platforms. It features hardware decoding capabilities and reduces CPU load. Furthermore, the VPU reduces server load and network bandwidth consumption. When reading pixels from memory, the VPU reads all pixels within a pixel block in the memory column by column, following the order of the memory address.

[0041] Static Random-Access Memory (SRAM), SRAM is used to store video data in the embodiment of the present application.

[0042] Video Direct Transfer Scheme (VDTS). In the embodiments of the present application, VDTS is used to represent the video direct transfer scheme in the present application.

[0043] The data storage method, device, electronic device, computer-readable storage medium and computer program product in the direct mode provided in this application are intended to solve the technical problem of low data transmission efficiency caused by the order in which the writing device writes data to the memory and the reading device reads data from the memory in the prior art.

[0044] The following describes several exemplary embodiments to illustrate the technical solutions of the embodiments of the present application and the technical effects produced by the technical solutions of the present application. It should be noted that the following embodiments can refer to, draw on, or combine with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0045] Figure 1 A schematic diagram of the data storage system architecture for implementing a pass-through mode is provided for an embodiment of the present application, wherein a direct frame bridge (DFB) is a circuit function module in the system, which is a hardware module. The circuit function module can be a hardware IP core, which includes a memory. In the embodiment of the present application, the memory is SRAM, and direct pass-through of video data between the ISP and the VPU is achieved through the circuit function module.

[0046] In an embodiment of the present application, the video data includes multiple frame data, each frame data includes multiple strips of data, the storage capacity of the SRAM is the data amount of one strip of data, the first device can be an ISP, the ISP sends the pixel information of the pixels in each strip to the DFB, the processor in the DFB is used to perform logical processing on the address information in the pixel information, determine the physical storage address where the pixel is stored in the memory, and store the pixel in the physical address corresponding to the memory. The second device can be a VPU. When the VPU reads the pixel from the memory, it also sends the address information of the read pixel to the DFB. After the processor performs logical processing on the address information, it determines the corresponding physical storage address in the DFB and sends the pixel stored in the physical address to the second device.

[0047] The data storage system in pass-through mode in the embodiments of the present application solves the problem that, in conventional video transmission systems that store data via DDR, video data occupies a large amount of backbone bus bandwidth and DDR resources, leading to system performance bottlenecks and affecting data processing speed and response time. Furthermore, other system components that use backbone bus and DDR resources may not be able to obtain sufficient resources due to the resources being occupied by video data, resulting in performance degradation.

[0048] On the other hand, the embodiment of the present application performs logical processing on the received address information through the processor, thereby solving the problem of low data transmission efficiency caused by the different order in which the first device writes pixels to the memory and the second device reads pixels from the memory.

[0049] The present application provides a method for storing data in a direct mode. Figure 2 As shown, the method includes steps S201-S207.

[0050] S201. Receive pixel information of a first pixel of a target video sent by a first device, where the pixel information includes a pixel value and first address information indicating a logical storage address of the first pixel in a memory.

[0051] In an embodiment of the present application, the first device may be an image signal processor (ISP), which corresponds to a device for acquiring video, such as a camera. The target video may be a video acquired by the device for acquiring video corresponding to the ISP, or may be a video acquired by the device after the ISP performs image processing on the video acquired by the device. The data format of the target video may be YUV format, and the target video may be composed of multiple consecutive video frames. The process of storing the pixel value of a pixel sent by the ISP in a memory may also be referred to as the ISP writing a pixel to the memory.

[0052] When the ISP writes pixels to the memory, it scans the pixels in each video frame row by row, following the order of the video frames, obtains pixel values, and assigns a logical storage address in the memory to each pixel. In this embodiment of the present application, the first pixel is any pixel in the target video. The pixel information of the first pixel sent by the ISP to the DFB includes the pixel value of the first pixel and first address information, where the first address information is used to indicate the logical storage address corresponding to the first pixel.

[0053] In this embodiment of the present application, the ISP can assign a logical storage address to each pixel in each video frame based on the starting address of the physical storage addresses of the data stored in the memory. That is, in this embodiment of the present application, the logical storage address corresponding to the pixel in the first row and first column of each video frame corresponds to the first physical storage address in the memory.

[0054] S202: Determine a first physical storage address of a first pixel in a memory according to the first address information.

[0055] In the embodiment of the present application, after the processor in the DFB receives the first address information of the first pixel, it can determine the first physical storage address of the first pixel in the memory according to the preset correspondence between the logical storage address and the physical storage address.

[0056] In an embodiment of the present application, the memory is designed according to the rules for storing pixels of the first device and the rules for reading pixels of the memory. The memory includes w*m physical storage addresses, w is the number of pixels corresponding to the width of the video frame corresponding to the first device, m is the number of pixel blocks read corresponding to the first data reading operation of the second device, and each pixel block includes at least k pixels, where k is a parameter for reading pixels preset by the second device, and k is generally 32. It should be understood that if w is not an integer multiple of k, the number of pixels in the last pixel block of each row read by the second device is less than k. For convenience of expression, the pixel block including k pixels is called a standard pixel block. When w is a multiple of k, each pixel block is a standard pixel block.

[0057] In the embodiment of the present application, a video frame is divided into at least one strip of data, the height of the video frame is h pixels, and the video frame is divided into multiple continuous strips with a width of w pixels and a height of m pixels. Figure 3 As shown, Figure 3 A schematic diagram of a stripe size and memory size provided in an embodiment of the present application is provided. Figure 3In the example, w is an integer multiple of k, and h is less than or equal to 2*m, so the video frame is divided into two strips, the height of the first strip is m pixels, and the height of the second strip is hm pixels. It should be understood that if h is less than or equal to n*m, and n is any positive integer, then the video frame includes n strips, and the height of the first n-1 strips is m pixels and the width is w pixels. The height of the nth strip is h-(n-1)m pixels and the width is w pixels. For the convenience of expression, the strip with a width of w pixels and a high order of m pixels is called a standard strip. It can be seen from the strip division and pixel block division in this application that this application has no restrictions on the width and height of the target video and can transmit target videos corresponding to any resolution.

[0058] from Figure 3 It can also be seen that when w is a multiple of k, the memory includes w*m physical storage addresses. Therefore, one memory in the embodiment of the present application corresponds to the number of pixels corresponding to a standard strip. Therefore, the memory in the embodiment of the present application can store the pixels in the standard strip. If the number of pixels in the last strip in the video frame is less than or equal to the standard strip, the memory can also store all the pixels in the last strip.

[0059] It should be understood that when w is not a multiple of k, the number of physical storage addresses of the memory is greater than the number of pixels in the stripe, so the memory can also store the pixel values ​​of all pixels in the stripe.

[0060] like Figure 4 As shown, Figure 4 A schematic diagram of a write rule for a first device and a read rule for a second device provided in an embodiment of the present application. Figure 4 In the figure, w takes the value of 4, m takes the value of 2, h takes the value of 4, and the number of pixels in the pixel block read by the second device is 1. The video frame includes two stripes, AP is the pixel value, the memory includes 8 physical storage addresses, and 0-7 are the physical storage addresses in the memory. For the first stripe, the ISP write rule is as shown in the figure, scanning the pixel value of each pixel by row, and the physical storage address corresponding to pixel A is 0, the physical storage address corresponding to pixel B is 1, and so on, until the physical storage address corresponding to H is 7, entering the second stripe, the physical storage address corresponding to I is 0, the physical storage address corresponding to J is 1, and so on, until the physical storage address corresponding to P is 7. The VPU reads the pixels in each physical storage address in the memory by column. After pixels A to H are stored in the memory, the reading order of the VPU is as shown in the figure.

[0061] Therefore, after the ISP finishes writing the pixel values ​​of the first strip to the memory, the VPU reads the pixel values. At this time, if the ISP continues to read the pixel values ​​of the second strip from the memory, for example, pixel J, since the physical storage address corresponding to pixel J is 1, and the VPU first reads pixel E at address 4, pixel B at address 1 is replaced by the newly written pixel J before being read by the VPU. In this case, it is necessary to wait for the VPU to finish reading the pixel values ​​of one strip before the ISP writes the pixel values ​​of the next strip to the memory. However, this processing method has the problem of low video transmission efficiency. Therefore, the present application improves the transmission efficiency of video data by changing the physical storage address corresponding to the pixel through the following steps.

[0062] S203, determining a first target stripe to which the first pixel belongs;

[0063] S204: Obtain a target matrix corresponding to the first target stripe.

[0064] In an embodiment of the present application, a logical storage address of the first pixel can be determined based on the first address information of the first pixel, and the first target stripe corresponding to the first pixel in the target video can be determined based on the logical storage address of the first pixel. The ISP can assign a different logical storage address to each pixel in the target video, and the memory determines the stripe number of the target video to which the first pixel belongs based on the logical storage address corresponding to each pixel.

[0065] As an optional embodiment, the ISP can set the logical storage address corresponding to the first pixel of the video frame to the physical storage address of the memory, combined with Figure 4 , the logical storage address of pixel A is 0, the logical storage address of pixel B is 1, and in this order, the logical storage address of pixel P is 15. The memory can determine how many times the first address information has been received, thereby determining the video frame to which the first pixel belongs, and then determining the first target stripe corresponding to the first pixel based on the width and height of a standard stripe.

[0066] In an embodiment of the present application, the physical storage addresses in the memory are divided into m*t consecutive address blocks, where t is w / k rounded up, so each address block corresponds to at least k physical storage addresses. For convenience of expression, the address block including k physical storage addresses is called a standard address block. Only the last address block of each row in the memory may not be a standard address block, and each address block stores the pixel value in a pixel block.

[0067] In an embodiment of the present application, each strip corresponds to a target address block, and the target matrix corresponding to the first strip of the target video is the initial address block matrix. The elements in the initial address block matrix are identifiers of the address blocks in the memory, that is, the initial address block matrix is ​​a matrix of m rows and t columns, and the element value of each element is the identifier of an address block. It should be understood that the position of the address block in the memory is the same as the position of the identifier of the address block in the initial address block matrix.

[0068] In an embodiment of the present application, the target matrix of the non-first strip of the target video is obtained by matrix transformation of the target matrix of the previous strip of the strip. Specifically, the target matrix of the previous strip of the strip is used as the first matrix, the transposed matrix of the first matrix is ​​obtained, the elements in the transposed matrix are arranged in the order of the number of rows in which the elements are located, the arranged matrix is ​​divided into m*t matrices, the divided matrix is ​​used as the second matrix, and the second matrix is ​​used as the target matrix of the strip. It should be noted that the previous strip of the first strip data of the non-first video frame in the target video is the last strip of the previous video frame, that is, the target video of the present application is composed of continuous strip data.

[0069] like Figure 5 As shown, Figure 5 A schematic diagram of a matrix conversion process provided in an embodiment of the present application. Taking t as 4 and m as 2 as an example, 0-8 are identifiers of corresponding address blocks, where matrix A is the first matrix. Matrix A is first transposed to obtain the transposed matrix of matrix A, i.e., matrix B. Matrix B is expanded row by row to obtain matrix C. Matrix C is then divided into 4 units to obtain matrix D. It can be seen that matrix D and matrix A are both matrices with 2 rows and 4 columns.

[0070] S205: Determine a first target address block to which the first physical storage address belongs in the memory.

[0071] In an embodiment of the present application, the memory includes multiple address blocks, each address block includes multiple physical storage addresses, and for each physical storage address, the processor can determine the address block described by the physical storage address, and thus can determine the first target address block to which the first physical storage address belongs in the memory.

[0072] S206: Determine a first position of the identifier of the first target address block in the initial address block matrix, and a second position of the first physical storage address within the first target address block;

[0073] S207 : Determine a second target address block corresponding to the first position in the target matrix corresponding to the first target stripe, and store the pixel value of the first pixel in a physical storage address corresponding to the second position in the second target address block.

[0074] In an embodiment of the present application, after determining the first target address block corresponding to the first physical address, the identifier of the first target address block is obtained, and the identifier of the first target address block is found from the initial address block matrix. The position of the identifier of the first target address block in the initial address block can be determined. The position can be the row number and column number of the identifier in the initial address block matrix, and the position is recorded as the first position.

[0075] In an embodiment of the present application, when the processor determines the first target matrix to which the first physical storage address belongs, it can also determine the position of the first physical storage address in the first target address block. The position can be the nth physical storage address of the first physical storage address in the first target address block, and the position is recorded as the second position.

[0076] In an embodiment of the present application, after obtaining the first position, the processor determines the address block identifier corresponding to the first position in the target matrix corresponding to the first target strip, and uses the address block corresponding to the address block identifier as the second target address block. The pixel value of the first pixel is stored in the physical storage address corresponding to the second position in the second target address block, and the physical storage address corresponding to the second position is used as the third physical storage address. The processor implements the address conversion from the first physical storage address to the physical storage address of the third position.

[0077] like Figure 6 As shown, Figure 6 A schematic diagram of a pixel storage process provided by an embodiment of the present application. Taking k as an example, a physical storage address corresponds to an address block, and the identifier of the physical storage address is used as the address block identifier. The video frame is the first video frame of the target video. For the first stripe, the target matrix of the stripe is the initial address block matrix. At this time, according to the pixel information sent by the ISP, it is stored in the memory row by row to obtain the memory storage result of the first stripe. According to the VPU reading order described above, the VPU will read the pixels in the memory in the order of AEBFCGDH. When the ISP writes the pixel value of the second stripe, the processor will convert the storage address of the pixel value according to the target matrix of the second stripe. For example, for pixel J, the original physical storage address of the pixel is 1, and 1 is the physical storage address in the address block 1 of the memory. Address block 1 is the first target address block. Therefore, the position of identifier 1 in the initial address block matrix is ​​determined, that is, the first row and second column. Then, the identifier at this position in the target matrix of the second stripe is determined, that is, identifier 4. At this time, it is determined that pixel J is stored in address block 4. Address block 4 is the second target address block. There is only one physical storage address in address block 4, that is, address 4. Therefore, pixel J is stored in the physical storage address 4 of the memory. The storage results of other pixels in the second stripe are obtained similarly.

[0078] It can be seen that the order in which the pixel values ​​of the second strip are stored in the addresses is consistent with the order in which the pixel values ​​of the first strip read in sequence by the VPU are located. Therefore, this application does not need to wait for the VPU to read all the data of the previous strip before storing the data of the current strip in the memory, thereby improving the transmission efficiency of video data.

[0079] As an optional embodiment, the identifier of the address block can be the high-order address of each physical storage address in the address block, and the second position of each physical storage address in the address block is the low-order address of each physical storage address block. The high-order addresses of the physical storage addresses in different address blocks in the memory are different, and the high-order addresses of the physical storage addresses in the same address block are the same but the low-order addresses are different. Therefore, the present application only needs to perform address conversion on the high-order address of the first physical storage address of the first pixel, and then splice the high-order address obtained after conversion with the low-order address of the first physical address to obtain the second physical storage address.

[0080] In an embodiment of the present application, by receiving pixel information sent by a first device, a pixel value of a pixel to be stored, i.e., a first pixel, and first address information of the pixel to be stored are obtained, where the first address information can represent a logical storage address designated for the pixel; by analyzing the first address information, a first physical storage address corresponding to the pixel to be stored in a memory can be determined; and by determining a first target strip to which the first pixel belongs in a target video, a target matrix corresponding to the first target strip can be determined.

[0081] Based on the first target address block described by the first physical storage address in the memory and the first position of the first target address block in the initial address block matrix, the second target address block corresponding to the first position in the target matrix can be determined, and the pixel to be stored is stored in the second position of the second target address block based on the second position of the first physical storage address within the first target address block.

[0082] Since the target matrix of the non-first strip is obtained after matrix transformation based on the target matrix of the previous strip, the order in which the address blocks in the target matrix of the non-first strip are read by row is the order in which the address blocks in the target matrix of the previous strip are read by column, which ensures that when the pixels to be read are stored in the memory, the pixels at the corresponding positions in the memory have been read by the second device. Therefore, the embodiment of the present application does not require the second device to read all the pixels in the memory before writing pixels to the memory, thereby improving the efficiency of video data transmission.

[0083] As an optional embodiment of the present application, the data storage method in the pass-through mode further includes:

[0084] When the pixel values ​​of all pixels belonging to the same stripe are stored in the memory, the value of the first parameter in the first record table is increased by 1, and the value of the first parameter represents the number of stripes that have been stored;

[0085] Determining a first target stripe to which the first pixel belongs includes:

[0086] Get the first record table;

[0087] A first target stripe to which the first pixel belongs in the target video is determined according to a value of the first parameter in the first record table.

[0088] In an embodiment of the present application, the processor in the DFB records the number of stripes read from the memory, and can record the number in a first record table, and set a first parameter in the first record table to indicate the number of stripes read.

[0089] In an embodiment of the present application, after storing the last pixel of a stripe, the processor may increment the value of the first parameter in the first record table by 1. As an optional embodiment, when the first physical storage address corresponding to the first address information of the first pixel is the last physical storage address of the memory, the first pixel is determined to be the last pixel of the stripe to which the pixel belongs; or, after determining that the first pixel is the first pixel of the stripe to which the pixel belongs, the processor increments the value of the first parameter in the first record table by 1, and when the first physical storage address corresponding to the first address information of the first pixel is the first physical storage address of the memory, the first pixel is determined to be the first pixel of the stripe to which the pixel belongs.

[0090] In the embodiment of the present application, after receiving the pixel information of the first pixel, the processor can determine the stripe number of the first pixel in the target video according to the first parameter in the first record table.

[0091] As an optional embodiment, the processor may further determine, based on the first physical storage address corresponding to the first pixel, the number of times the first physical storage address is received, and determine the stripe to which the first pixel belongs in the target video.

[0092] In the embodiment of the present application, by recording the number of strips stored in the memory, the first target strip to which the first pixel belongs in the target video can be effectively determined, thereby further determining the target matrix of the first target strip.

[0093] As an optional embodiment of the present application, for a non-first strip of the target video, the target matrix corresponding to the strip is obtained by:

[0094] Obtain a target matrix corresponding to a previous strip, and use the target matrix corresponding to the previous strip as a first matrix;

[0095] After sorting the elements in the transposed matrix of the first matrix in the order of the row numbers corresponding to the rows where the elements are located, the m*t matrices obtained by slicing the sorted elements are used as the second matrix;

[0096] The second matrix is ​​used as a target matrix corresponding to the first target stripe to which the first pixel belongs.

[0097] As an optional embodiment of the present application, when pixel information of the first pixel of a non-first strip is received, a matrix transformation is performed on a target matrix of a strip preceding the non-first strip to obtain a target matrix of the non-first strip.

[0098] In an embodiment of the present application, the processor can determine that the first pixel is the first pixel of a non-first strip based on the first physical storage address corresponding to the first pixel, which is the first physical storage address in the memory, and the strip to which the first pixel belongs is a non-first strip of the target video. At this time, the processor can obtain the target matrix of the previous strip as the first matrix, perform the above matrix conversion on the first matrix, obtain the second matrix, and use the second matrix as the target matrix of the first target strip to which the first pixel belongs.

[0099] In the embodiment of the present application, by determining that the first pixel is the first pixel of a non-first strip of the target video, it is determined that a matrix conversion operation needs to be performed, which is conducive to determining the target matrix corresponding to the first target strip.

[0100] As an optional embodiment, the present application may also pre-generate target matrices corresponding to respective strips in the target video, thereby improving the transmission efficiency of the processor during video transmission.

[0101] As an optional embodiment, determining a first physical storage address of the first pixel in a memory according to the first address information includes:

[0102] determining a first address offset between a logical storage address of a first pixel and a logical storage address of a first pixel in a first target stripe to which the first pixel belongs;

[0103] A first physical storage address of the first pixel in the memory is obtained according to the first address offset and the first physical storage address of the memory, wherein the address offset of the first physical storage address relative to the first physical storage address of the memory is equal to the first address offset.

[0104] In an embodiment of the present application, a processor receives first address information of a first pixel, where the first address information represents a logical storage address of the first pixel. The processor may obtain the logical storage address of the first pixel of a first target stripe to which the first pixel belongs, and determine a first address offset, where the first address offset represents an address offset between the first pixel and the first pixel of the first target stripe.

[0105] The processor can determine the first physical storage address based on the first address offset and the first physical storage address in the memory. It should be understood that the ISP is each pixel within a strip scanned row by row, and the position of each pixel within the strip corresponds to the position of the first physical storage address corresponding to each pixel in the memory. For example, if the first pixel is located in the second row and second column in the strip, the first physical storage address is also located in the second row and second column in the memory.

[0106] By determining the logical storage address of the first pixel of the first target strip to which the first pixel belongs, the relative positional relationship between the first pixel and the first pixel can be determined. Then, since the first pixel corresponds to the first physical storage address in the memory, the physical storage address having the relative positional relationship is determined to be the first physical storage address corresponding to the first pixel.

[0107] like Figure 7 As shown, Figure 7 A schematic diagram of the logical storage address in a video frame provided by an embodiment of the present application. Wherein, w=4, k=2, i.e., w is an integer multiple of k. As can be seen from the figure, for pixel G, the logical storage address of the pixel is 6, the first pixel of the strip to which the pixel belongs is pixel A, and the logical storage address of pixel A is 0, then the first address offset is 6. Combined with the first physical storage address of the memory being 0, the first physical storage address to pixel G is address 6; for pixel O, the logical storage address of the pixel is 14, the first pixel of the strip to which the pixel belongs is pixel I, and the logical storage address of pixel I is 8, then the first address offset is 6. Combined with the first physical storage address of the memory being 0, the first physical storage address of pixel O is 6.

[0108] To further illustrate the logical storage address of each pixel in the video frame when w is not an integer multiple of k, such as Figure 8 As shown, Figure 8Another schematic diagram of the logical storage address in a video frame provided for an embodiment of the present application. Wherein w is not an integer multiple of k, k=2, w=3, in this case, the first device will specify the logical storage address of the pixel according to the size of the k value and the width of the video frame, so that the position of the pixel in the strip is aligned with the position of the physical storage address in the memory corresponding to the pixel. For example, for the first address information used to represent the logical storage address 3, the first physical storage address corresponding to the address is the address of the first row and fourth column in the memory, and the pixel d is the pixel in the second row and first column. Therefore, when the first device executes the logical storage address of pixel d, the logical storage address 3 will be left blank and the logical storage address of pixel d will be specified as 4.

[0109] In the embodiment of the present application, the first physical storage address of the first pixel is determined by determining the first address offset between the first pixel and the first pixel in the strip to which it belongs.

[0110] As an optional embodiment of the present application, determining a first address offset between a logical storage address of a first pixel and a logical storage address of a first pixel in a first target stripe to which the first pixel belongs includes:

[0111] Determining an intra-frame address offset of a logical storage address of the first pixel relative to a logical storage address of a first pixel of a corresponding video frame, wherein the logical storage address of the first pixel of each video frame corresponds to a first physical storage address of the memory;

[0112] determining, according to the number of physical storage addresses in the memory, an intra-frame address offset of a first pixel in a strip to which the first pixel belongs;

[0113] The first address offset is determined according to the intra-frame address offset of the first pixel and the intra-frame address offset of the first pixel in the strip to which the first pixel belongs.

[0114] In an embodiment of the present application, the ISP corresponds the logical storage address of the first pixel in each video frame to the first physical storage address of the memory, and the DFB pre-stores the correspondence between the logical storage address and the first physical storage address of the pixel in the first row and first column of each video frame. The ISP and VPU can also obtain this correspondence in advance. Therefore, after the processor receives the first address information of the first pixel, it obtains the logical storage address specified by the ISP for the first pixel. Since the logical storage address of the first pixel of the video frame to which the first pixel belongs is determined, the intra-frame address offset of the first pixel can be obtained, where the intra-frame address offset is used to represent the relative position of the first pixel relative to the first pixel of the video frame to which it belongs.

[0115] In an embodiment of the present application, the processor can determine the intra-frame address offset of the first pixel in the strip to which the first pixel belongs based on the number of physical storage addresses t*k*m in the memory, that is, the number of pixels in a standard strip. The processor can determine the first address offset based on the difference between the intra-frame address offset of the first pixel and the intra-frame address offset of the first pixel in the first target strip. It should be understood that the intra-frame address offset of the first pixel is used to indicate the relative position of the first pixel relative to the first pixel of the video frame, and the intra-frame address offset of the first pixel of the first target strip is used to indicate that the first pixel of the first target strip is equivalent to the relative position of the first pixel of the video frame. Therefore, based on the difference between the intra-frame address offset of the first pixel and the intra-frame address offset of the first pixel in the first target strip, the relative position of the first pixel relative to the first pixel of the first target strip, that is, the first address offset, can be determined.

[0116] like Figure 7 As shown in , for pixel O, the intra-frame address offset of the pixel is 14. According to the number of physical storage addresses of the memory 8, and 8<14<16, the logical storage address of the first pixel I of the strip to which pixel O belongs is 8, and the intra-frame address offset of pixel I is 8. Therefore, the first address offset of pixel I is 6.

[0117] like Figure 8 As shown in , for pixel j, the intra-frame address offset of the pixel is 12. According to the number of physical storage addresses of the memory 8, and 8<12<16, the logical storage address of the first pixel g in the strip to which pixel j belongs is 8, and the intra-frame address offset of pixel g is 8. Therefore, the first address offset of pixel j is 4.

[0118] In an embodiment of the present application, the relative position of the first pixel within the frame is determined by determining the intra-frame address offset of the first pixel, and the relative position of the first pixel within the frame is determined by determining the intra-frame address offset of the first pixel of the strip to which the first pixel belongs, thereby determining the relative position of the first pixel within the strip.

[0119] As an optional embodiment of the present application, the data storage method in the pass-through mode further includes:

[0120] receiving a pixel read request sent by a second device, where the pixel read request includes second address information of logical storage addresses of k pixels to be read;

[0121] Determining a second physical storage address of each of the k pixels in the memory according to the second address information;

[0122] Determining a second target stripe corresponding to the pixel read request, and determining a target matrix corresponding to the second target stripe;

[0123] Determine a third target address block to which the k second physical storage addresses belong in the memory;

[0124] Determining a third position of an identifier of a third target address block in the initial address matrix;

[0125] Determine a third target address block corresponding to a third position in the target matrix corresponding to the second target stripe, and send k pixel values ​​in the third target address block to the second device.

[0126] In the embodiment of the present application, the VPU reads pixels in a block manner. When the VPU sends a pixel read request to the DFB, the pixel read request includes second address information of the logical storage addresses of k pixels.

[0127] In the embodiment of the present application, the DFB processor can determine the second physical storage address corresponding to each pixel based on the second address information of each pixel. For ease of understanding, each pixel to be read is referred to as a second pixel. The processor can determine the second physical storage address corresponding to each second pixel in the same manner as it determines the first physical storage address corresponding to the first pixel. It should be understood that each second pixel is a pixel stored in the same address block.

[0128] In an embodiment of the present application, the processor also needs to determine the second target stripe corresponding to each second pixel and the target matrix corresponding to the second target stripe. As an optional embodiment, the processor can record the number of stripes read and use the number of stripes read as the second parameter in the first record table. When the processor sends the pixels of the last address block in the memory to the second device, the second parameter can be incremented by 1; or when the processor determines that the address block corresponding to the pixel read request is the first address block, the second parameter is incremented by 1.

[0129] In an embodiment of the present application, the processor may determine the third target block address described in the memory by the k second physical storage addresses (it should be understood that the k second physical storage addresses correspond to the same address block in the memory), then determine the third position of the identifier of the third address block in the initial address block matrix, determine the identifier corresponding to the third position in the target matrix corresponding to the second target stripe, determine the fourth target address block corresponding to the identifier, sequentially send each pixel in the fourth target address block to the second device according to the fourth position of each pixel in the fourth target address, and use the physical storage address corresponding to the fourth position as the fourth physical storage address, that is, the processor implements the address conversion from the second physical storage address to the fourth physical address.

[0130] In the embodiment of the present application, when the second device reads the pixel, the second physical storage address corresponding to each pixel is also converted, so that the pixel storage and reading processes undergo the same address conversion, ensuring that the pixels read by the VPU are correct, thereby ensuring the normal transmission of video data. In the embodiment of the present application, there is no need to change the writing and reading rules originally set by the ISP and VPU. Through two corresponding address conversions, video pass-through with high data transmission efficiency can be achieved through a memory of the same size as the stripe data.

[0131] The comparison results of the data storage solution in the pass-through mode in this application and the data storage solution of a memory with twice the area of ​​the sample are shown in Table 1. Among them, the experimental environment is based on TSMC cln16, the video resolution is 4K, and the stripe height is 64 lines. Among them, the area index is the area of ​​the memory, which is used to represent the capacity of the memory. The solution before optimization is to use a memory with twice the capacity of the stripe data, which is used to read the data of one stripe when the VPU reads the data of one stripe. The ISP can continue to store the pixels of another stripe in another storage space. It is also used to solve the problem that the ISP can continue to write the stripe data only after the VPU reads all the data of a stripe. The optimized solution is the solution provided in this application. It can be clearly seen from the area yield and the static power consumption yield that the video storage solution in the pass-through mode provided in the embodiment of the present application occupies less storage resources and generates lower power consumption.

[0132] Table 1 Comparison of benefits of different video direct solutions

[0133]

[0134] Figure 9 A schematic diagram of a data storage device in a pass-through mode according to an embodiment of the present application is shown in FIG. Figure 9 As shown, the apparatus of this embodiment may include: a receiving module 901 , an address translation module 902 , a target matrix acquisition module 903 and a storage module 904 .

[0135] A receiving module 901 is configured to receive pixel information of a first pixel of a target video sent by a first device, the pixel information including a pixel value and first address information indicating a logical storage address of the first pixel in a memory; wherein a video frame in the target video has a width of w pixels and a height of h pixels, respectively; and each video frame is divided into a plurality of continuous strips having a width of w pixels and a height of m pixels;

[0136] An address translation module 902 is configured to determine, based on the first address information, a first physical storage address of the first pixel in the memory; wherein the memory includes t*k*m physical storage addresses, and the physical storage addresses of the memory are divided into m*t consecutive address blocks, where t is w / k rounded up; wherein k*m is the number of pixels read by the second device in a single data read operation in the memory, wherein a single data read operation includes m column-wise read operations performed on m rows of pixels, and the number of pixels read in a single column-wise read operation is k pixels in a row;

[0137] The target matrix acquisition module 903 determines the first target stripe to which the first pixel belongs; and obtains a target matrix corresponding to the first target stripe; wherein the target matrix corresponding to the first stripe of the target video is the initial address block matrix, and the target matrix corresponding to the non-first stripe is a second matrix obtained by performing matrix transformation on the first matrix. The first matrix is ​​the target matrix corresponding to the previous stripe, the initial address block matrix is ​​an m*t matrix, and the element values ​​of the m*t elements are identifiers of the m*t address blocks. The second matrix is ​​an m*t matrix obtained by sorting the elements in the transposed matrix of the first matrix in order of the number of rows in which the elements are located, and then sequentially slicing the sorted elements.

[0138] The storage module 904 is configured to determine a first target address block to which the first physical storage address belongs in the memory; determine a first position of an identifier of the first target address block in the initial address block matrix, and a second position of the first physical storage address within the first target address block; determine a second target address block corresponding to the first position in the target matrix corresponding to the first target stripe, and store the pixel value of the first pixel in the physical storage address corresponding to the second position in the second target address block.

[0139] As an optional embodiment of the present application, the data storage device in the pass-through mode further includes:

[0140] a recording module, configured to add 1 to the value of a first parameter in the first recording table when the pixel values ​​of all pixels belonging to the same stripe are stored in the memory, the value of the first parameter representing the number of stripes that have been stored;

[0141] When used to determine the first target stripe to which the first pixel belongs, the target matrix acquisition module 903 is specifically configured to:

[0142] Obtaining the first record table;

[0143] A first target stripe to which the first pixel belongs in the target video is determined according to a value of the first parameter in the first record table.

[0144] As an optional embodiment of the present application, the target matrix acquisition module 903 is further configured to:

[0145] Obtain a target matrix corresponding to a previous strip, and use the target matrix corresponding to the previous strip as a first matrix;

[0146] After sorting the elements in the transposed matrix of the first matrix in the order of the row numbers corresponding to the rows where the elements are located, the m*t matrices obtained by slicing the sorted elements are used as the second matrix;

[0147] The second matrix is ​​used as a target matrix corresponding to a first target stripe to which the first pixel belongs.

[0148] As an optional embodiment of the present application, the target matrix acquisition module 903 is further configured to perform matrix transformation on the target matrix of the previous strip of the non-first strip when receiving pixel information of the first pixel of the non-first strip, to obtain the target matrix of the non-first strip.

[0149] As an optional embodiment of the present application, when the address translation module 902 is used to determine the first physical storage address of the first pixel in the memory according to the first address information, it is specifically used to:

[0150] determining a first address offset between a logical storage address of a first pixel and a logical storage address of a first pixel in a first target stripe to which the first pixel belongs;

[0151] A first physical storage address of the first pixel in the memory is obtained according to the first address offset and a first physical storage address of the memory, wherein an address offset of the first physical storage address relative to the first physical storage address of the memory is equal to the first address offset.

[0152] As an optional embodiment of the present application, when determining a first address offset between the logical storage address of a first pixel and the logical storage address of a first pixel in a first target stripe to which the first pixel belongs, the address translation module 902 is specifically configured to:

[0153] Determining an intra-frame address offset of a logical storage address of the first pixel relative to a logical storage address of a first pixel of a corresponding video frame, wherein the logical storage address of the first pixel of each video frame corresponds to a first physical storage address of the memory;

[0154] determining, according to the number of physical storage addresses in the memory, an intra-frame address offset of a first pixel in the strip to which the first pixel belongs;

[0155] The first address offset is determined according to the intra-frame address offset of the first pixel and the intra-frame address offset of the first pixel in the strip to which the first pixel belongs.

[0156] As an optional embodiment of the present application, the receiving module 901 is further configured to receive a pixel read request sent by a second device, where the pixel read request includes second address information of the logical storage addresses of k pixels to be read;

[0157] The address translation module 902 is further configured to determine a second physical storage address of each of the k pixels in the memory according to the second address information;

[0158] The target matrix acquisition module 903 is further configured to determine a second target stripe corresponding to the pixel read request, and determine a target matrix corresponding to the second target stripe;

[0159] The storage module 904 is also used to determine the third target address block to which the k second physical storage addresses belong in the memory; determine the third position of the identifier of the third target address block in the initial address matrix; determine the fourth target address block corresponding to the third position in the target matrix corresponding to the second target stripe, and send the k pixel values ​​in the fourth target address block to the second device.

[0160] The device of the embodiment of the present application can execute the method provided by the embodiment of the present application, and its implementation principle is similar. The actions performed by each module in the device of each embodiment of the present application correspond to the steps in the method of each embodiment of the present application. For the detailed functional description of each module of the device, please refer to the description in the corresponding method shown in the previous text, and will not be repeated here.

[0161] In an embodiment of the present application, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of a data storage method in a pass-through mode. Compared with the related art, the method can achieve the following: by receiving pixel information sent by a first device, a pixel value of a pixel to be stored and first address information of the pixel to be stored are obtained, wherein the first address information can represent the logical storage address designated for the pixel; by analyzing the first address information, a first physical storage address corresponding to the pixel to be stored in the memory can be determined; by determining the target stripe described by the first pixel in the video, a target matrix corresponding to the target stripe can be determined. Based on the first target address block described by the first physical storage address in the memory and the first position of the first target address block in the initial address block matrix, a second target address block corresponding to the first position in the target matrix can be determined; and based on the second position of the first physical storage address within the first target address block, the pixel to be stored is stored in the second position of the second target address block. Since the target matrix of the non-first strip is obtained after matrix transformation based on the target matrix of the previous strip, the order in which the address blocks in the target matrix of the non-first strip are read by row is the order in which the address blocks in the target matrix of the previous strip are read by column, which ensures that when the pixels to be read are stored in the memory, the pixels at the corresponding positions in the memory have been read by the second device. Therefore, the embodiment of the present application does not require the second device to read all the pixels in the memory before writing pixels to the memory, thereby improving the efficiency of video data transmission.

[0162] In an alternative embodiment, an electronic device is provided, such as Figure 10 As shown, Figure 10 The electronic device 4000 shown includes: a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, for example, via a bus 4002. Optionally, the electronic device 4000 may further include a transceiver 4004, which may be used for data exchange between the electronic device and other electronic devices, such as data transmission and / or data reception. It should be noted that in actual applications, the number of transceivers 4004 is not limited to one, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present application.

[0163] Processor 4001 can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 4001 can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0164] Bus 4002 may include a path for transmitting information between the above components. Bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. Bus 4002 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 10 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0165] The memory 4003 may be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory) or other type of dynamic storage device that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, optical disk storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media, other magnetic storage devices, or any other medium that can be used to carry or store computer programs and can be read by a computer, without limitation herein.

[0166] The memory 4003 is used to store the computer program for executing the embodiment of the present application, and the execution is controlled by the processor 4001. The processor 4001 is used to execute the computer program stored in the memory 4003 to implement the steps shown in the above method embodiment.

[0167] Among them, electronic devices may include but are not limited to mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., as well as fixed terminals such as digital TVs, desktop computers, etc. Figure 10 The electronic device shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0168] The embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps and corresponding contents of the aforementioned method embodiment can be implemented. Compared with the prior art, it can be implemented as follows: by receiving pixel information sent by a first device, the pixel value of the pixel to be stored and the first address information of the pixel to be stored are obtained, and the first address information can represent the logical storage address designated for the pixel; by the first address information, the first physical storage address corresponding to the pixel to be stored in the memory can be determined; by determining the target stripe described by the first pixel in the video, the target matrix corresponding to the target stripe can be determined. According to the first target address block described by the first physical storage address in the memory and the first position of the first target address block in the initial address block matrix, the second target address block corresponding to the first position in the target matrix can be determined, and according to the second position of the first physical storage address in the first target address block, the pixel to be stored is stored in the second position of the second target address block. Since the target matrix of the non-first strip is obtained after matrix transformation based on the target matrix of the previous strip, the order in which the address blocks in the target matrix of the non-first strip are read by row is the order in which the address blocks in the target matrix of the previous strip are read by column, which ensures that when the pixels to be read are stored in the memory, the pixels at the corresponding positions in the memory have been read by the second device. Therefore, the embodiment of the present application does not require the second device to read all the pixels in the memory before writing pixels to the memory, thereby improving the efficiency of video data transmission.

[0169] It should be noted that the computer-readable medium mentioned in the present disclosure may be a computer-readable signal medium or a computer-readable medium, or any combination thereof. Computer-readable storage media may include, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or components, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more conductors, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such a propagated data signal may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wire, optical cable, RF (radio frequency), or any suitable combination thereof.

[0170] The embodiment of the present application also provides a computer program product, including a computer program, which can implement the steps and corresponding contents of the aforementioned method embodiment when executed by a processor. Compared with the prior art, it can be achieved: by receiving pixel information sent by the first device, the pixel value of the pixel to be stored and the first address information of the pixel to be stored are obtained, and the first address information can represent the logical storage address designated for the pixel; by the first address information, the first physical storage address corresponding to the pixel to be stored in the memory can be determined; by determining the target stripe described by the first pixel in the video, the target matrix corresponding to the target stripe can be determined. According to the first target address block described by the first physical storage address in the memory, and the first position of the first target address block in the initial address block matrix, the second target address block corresponding to the first position in the target matrix can be determined, and according to the second position of the first physical storage address in the first target address block, the pixel to be stored is stored in the second position of the second target address block. Since the target matrix of the non-first strip is obtained after matrix transformation based on the target matrix of the previous strip, the order in which the address blocks in the target matrix of the non-first strip are read by row is the order in which the address blocks in the target matrix of the previous strip are read by column, which ensures that when the pixels to be read are stored in the memory, the pixels at the corresponding positions in the memory have been read by the second device. Therefore, the embodiment of the present application does not require the second device to read all the pixels in the memory before writing pixels to the memory, thereby improving the efficiency of video data transmission.

[0171] In the specification and claims of this application and the accompanying drawings, the terms "first," "second," "third," "fourth," "1," "2," and so on (if any) are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present application described herein can be practiced in an order other than that shown or described.

[0172] It should be understood that, although each operation step is indicated by arrows in the flowchart of the embodiment of the present application, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless otherwise clearly stated herein, in some implementation scenarios of the embodiment of the present application, the implementation steps in each flowchart can be performed in other orders according to demand. In addition, some or all of the steps in each flowchart can include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage in these sub-steps or stages can also be executed at different times respectively. Under different scenarios at the execution time, the execution order of these sub-steps or stages can be flexibly configured according to demand, and the embodiment of the present application does not limit this.

[0173] The above description is only an optional implementation method for some implementation scenarios of this application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of this application, the use of other similar implementation methods based on the technical ideas of this application also falls within the protection scope of the embodiments of this application.

Claims

1. A data storage method in direct mode, characterized in that: include: receiving pixel information of a first pixel of a target video sent by a first device, the pixel information including a pixel value and first address information indicating a logical storage address of the first pixel in a memory; wherein a video frame in the target video has a width of w pixels and a height of h pixels, respectively; and each video frame is divided into a plurality of continuous strips having a width of w pixels and a height of m pixels; According to the first address information, a first physical storage address of the first pixel in the memory is determined; wherein the memory includes t k m physical storage addresses, the physical storage addresses of the memory are divided into m t consecutive address blocks, t is w / k rounded up; where k m is the number of pixels read by the second device in one data read operation in the memory, where one data read operation includes m column-wise read operations performed on m rows of pixels, and the number of pixels read in one column-wise read operation is k pixels in one row; determining a first target stripe to which the first pixel belongs; Obtain the target matrix corresponding to the first target strip; wherein the target matrix corresponding to the first strip of the target video is the initial address block matrix, and the target matrix corresponding to the non-first strip is the second matrix obtained by matrix conversion of the first matrix, the first matrix is ​​the target matrix corresponding to the previous strip, and the initial address block matrix is ​​m t's matrix, m The element value of t elements is m The second matrix is ​​obtained by sorting the elements in the transposed matrix of the first matrix in the order of the number of rows where the elements are located, and then dividing the sorted elements into m t's matrix; Determine a first target address block to which the first physical storage address belongs in the memory; Determine a first position of the identifier of the first target address block in the initial address block matrix and a second position of the first physical storage address within the first target address block; A second target address block corresponding to the first position in the target matrix corresponding to the first target stripe is determined, and a pixel value of the first pixel is stored in a physical storage address corresponding to the second position in the second target address block.

2. The method according to claim 1, characterized in that Also includes: When the pixel values ​​of all pixels belonging to the same stripe are stored in the memory, the value of the first parameter in the first record table is increased by 1, the value of the first parameter indicating the number of stripes that have been stored; The determining the first target stripe to which the first pixel belongs includes: Obtaining the first record table; A first target stripe to which the first pixel belongs in the target video is determined according to a value of the first parameter in the first record table.

3. The method according to any one of claims 1-2, characterized in that For non-first strips of the target video, the target matrix corresponding to the non-first strips is obtained in the following manner: Obtain a target matrix corresponding to a previous strip, and use the target matrix corresponding to the previous strip as a first matrix; After sorting the elements in the transposed matrix of the first matrix according to the row number corresponding to the row where the elements are located, the m The matrix of t is used as the second matrix; The second matrix is ​​used as a target matrix corresponding to a first target stripe to which the first pixel belongs.

4. The method according to claim 3, characterized in that When pixel information of a first pixel of a non-first strip is received, matrix transformation is performed on a target matrix of a strip preceding the non-first strip to obtain a target matrix of the non-first strip.

5. The method according to claim 1, wherein Determining a first physical storage address of the first pixel in the memory according to the first address information includes: determining a first address offset between a logical storage address of a first pixel and a logical storage address of a first pixel in a first target stripe to which the first pixel belongs; A first physical storage address of the first pixel in the memory is obtained according to the first address offset and a first physical storage address of the memory, wherein an address offset of the first physical storage address relative to the first physical storage address of the memory is equal to the first address offset.

6. The method according to claim 5, characterized in that The determining of a first address offset between the logical storage address of the first pixel and the logical storage address of the first pixel in the first target stripe to which the first pixel belongs includes: Determining an intra-frame address offset of a logical storage address of the first pixel relative to a logical storage address of a first pixel of a corresponding video frame, wherein the logical storage address of the first pixel of each video frame corresponds to a first physical storage address of the memory; determining, according to the number of physical storage addresses in the memory, an intra-frame address offset of a first pixel in a first target stripe to which the first pixel belongs; The first address offset is determined according to the intra-frame address offset of the first pixel and the intra-frame address offset of a first pixel in a first target stripe to which the first pixel belongs.

7. The method according to claim 1, characterized in that The method further comprises: receiving a pixel read request sent by a second device, where the pixel read request includes second address information of logical storage addresses of k pixels to be read; determining, according to the second address information, a second physical storage address of each of the k pixels in the memory; Determining a second target stripe corresponding to the pixel read request, and determining a target matrix corresponding to the second target stripe; Determine a third target address block to which the k second physical storage addresses belong in the memory; Determining a third position of the identifier of the third target address block in the initial address block matrix; Determine a fourth target address block corresponding to the third position in the target matrix corresponding to the second target stripe, and send k pixel values ​​in the fourth target address block to the second device.

8. A data storage device in direct mode, characterized in that: include: a receiving module, configured to receive pixel information of a first pixel of a target video sent by a first device, the pixel information including a pixel value and first address information indicating a logical storage address of the first pixel in a memory; wherein a video frame in the target video has a width of w pixels and a height of h pixels, respectively; and each video frame is divided into a plurality of continuous strips having a width of w pixels and a height of m pixels; An address translation module is configured to determine a first physical storage address of the first pixel in the memory according to the first address information; wherein the memory includes t k m physical storage addresses, the physical storage addresses of the memory are divided into m t consecutive address blocks, t is w / k rounded up; where k m is the number of pixels read by the second device in one data read operation in the memory, where one data read operation includes m column-wise read operations performed on m rows of pixels, and the number of pixels read in one column-wise read operation is k pixels in one row; A target matrix acquisition module is configured to determine the first target stripe to which the first pixel belongs; and to obtain a target matrix corresponding to the first target stripe; wherein the target matrix corresponding to the first stripe of the target video is the initial address block matrix, and the target matrix corresponding to the non-first stripe is a second matrix obtained by performing matrix transformation on the first matrix, wherein the first matrix is ​​the target matrix corresponding to the previous stripe, and the initial address block matrix is ​​m t's matrix, m The element value of t elements is m The second matrix is ​​obtained by sorting the elements in the transposed matrix of the first matrix in the order of the number of rows where the elements are located, and then dividing the sorted elements into m t's matrix; A storage module is configured to determine a first target address block to which the first physical storage address belongs in a memory; determine a first position of an identifier of the first target address block in the initial address block matrix, and a second position of the first physical storage address within the first target address block; determine a second target address block corresponding to the first position in a target matrix corresponding to the first target stripe, and store a pixel value of the first pixel in a physical storage address corresponding to the second position in the second target address block.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory, wherein: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

11. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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