Method for efficiently utilizing cache unit for caching PRP in storage device

Abstract

The embodiment of the invention provides a method for efficiently utilizing a cache unit for caching PRP in storage equipment, and relates to the technical field of storage equipment. The method comprises the following steps: in response to a received IO command, obtaining address positioning information indicated by the IO command, and adding the address positioning information to an allocated cache unit; if the IO command is an NVMe write command, a DMA command is generated in response to address positioning information indicated by the NVMe write command, and a cache unit occupied by the address positioning information indicated by the NVMe write command is released; and if the IO command is an NVMe read command, releasing the cache unit occupied by the address positioning information indicated by the storage command processing completion message in response to the fact that the number of times that the address positioning information indicated by the storage command processing completion message is used is equal to the expected number of times. According to the method, the cache unit occupied by the address positioning information can be released in time, enough space is provided for caching subsequent address positioning information, and the cache utilization rate is increased.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a method for efficiently utilizing a cache unit for caching PRP in a storage device. Background Art

[0002] Figure 1A The block diagram of the solid-state storage device is shown. The solid-state storage device 102 is coupled to the host to provide storage capacity for the host. The host and the solid-state storage device 102 can be coupled in a variety of ways, including but not limited to connecting the host and the solid-state storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fiber Channel, wireless communication network, etc. The host can be an information processing device that can communicate with the storage device in the above manner, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 (hereinafter, the solid-state storage device is referred to as the storage device for short) includes an interface 103 , a control component 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory) 110 .

[0003] The above-mentioned NVM chip 105 includes NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), etc., which are common storage media.

[0004] The above-mentioned interface 103 can be adapted to exchange data with the host through, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is used to control data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access the data of the DRAM 110. The data of the FTL table and / or cached IO commands can be stored in the DRAM.

[0006] The control part 104 issues a command to the NVM chip 105 in a manner complying with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives a command execution result output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI" and the like.

[0007] A memory target is one or more logic units (LUNs) within a NAND flash package that share a CE (Chip Enable) signal. A NAND flash package may include one or more dies. Typically, a logic unit corresponds to a single die. A logic unit may include multiple planes. Multiple planes within a logic unit can be accessed in parallel, and multiple logic units within a NAND flash chip can execute commands and report status independently of each other.

[0008] Data is usually stored and read on a storage medium in pages. Data is erased in blocks. A block (also called a physical block) contains multiple pages. A block contains multiple pages. A page on a storage medium (called a physical page) has a fixed size, such as 17664 bytes. A physical page can also have other sizes.

[0009] In the storage device 102, FTL (Flash Translation Layer) is used to maintain the mapping information from the logical address (LBA) to the physical address. The logical address constitutes the storage space of the solid-state storage device perceived by the upper-layer software such as the operating system. The physical address is the address used to access the physical storage unit of the solid-state storage device. In the related art, the address mapping can also be implemented using the intermediate address form. For example, the logical address is mapped to the intermediate address, and then the intermediate address is further mapped to the physical address. The table structure that stores the mapping information from the logical address to the physical address is called the FTL table. The FTL table is an important metadata in the storage device. The data items of the FTL table record the address mapping relationship in the storage device in units of data units.

[0010] The host accesses the storage device with IO commands that follow the storage protocol. The control component generates one or more media interface commands based on the IO commands from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (e.g., programming commands, read commands, and erase commands) that follow the interface protocol of the NVM chip based on the media interface commands. The control component also tracks that all media interface commands generated from an IO command have been executed and indicates the processing results of the IO command to the host.

[0011] See also Figure 1B The control component includes a host interface 1041, a host command processing unit 1042, a storage command processing unit 1043, a medium interface controller 1044 and a storage medium management unit 1045. The host interface 1041 obtains the IO command provided by the host. The host command processing unit 1042 generates a storage command according to the IO command and provides it to the storage command processing unit 1043. The storage command can access the storage space of the same size, such as 4KB. The data unit corresponding to the data accessed by a storage command recorded in the NVM chip is called a data frame. The physical page records one or more data frames. For example, the size of the physical page is 17664 bytes, and the size of the data frame is 4KB, then one physical page can store 4 data frames.

[0012] The storage medium management unit 1045 maintains the conversion of the logical address to the physical address for each storage command. For example, the storage medium management unit 1045 includes an FTL table (the FTL will be explained below). For a read command, the storage medium management unit 1045 outputs the physical address corresponding to the logical address (LBA) accessed by the storage command. For a write command, the storage medium management unit 1045 allocates an available physical address for it and records the mapping relationship between the logical address (LBA) accessed by it and the allocated physical address. The storage medium management unit 1045 also maintains functions required for managing the NVM chip such as garbage collection and wear leveling.

[0013] The storage command processing unit 1043 operates the medium interface controller 1044 to issue a storage medium access command to the NVM chip 105 according to the physical address provided by the storage medium management unit 1045 .

[0014] For the purpose of clarity, the command sent by the host to the storage device 102 is called an IO command (including, for example, an NVMe read command and an NVMe write command), the command sent by the host command processing unit 1042 to the storage command processing unit 1043 is called a storage command, the command sent by the storage command processing unit 1043 to the medium interface controller 1044 is called a medium interface command, and the command sent by the medium interface controller 1044 to the NVM chip 105 is called a storage medium access command. The storage medium access command complies with the interface protocol of the NVM chip.

[0015] In the NVMe protocol, NVMe has two commands, one is the admin command, which is used by the host to manage and control the storage device, and the other is the IO command, including the NVMe write command and the NVMe read command, which is used to control the data transmission between the host and the storage device. After receiving the NVMe write command, the solid-state storage device 102 obtains the data from the host's memory through the host interface 1041, and then writes the data into the flash memory. For the NVMe read command, when the data is read from the flash memory, the solid-state storage device 102 moves the data to the host memory through the host interface 1041. PRP (Physical Region Page) and SGL (Scatter / Gather List) are two ways to describe the data to be transmitted between the host and the storage device. In the PRP method, several linked PRP entries are used, and each PRP entry includes a 64-bit memory physical address, which is used to describe a physical page (Page) of the host memory. SGL is a linked list consisting of one or more SGL segments, each of which consists of one or more SGL descriptors; each SGL descriptor describes the address and length of the data cache in the host memory, that is, each SGL descriptor corresponds to a host memory address space; each SGL descriptor has, for example, a fixed size (e.g., 16 bytes).

[0016] There are fields related to SGL or PRP in the NVMe write command and NVMe read command, which indicate the location of the data in the host memory (for write commands) or the host memory address to be written (for read commands). The PRP field or SGL field in the NVMe write command and NVMe read command can be an SGL or PRP entry pointing to the host memory address space to be accessed, or a pointer to an SGL or PRP linked list, or even a pointer to a pointer. If the NVMe write command and NVMe read command carry SGL or PRP, the storage device can directly obtain the SGL or PRP in response to receiving the IO command. If the NVMe write command and NVMe read command carry an SGL or PRP pointer, in response to receiving the IO command, the storage device accesses the host according to the above-mentioned SGL or PRP pointer and obtains the SGL or PRP from the host. A host command processing unit for processing NVMe read commands is provided in Chinese Patent 202110746144.1, and a host command processing unit for processing NVMe write commands is provided in Chinese Patent 202110746142.2, which describe a process in which a storage device obtains a PRP entry or an SGL descriptor from an NVMe write command or an NVMe read command.

[0017] In high-performance storage devices, the control component may process hundreds or even thousands of IO commands (including NVMe read commands and NVMe write commands) per second, and each IO command carries a PRP field or an SGL field. However, the resources of the cache unit that stores the PRP field or the SGL field are limited. In order to enable the cache unit to cache the PRP or SGL sent by the host to the storage device, the resources of the cache unit need to be managed. Summary of the invention

[0018] In view of this, an embodiment of the present application provides a cache unit management method for a storage device and a storage device, which can promptly release the cache unit occupied by the address location information indicated by the IO command (for example, a PRP entry, an SGL descriptor, or based on the PRP entry or the SGL descriptor), so that the cache unit has sufficient space to cache the address location information indicated by subsequent IO commands, thereby improving the utilization rate of the cache unit.

[0019] According to a first aspect of the present application, a cache unit management method of a storage device is provided, comprising:

[0020] In response to receiving an IO command, acquiring address location information indicated by the IO command, and adding the address location information to the allocated cache unit;

[0021] If the IO command is an NVMe write command, in response to generating a DMA command according to the address location information indicated by the NVMe write command, releasing the cache unit occupied by the address location information indicated by the NVMe write command; or,

[0022] If the IO command is an NVMe read command, in response to the address location information indicated by the storage command processing completion message having been used a number of times equal to the expected number of times, the cache unit occupied by the address location information indicated by the storage command processing completion message is released; wherein the storage command indicated by the storage command processing completion message is generated based on the NVMe read command.

[0023] In an optional embodiment, the method further includes: in response to receiving the storage command processing completion message, if the number of times the address location information indicated by the storage command processing completion message has been used is not equal to the expected number of times, controlling the number of times used to be increased by one.

[0024] In an optional embodiment, the method also includes: if the IO command is an NVMe read command, determining one or more data to be moved indicated by the NVMe read command; determining the number of data to be moved accommodated in the storage block according to the data volume of the one or more data to be moved and the capacity of the storage block corresponding to the address location information indicated by the NVMe read command; the number of data to be moved accommodated in the storage block is the expected number of times the address location information corresponding to the storage block is used.

[0025] In an optional embodiment, the address location information includes one or more of the following: a PRP entry, an SGL descriptor, and a host memory address determined according to the PRP entry or the SGL description.

[0026] According to a second aspect of the present application, a storage device is provided, the storage device comprising a host command processing unit, the host command processing unit comprising a cache unit, a circuit for writing to the cache unit, and a circuit for releasing the cache unit:

[0027] The circuit of the write cache unit is used to obtain the address location information indicated by the IO command in response to receiving the IO command, and add the address location information to the allocated cache unit;

[0028] The circuit for releasing the cache unit is used to, if the IO command is an NVMe write command, in response to generating a DMA command according to the address location information indicated by the NVMe write command, release the cache unit occupied by the address location information indicated by the NVMe write command; or, if the IO command is an NVMe read command, in response to the address location information indicated by the storage command processing completion message having been used the number of times equal to the expected number of times, release the cache unit occupied by the address location information indicated by the storage command processing completion message; wherein the storage command indicated by the storage command processing completion message is generated according to the NVMe read command.

[0029] In an optional embodiment, the address location information includes one or more of the following: a PRP entry, an SGL descriptor, a host memory address determined according to the PRP entry or the SGL description;

[0030] The circuit of the write cache unit includes a PRP circuit and / or an SGL circuit;

[0031] The PRP circuit is configured to, in response to receiving an IO command, obtain a PRP entry indicated by the IO command or a host memory address indicated by the PRP entry, and add the PRP entry or the host memory address indicated by the PRP entry to an allocated cache unit;

[0032] The SGL circuit is used for, in response to receiving an IO command, obtaining an SGL descriptor indicated by the IO command or a host memory address indicated by the SGL descriptor, and adding the SGL descriptor or the host memory address indicated by the SGL descriptor to an allocated cache unit.

[0033] In an optional embodiment, the host command processing unit includes a write initiation circuit, and the write initiation circuit includes a DMA command generation circuit;

[0034] The DMA command generation circuit includes a circuit for releasing the cache unit, and the DMA command generation circuit generates a DMA command according to the address location information indicated by the NVMe write command, and in response to generating the DMA command, releases the cache unit occupied by the address location information indicated by the NVMe write command.

[0035] In an optional embodiment, the host command processing unit includes a read initiation circuit, and the read initiation circuit includes a completion message processing circuit;

[0036] The completion message processing circuit includes a circuit for releasing the cache unit. In response to the address location information indicated by the storage command processing completion message having been used a number of times equal to an expected number of times, the completion message processing circuit releases the cache unit occupied by the address location information indicated by the storage command processing completion message; wherein the storage command indicated by the storage command processing completion message is generated based on the NVMe read command.

[0037] In an optional embodiment, the circuit for releasing the cache unit includes a first memory, a first calculation circuit, a comparison circuit, and an address location information deletion circuit;

[0038] The first memory is used to record the number of times the address location information indicated by the NVMe read command has been used;

[0039] The first calculation circuit, in response to receiving a storage command processing completion message, calculates an expected number of times the address location information indicated by the storage command processing completion message is used;

[0040] The comparison circuit is coupled to the first memory and the first calculation circuit, and is used to compare the number of times the address location information corresponding to the storage command processing completion message has been used with the expected number of times, and output a comparison result;

[0041] The address location information deletion circuit is coupled to the comparison circuit and is used to release the cache unit occupied by the address location information indicated by the storage command processing completion message when the comparison result is that the number of times used is equal to the expected number of times.

[0042] In an optional embodiment, the circuit of the release cache unit includes: a second memory, a second calculation circuit and a control circuit;

[0043] The second memory is used to record the number of times the address location information indicated by the NVMe read command has been used;

[0044] The second calculation circuit calculates the expected number of times the address location information corresponding to the storage command processing completion message is used in response to receiving the storage command processing completion message;

[0045] The control circuit is coupled to the second memory and the second calculation circuit, and is used to compare the number of times the address location information indicated by the storage command processing completion message has been used with the expected number of times; when the number of times used is equal to the expected number of times, release the cache unit occupied by the address location information indicated by the storage command processing completion message; when the number of times used is not equal to the expected number of times, control the number of times used recorded in the second memory to be increased by one.

[0046] The cache unit management method of the storage device of the embodiment of the present application promptly releases the cache unit occupied by the address location information indicated by the IO command (such as a PRP entry, an SGL descriptor, or based on a PRP entry or an SGL descriptor), so that the cache unit has sufficient space to cache the address location information indicated by subsequent IO commands, thereby improving cache utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0048] Figure 1A shows a block diagram of a solid-state storage device;

[0049] Figure 1B A block diagram showing control components in a solid-state storage device;

[0050] Figure 2 A schematic diagram showing the structure of a host command processing unit according to an embodiment of the present application is shown;

[0051] Figure 3 A schematic diagram showing the structure of a host command processing unit according to another embodiment of the present application is shown;

[0052] Figure 4 A schematic diagram showing the organization of data of a storage device on a physical page of an NVM chip according to an embodiment of the present application;

[0053] Figure 5 A schematic diagram showing a physical page of a storage device according to another embodiment of the present application is shown;

[0054] Figure 6 A schematic diagram showing the transfer of data from a storage device to a host according to an embodiment of the present application is shown;

[0055] Fig. 7A A schematic diagram showing data to be moved indicated by an NVMe read command according to an embodiment of the present application is shown;

[0056] Figure 7B A schematic diagram showing a host memory address indicated by an NVMe read command according to an embodiment of the present application is shown;

[0057] Figure 7C A schematic diagram showing the storage of data indicated by an NVMe read command in a host memory according to an embodiment of the present application;

[0058] Figure 8A schematic diagram showing a circuit for releasing a cache unit according to an embodiment of the present application is shown;

[0059] Fig. 9 A schematic diagram showing a circuit for releasing a cache unit according to another embodiment of the present application is shown;

[0060] Fig. 10A A schematic diagram showing a host memory address indicated by an NVMe read command according to an embodiment of the present application is shown;

[0061] Fig. 10B A schematic diagram showing the storage of data indicated by an NVMe read command in a host memory according to an embodiment of the present application;

[0062] Fig.11 A schematic flow chart of a cache unit management method for a storage device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0063] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0064] For ease of understanding, the following briefly describes how the host and storage device move data through PRP entries or SGL descriptors.

[0065] If data is moved from the storage device to the host, the host sends an NVMe read command to the storage device. The NVMe read command sent by the host to the storage device indicates the address of the host memory to be written, and also includes the starting logical address (LBA) of the storage device to be accessed and the data length. The storage device searches the FTL table based on the LBA, finds the corresponding physical address, and obtains the data from the physical block corresponding to the physical address. The address indicated by the NVMe read command to write data to the host memory can be indicated by a PRP entry or an SGL descriptor. The NVMe read command indicates one or more RPR entries or SGL descriptors.

[0066] If data is moved from the host to the storage device, the host sends an NVMe write command to the storage device. The NVMe write command sent by the host to the storage device indicates the length of the data to be written and the location where the data to be written is stored in the host memory. The location where the data to be written is stored in the host memory can be indicated by a PRP entry or an SGL descriptor. The NVMe write command can indicate one or more RPR entries or SGL descriptors. The storage location of the data to be written in the storage device is allocated by the storage device.

[0067] The host carries a PRP or SGL related field in the NVMe read command or NVMe write command, which can be the SGL or PRP itself, pointing to the host memory address space to be accessed, or a pointer, pointing to the SGL or PRP linked list, or even a pointer to a pointer. Whether it is a PRP entry or an SGL descriptor, it essentially describes one or more address spaces in the host memory, and the location of these address spaces in the host memory is arbitrary. The PRP entry indicates a fixed-size storage space in the host memory, that is, the storage space size indicated by different PRP entries is the same, such as 4KB, 16KB, etc. The SGL descriptor indicates a storage space of indefinite size in the host memory. For example, the NVMe read command indicates three SGL descriptors (SGL1, SGL2, and SGL3), where SGL1 indicates a 4KB storage space, SGL2 indicates a 2KB storage space, and SGL3 indicates a 3KB storage space.

[0068] Regardless of the form, according to the NVMe read command or the NVMe write command, the storage device can always obtain the corresponding SGL descriptor or PRP entry. It can be understood that the embodiments of the present application are not limited to transmitting data between the host and the storage device through PRP entries or SGL descriptors, but can also transmit data through other information with similar functions. In some cases, they are collectively referred to as address location information indicated by IO commands.

[0069] In response to receiving an NVMe read command or an NVMe write command (collectively referred to as an IO command), the storage device first obtains the PRP or SGL according to the IO command before accessing the data. For example, all PRP entries or SGL descriptors corresponding to the IO command are obtained. Since there can be multiple PRP entries or SGL descriptors corresponding to the IO command, the movement of the data described by each PRP entry or SGL descriptor (movement between the host and the storage device) is independent of each other and performed in parallel. Therefore, the movement of the data described by each PRP entry or SGL descriptor is usually not completed at the same time. For this reason, the control component of the storage device provides a cache, in particular, a cache unit located inside the control component to temporarily record the PRP entry or SGL descriptor corresponding to the IO command. However, the cache unit inside the control component is extremely limited and valuable, and it is necessary to release the PRP entry or SGL descriptor corresponding to the IO command in the cache unit as soon as possible to provide caching capacity for the PRP entries or SGL descriptors of other IO commands.

[0070] Taking the storage device processing NVMe write commands and the NVMe write commands using PRP to describe the host memory address as an example, the process of the storage device processing NVMe write commands is explained. Figure 2 FIG. 2 shows a schematic diagram of the structure of a host command processing unit according to an embodiment of the present application. Figure 2As shown, the host command processing unit includes a PRP circuit, a write initiation circuit, a DMA transmission circuit and a cache unit. The write initiation circuit includes a DMA command generation circuit and a storage command generation circuit. Figure 2 An example of a write initiation circuit is schematically shown. Other forms of write initiation circuits can refer to Chinese Patent 202310788448.3, which will not be described in detail in this application.

[0071] The process of the host command processing unit processing the NVMe write command includes:

[0072] The PRP circuit responds to receiving an NVMe write command (such as Figure 2 In process (1), a PRP entry is obtained from an NVMe write command, the PRP entry is cached in a cache unit, and a PRP index indicating the PRP entry is provided to a DMA command generation circuit (such as a DMA command generation circuit) of a write initiation circuit. Figure 2 Process (2)). Among them, obtaining the PRP entry from the NVMe write command and obtaining the PRP index belongs to the prior art (such as the PRP unit shown in Chinese patent 202110746142.2), which will not be repeated here.

[0073] The PRP index has various forms, for example, the PRP index carries the host memory address indicated in the PRP entry, or the PRP index carries a pointer to a cache unit, the cache unit stores the PRP entry, and the PRP entry is obtained from the cache unit through the PRP index to obtain the host memory address. Still optionally, the PRP index corresponds to the PRP entry one-to-one.

[0074] In response to receiving the PRP index, the DMA command generation circuit generates a DMA command based on the PRP index and provides the generated DMA command to the DMA transmission circuit (eg, Figure 2 process (3)).

[0075] The DMA command is used to control the DMA transfer circuit to perform data transfer. It indicates the mapping relationship between the host memory address space and the storage device cache address space (such as DRAM address) and is used to perform a data movement operation between the host and the storage device. The host memory address indicated by the DMA command is determined according to the address space indicated by the PRP, and the storage device cache address is allocated by the storage device.

[0076] For NVMe write commands, the host memory address is the source address and the storage device cache address is the destination address. Generating a DMA command requires the host memory address as the source address and the storage device cache address as the destination address. The DMA command generation circuit obtains the host memory address based on the PRP index and allocates storage space from the storage device cache to obtain the storage device cache address.

[0077] The DMA transmission circuit responds to the received DMA command, moves data between the host memory and the storage device cache according to the DMA command, and after the data move is completed, provides a message indicating that the DMA command processing is completed to the storage command generation circuit (such as Figure 2 process (4)).

[0078] The storage command generation circuit generates a storage command in response to receiving a DMA command processing completion message sent by the DMA transmission circuit, and sends the storage command to the storage command processing unit (such as Figure 2 As an example, the storage command causes the storage command processing unit to move the data in the storage device cache to the NVM chip of the storage device according to the storage command. The storage command processing unit and the storage command are both prior art and will not be described in detail here.

[0079] By the above Figure 2 It can be seen from the processes (1)-(5) shown that the PRP entry indicated by the NVMe write command is mainly used to generate a DMA command. Once a DMA command is generated based on a PRP entry indicated by the NVMe write command, the PRP entry in the cache unit can be released.

[0080] Therefore, the host command processing unit of the storage device receives the NVMe write command, allocates a cache unit for the address location information indicated by the NVMe write command, generates a DMA command according to the address location information indicated by the NVMe write command, and releases the cache unit occupied by the address location information indicated by the NVMe write command corresponding to the DMA command in response to the generation of the DMA command. Figure 2 In the write initiation circuit shown, the function of releasing the cache unit can be implemented by a DMA command generation circuit, that is, the DMA command generation circuit releases the cache unit occupied by the address location information indicated by the NVMe write command corresponding to the DMA command in response to generating a DMA command.

[0081] Taking the storage device processing the NVMe read command and the NVMe read command using the PRP descriptor host memory address as an example, the process of the storage device processing the NVMe read command is explained. Figure 3 FIG. 2 shows a schematic diagram of the structure of a host command processing unit according to an embodiment of the present application. Figure 3 As shown, the host command processing unit includes: a PRP circuit, a read initiation circuit, a DMA transmission circuit and a cache unit, wherein the read initiation circuit includes an information cache, a DMA command generation circuit and a completion message processing circuit. Figure 3 An example of a write initiation circuit is schematically shown. Other forms of write initiation circuits can refer to Chinese patent 202310788454.9, which will not be described in detail in this application.

[0082] In response to receiving an NVMe read command, the PRP circuit obtains a PRP entry from the NVMe read command, caches the PRP entry to a cache unit, and provides a PRP index indicating the PRP entry to a read initiation circuit. Obtaining a PRP entry from an NVMe read command and obtaining a PRP index belongs to the prior art (such as the PRP circuit shown in Chinese Patent 202110746144.1), which will not be repeated here.

[0083] In response to receiving a PRP index or an NVMe read command, the read initiation circuit updates the information cache (such as Figure 3 Process (1)). The information cache can accommodate multiple entries, each entry corresponds to an NVMe read command, different entries correspond to different NVMe read commands, and all PRP entries, all DMA commands, and all DMA command processing completion messages associated with the same NVMe read command correspond to the same entry. Thus, the storage device concurrently processes multiple NVMe read commands at the same time. It can be understood that the NVMe read command stored in the information cache may be different in form from the NVMe read command received from the host, but each NVMe read command occupies an entry in the information cache. For example, in order to read the needs of the initiating circuit processing, the NVMe read command in the information cache includes information such as a command identifier, a cache unit index, a DMA command count, and a timestamp. The command identifier is used to identify a specified NVMe read command from multiple NVMe read commands. The cache unit index is used to indicate the PRP entry in the cache unit. The DMA command count is used to indicate the number of DMA commands that have been processed corresponding to the NVMe read command to which it belongs. The timestamp indicates the time when the NVMe read command is received.

[0084] It is understandable that the control component of the storage device also performs other processing on the NVMe read command, for example, generating a physical address based on the logical address to be accessed by the NVMe read command through the FTL table, and using the physical address to read data from the NVM chip, etc. These processing processes and the components that implement these processes belong to the prior art. The components that implement these processes are collectively referred to as back-end modules. After reading the data from the NVM chip and adding it to the storage device cache (such as DRAM), the back-end module provides a storage command processing completion message (such as DRAM) to the read initiation circuit. Figure 3 In process (2)). A single NVMe read command corresponds to one or more storage commands, and thus a single NVMe read command corresponds to one or more storage command completion messages.

[0085] The DMA command generation circuit responds to receiving a storage command processing completion message (such as Figure 3 In process (2), the cache unit index corresponding to the storage command is obtained from the information cache (such as Figure 3In process (3), based on the cache unit index, a PRP entry corresponding to the storage command is obtained from the cache unit (such as Figure 3 Process (4)), and based on the PRP entry, a corresponding DMA command is generated, and the DMA command is sent to the DMA transmission circuit (such as Figure 3 process (5)).

[0086] To generate a DMA command, it is necessary to know the storage device cache address as the DMA transfer source address and the host memory address as the destination address. According to an embodiment of the present application, the storage device cache address is obtained according to the storage command processing completion message, and the host memory address is obtained according to the PRP entry. Figure 3 The NVMe read command stored in the information cache includes, for example, a cache unit index, obtaining the corresponding NVMe read command based on a storage command processing completion message, obtaining the cache unit index from the information cache, and obtaining a PRP entry from the corresponding cache unit based on the cache unit index.

[0087] In response to receiving the DMA command, the DMA transmission circuit moves data from the storage device cache to the host memory, and in response to the completion of the DMA command processing, sends a DMA command processing completion message (such as Figure 3 process (6)).

[0088] The completion message processing circuit is coupled to the DMA transmission circuit and the cache unit, and in response to receiving the DMA command processing completion message, updates the NVMe read command corresponding to the DMA command processing completion message in the cache unit. For example, the DMA command count value is updated (for example, incremented), or if all DMA commands corresponding to the NVMe read command are processed, the NVMe read command is deleted from the cache unit (for example, Figure 3 process (7)).

[0089] exist Figure 3 In the illustrated embodiment, there are two different stages in the NVMe read command processing process, and the information cache of the read initiation circuit is updated. Stage (1) After the control component of the storage device receives the NVMe read command and obtains the PRP entry from the host according to the NVMe read command, the entry associated with the NVMe read command is added to the information cache, and the entry associated with the NVMe read command added to the information cache includes a PRP index indicating the cache address of the PRP entry; Stage (2) In response to receiving one or more DMA command processing completion messages corresponding to the NVMe read command, the DMA command count of the NVMe read command in the information cache is updated or the NVMe read command is deleted.

[0090] Figure 4FIG. 1 is a schematic diagram showing the organization of data of a storage device according to an embodiment of the present application on a physical page of an NVM chip. Figure 4 As shown in FIG. 1 , in the NVM chip, the storage space for storing data is organized into physical blocks and physical pages. In the IO command provided by the host to the storage device, the storage unit size represented by the logical address LBA is, for example, 4KB. In addition to recording the 4KB data provided by the user (recorded in Figure 4 The spare data area also records information generated by the storage device itself, such as the verification data generated by the ECC algorithm for the user data, the LBA of the user data, the random number seed when scrambling the user data, the encryption or decryption key, etc. For the sake of simplicity, the data recorded in the spare data area are also collectively referred to as metadata. Optionally, the size of the storage unit represented by each LBA can be 4KB, 8KB, 16KB, etc., and the size of the metadata can be 512Byte or other sizes.

[0091] exist Figure 4 In the illustrated embodiment, the physical page is slightly larger than the storage unit represented by the LBA, that is, the size of the physical page is slightly larger than 4KB. In an optional embodiment, the storage device also provides a larger physical page (for example, larger than 16KB), so that the capacity of the physical page is inconsistent with the capacity of the storage unit represented by the LBA. Figure 5 As shown in FIG. 1 , the physical page records metadata corresponding to four LBAs and metadata corresponding to each user data. The combination of user data stored in a physical page and its corresponding metadata is called DU (Date Unit). Figure 5 As described above, four DUs are recorded in a physical page. When a host reads data from a storage device, the data is moved according to the DUs.

[0092] In some optional embodiments, the size of the storage block (in the host memory) indicated by each PRP entry is consistent with the size of the storage unit represented by the LBA, for example, the size of the storage block indicated by each PRP is 4KB, and the size of the storage unit represented by the LBA is also 4KB. In other optional embodiments, the size of the storage block (host memory) indicated by the PRP entry is inconsistent with the size of the storage unit represented by the LBA, for example, the storage block indicated by the PRP entry is 4KB, while the size of the storage unit represented by the LBA is 2KB.

[0093] For example, the size of the storage block (in the host memory) indicated by each PRP entry is consistent with the size of the storage unit represented by the LBA. For example, the size of the storage block indicated by each PRP entry is 4KB, and the size of the storage unit represented by each LBA is also 4KB. Figure 6As shown, the storage unit size represented by each logical address LBA indicated by the NVMe read command is, for example, 4KB, the metadata size is, for example, 512Byte, and the data size moved from the NVM chip to the DRAM by each storage command is, for example, (4KB+512Byte). The data of each size (4KB++512Byte) stored in the DRAM is called a DTU (Data Transfer Unit). The DTU is moved to the storage block described by the PRP entry on the host side through a DMA command. However, the size of the storage block (in the host memory) indicated by each PRP entry is, for example, 4KB, resulting in the data size of the DTU (4KB+512Byte) being larger than the storage unit size (4KB) represented by each PRP entry on the host side. Furthermore, when the logical address LBA corresponding to the DTU is not 4KB aligned, part of the data in the DTU is not valid data, so it does not need to be transmitted to the host, which results in the data moved to the host according to some DTUs (even with metadata) being smaller than the storage block size (e.g., 4KB) indicated by the PRP entry. Still further, in addition to the metadata recorded in the spare data area of ​​the NVM chip, the control component may also generate other metadata (e.g., PI, protection information) so that when the DTU is moved to the host memory, the required host memory space is not equal to the storage block size (e.g., 4KB) indicated by the PRP entry. However, when storing data on the host side, the data is stored in a 4KB aligned manner (the storage block size indicated by each PRP is 4KB, and its address space is aligned along 4KB), so that the storage block indicated by a PRP entry on the host side may store data of one or more DTUs.

[0094] Since the host memory storage block size indicated by the PRP entry is inconsistent with the DTU size, the storage command processing completion message and the PRP entry are not one-to-one corresponding. Therefore, when a storage command processing completion message is received during the processing of an NVMe read command, it is necessary to determine whether to delete the corresponding PRP entry.

[0095] like Fig. 7A , 7B , 7C, in Fig. 7AIn the NVMe read command, according to the physical addresses corresponding to the logical addresses LBA0~LBA5 indicated by the NVMe read command, 5 copies of data are read from the NVM chip respectively, and the data is stored in the DRAM. The storage unit size represented by each logical address is 4KB. Among them, data 1 is the data that needs to be moved to the host memory from the (4KB+512Byte) data corresponding to LBA0. Since LBA0 indicated by the NVMe read command is not 4KB aligned, the beginning part of data 1 does not need to be moved to the host, and the part to be moved to the host is less than 4KB; data 2 is the data that needs to be moved to the host memory from the (4KB+512Byte) data corresponding to LBA1, and the size is equal to 4KB+512Byte; data 3 is the data that needs to be moved to the host memory from the (4KB+512Byte) data corresponding to LBA2, and the size is equal to 4KB+512B; data 4 is the (4KB+512Byte) data corresponding to LBA3. The first data of the NVMe read command corresponds to the (4KB+512Byte) data. The first data of the NVMe read command corresponds to the (4KB+512Byte) data. The second data of the NVMe read command corresponds to the (4KB+512Byte) data. The third data of the NVMe read command corresponds to the (4KB+512Byte) data. The fourth data of the NVMe read command corresponds to the (4KB+512Byte) data. The fourth data of the NVMe read command corresponds to the (4KB+512Byte) data. The fourth data of the NVMe read command corresponds to the (4KB+512Byte) data. The fourth data of the NVMe read command corresponds to the (4KB+512Byte) data. The fifth ...

[0096] like Figure 7B As shown, PRP0-PRP6 are PRP entries indicated by NVMe read commands, and the size of the storage block in the host memory represented by each PRP in PRP0-PRP6 is 4KB. Figure 7B The storage blocks indicated by PRP0-PRP6 that are spatially continuous are shown in the figure. Optionally, these storage blocks may be discontinuous storage blocks in the host memory space. However, these storage blocks together form a continuous virtual storage space in the order of PRP0-PRP6. And the positions of each data (DTU) moved to the storage block indicated by the PRP entry according to the NVMe read command in the continuous virtual storage space are sorted according to their LBAs, so that each DTU has a certain position and size in the continuous virtual storage space. Therefore, according to the LBA and size of the DTU, it is determined that it has a certain position in the virtual storage space, and it is determined which storage block indicated by which PRP the position belongs to.

[0097] like Figure 7CAs shown, data is stored starting from the storage block represented by PRP0, that is, data 1 is stored in the storage block represented by PRP0. Since the size of data 1 is less than 4KB, and the starting address of the required data is not 4KB aligned, data 1 is not stored from the beginning (but from the middle position) in the storage block indicated by PRP0. After data 1 is stored in the storage block indicated by PRP0, the storage block represented by PRP0 also needs to store part of the data in data 2. Part of the data of data 2 is stored in the data block represented by PRP1. Since the size of data 2 is greater than 4KB, the data block represented by PRP1 cannot completely store data 2, and the storage block represented by PRP2 needs to be occupied. Data 3 is stored in the data blocks represented by PRP2 and PRP3. Data 4 needs to be stored in the data blocks represented by PRP3 and PRP4. Data 5 needs to be stored in the data blocks represented by PRP5 and PRP6. Data 6 needs to be stored in the data block represented by PRP6. Figure 7C In the figure, shaded boxes are used to represent the data corresponding to the LBA to be stored in the host memory.

[0098] For PRP0, since the storage block represented by PRP0 stores data 1 and data 2, after receiving the message that the storage command processing corresponding to data 1 is completed, the PRP0 entry in the cache unit cannot be deleted (because PRP0 is still needed when processing the storage command processing corresponding to data 2 next). PRP0 in the cache unit can only be deleted after receiving the storage command processing corresponding to data 2. Further, the order in which the storage command processing corresponding to data 1 and the storage command processing corresponding to data 2 are received is not guaranteed, so that when the storage command processing corresponding to data 2 is received, it cannot be guaranteed that the storage command processing corresponding to data 1 has been received. Therefore, the PRP entry in the cache unit cannot be deleted according to the number or index of the data corresponding to the storage command processing completed message, but the PRP entry in the cache unit is deleted according to the number of storage command processing completed messages received, and the storage command processing completed messages corresponding to each PRP entry may be different. For example, for the PRP0 entry, it is necessary to receive two storage command processing completed messages related to PRP0 before it is deleted from the cache unit. For PRP1, since only data 2 is stored in PRP1, it needs to receive a storage command processing completion message related to PRP1 before it can be deleted from the cache unit. Similarly, the release process of PRP2-PRP6 can be known.

[0099] Combination Fig. 7A , 7BAs shown in 7C, when the PRP entry represents a 4KB host storage block and the storage command processing completion message represents 4KB+512B, it is determined how many DTUs of data each PRP entry contains:<PRP0,2> (Indicates that PRP0 accommodates 2 DTUs of data).<PRP1,1> ,<PRP2,2> ,<PRP3,2> ,<PRP4,1> ,<PRP5,1> ,<PRP6,2> According to the number of DTUs corresponding to each PRP entry, it is determined that after receiving several storage command completion messages, the corresponding PRP entry is deleted to release the cache unit.

[0100] In an alternative embodiment, reference Figure 3 The function of releasing the cache unit can be realized by the completion message processing circuit in the read initiation circuit, or other circuits can be set in the read initiation circuit to realize the function of releasing the cache unit.

[0101] Figure 8 FIG. 1 is a schematic diagram showing a circuit for releasing a cache unit according to an embodiment of the present application. Figure 8 As shown, the circuit of the release cache unit includes: a memory M1, a calculation circuit W1, a comparison circuit and a PRP entry deletion circuit.

[0102] Among them, the memory M1 is used to record the number of storage command processing completion messages corresponding to the PRP entry indicated by the NVMe read command, that is, the number of times the PRP entry indicated by the NVMe read command has been used. Each time a storage command processing completion message is received, the number of times the PRP entry corresponding to the storage command processing completion message has been used is increased by 1 and recorded in the memory.

[0103] The calculation circuit W1 receives the storage command processing completion message, and calculates the expected number of times the PRP entry associated with it is used according to the storage command processing completion message. Fig. 7A and 7CAs shown, for example, the computing circuit receives a storage command processing completion message corresponding to data 1, whose LBA=0, and the corresponding PRP entry is: PRP0, PRP0 contains 2 DTUs of data, and PRP0 should be released after receiving 2 storage command processing completion messages corresponding to PRP0, so the expected number of times PRP0 is used is 2. For another example, the computing circuit receives a storage command processing completion message corresponding to data 2, whose LBA=1, and the corresponding PRP entries include: PRP0, PRP1 and PRP2. PRP0 contains 2 DTUs of data, and PRP0 should be released after receiving 2 storage command processing completion messages corresponding to PRP0, so the expected number of times PRP0 is used is 2. PRP1 contains 1 DTU of data, and PRP1 should be released after receiving 1 storage command processing completion message corresponding to PRP1, so the expected number of times PRP0 is used is 1. PRP2 contains 2 DTUs of data, and PRP2 should be released after receiving 2 storage command processing completion messages corresponding to PRP2, so the expected number of times PRP2 is used is 2.

[0104] The comparator is coupled to the memory M1 and the calculation circuit W1, and is used to compare whether the number of times the PRP has been used recorded by the memory M1 is the same as the expected number of times calculated by the calculation circuit W1, and if they are the same, the index of the PRP entry is provided to the PRP entry deletion circuit. For example, the comparator compares whether the number of times PRP0 has been used is equal to 2, and if so, the index of the PRP0 entry is provided to the PRP entry deletion circuit.

[0105] The PRP entry deletion circuit deletes the corresponding PRP entry in the cache unit according to the index of the received PRP entry. For example, the PRP entry deletion circuit receives PRP0 provided by the comparator and deletes PRP0 in the cache unit to release the cache unit.

[0106] Fig. 9 FIG. 2 is a schematic diagram showing another circuit for releasing a cache unit according to an embodiment of the present application. Fig. 9 As shown, the circuit of the release cache unit includes a memory M2, a calculation circuit W2 and a control circuit.

[0107] Among them, the memory M2 is used to record the number of storage command processing completion messages corresponding to the PRP entry indicated by the NVMe read command, that is, the number of times the PRP entry indicated by the NVMe read command has been used.

[0108] The calculation circuit W2 receives the storage command processing completion message, calculates the expected number of times the corresponding one or more PRP entries are used according to the LBA indicated by the storage command processing completion message, and provides the expected number of times the PRP entries are used to the control circuit.

[0109] The control circuit is coupled to the memory M2 and the calculation circuit W2, and receives the expected number of times the PRP entry is used provided by the calculation circuit W2 (eg Fig. 9 In process (1)), the number of times the PRP entry has been used is obtained from memory M2 (such as Fig. 9 In process (2), the number of times the PRP entry has been used is compared with the expected number of times, and the PRP entry in the cache unit is managed according to the comparison result. If the number of times the PRP entry has been used is equal to the expected number of times, the PRP entry in the cache unit is deleted, and the cache unit is released (such as Fig. 9 If the number of times the PRP entry has been used is not equal to the expected number of times, the number of times the PRP entry in the control memory M2 has been used is increased by 1 (as shown in process (4) in the figure).

[0110] As can be seen from the above, the size of the storage block (in the host memory) indicated by each PRP entry is inconsistent with the size of the storage unit represented by the LBA. For example, the size of the storage block indicated by each PRP entry is 8KB, and the size of the storage unit represented by each LBA is 4KB. Fig. 10A ), the size of the storage unit represented by each LBA is 4KB as an example to illustrate the process of releasing the cache unit.

[0111] The data that needs to be moved from the storage device indicated by the NVMe read command is recorded as data 1 to data 6. Fig. 10B As shown, PRP0-PRP3 are PRP entries indicated by NVMe read commands, and the size of the storage block represented by each PRP in PRP0-PRP3 is 8KB. Fig. 10B As shown, data is stored starting from the storage block indicated by PRP0, that is, data 1 is stored in PRP0. Since data 1 is less than 4KB, and the starting address of the required data is not aligned with 8KB, after data 1 is stored in the storage block indicated by PRP0, the storage block indicated by PRP0 also needs to store data 2. Since the sum of data 1 and data 2 is less than 8KB, the storage block indicated by PRP0 can also store part of data 3. Similarly, it can be known that the storage block indicated by PRP1 can store the remaining data of data 3, the complete data 4 and part of data 5, and the storage block represented by PRP2 can store the remaining data of data 5 and data 6.

[0112] For PRP0, since the storage block represented by PRP0 stores part of data 1, data 2, and data 3, after receiving the message that the storage command processing corresponding to data 1 is completed, PRP0 in the cache unit will not be deleted. It is necessary to receive the storage command processing completion message corresponding to data 2 and data 3 before initiating the operation of deleting PRP0 in the cache unit. That is, for PRP0, it is necessary to receive three storage command processing completion messages related to PRP0 before it is deleted from the cache unit. For PRP1, since PRP1 stores part of data 3, data 4, and data 5, it is also necessary to receive three storage command processing completion messages related to PRP1 before it is deleted from the cache unit. For PRP2, since PRP2 only stores part of data 5 and data 6, it is necessary to receive two storage command processing completion messages related to PRP2 before it is deleted from the cache unit.

[0113] Combination Figure 3-10B The embodiment shown, as Fig.11 As shown, the cache unit management method of the storage device in the embodiment of the present application includes:

[0114] Step S1101: In response to receiving an IO command, obtain address location information indicated by the IO command and add it to the allocated cache unit. The address location information includes a PRP entry, an SGL descriptor, and a host memory address determined according to the PRP entry or the SGL descriptor. The number of the PRP entry, the SGL descriptor, and the host memory address determined according to the PRP entry or the SGL descriptor can be one or more.

[0115] Step S1102: If the IO command is an NVMe write command, in response to generating a DMA command according to the address location information indicated by the NVMe write command, release the cache unit occupied by the target address location information.

[0116] Step S1103: If the IO command is an NVMe read command, in response to the fact that the address location information indicated by the storage command processing completion message has been used a number of times equal to the expected number of times, release the cache unit occupied by the address location information indicated by the storage command processing completion message; wherein the storage command indicated by the storage command processing completion message is generated based on the NVMe read command.

[0117] Step S1104: If the IO command is an NVMe read command, in response to the fact that the number of times the address location information indicated by the storage command processing completion message has been used is not equal to the expected number of times, the number of times the address location information indicated by the storage command processing completion message has been used is controlled to be increased by one.

[0118] The cache unit management method of the storage device in the embodiment of the present application can promptly release the PRP entry or SGL descriptor corresponding to the IO command in the cache unit, provide a cache unit for the PRP entry or SGL descriptor of other IO commands, and improve cache utilization.

[0119] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application. Obviously, those skilled in the art may make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A cache unit management method for a storage device, characterized in that: include: In response to receiving an IO command, acquiring address location information indicated by the IO command, and adding the address location information to the allocated cache unit; If the IO command is an NVMe write command, in response to generating a DMA command according to the address location information indicated by the NVMe write command, releasing the cache unit occupied by the address location information indicated by the NVMe write command; or, If the IO command is an NVMe read command, in response to the address location information indicated by the storage command processing completion message having been used a number of times equal to the expected number of times, the cache unit occupied by the address location information indicated by the storage command processing completion message is released; wherein the storage command indicated by the storage command processing completion message is generated based on the NVMe read command.

2. The method according to claim 1, characterized in that: The method further comprises: In response to receiving the storage command processing completion message, if the number of times the address location information indicated by the storage command processing completion message has been used is not equal to the expected number of times, the number of times that has been used is controlled to increase by one.

3. The method according to claim 1 or 2, characterized in that: The method further comprises: If the IO command is an NVMe read command, determine one or more data to be moved indicated by the NVMe read command; According to the data amount of the one or more data to be moved and the capacity of the storage block corresponding to the address location information indicated by the NVMe read command, the number of the data to be moved accommodated in the storage block is determined; the number of the data to be moved accommodated in the storage block is the expected number of times the address location information corresponding to the storage block is used.

4. The method according to any one of claims 1 to 3, characterized in that: The address location information includes one or more of the following: a PRP entry, an SGL descriptor, and a host memory address determined according to the PRP entry or the SGL description.

5. A storage device, comprising a host command processing unit, characterized in that: The host command processing unit includes a cache unit, a circuit for writing into the cache unit, and a circuit for releasing the cache unit: The circuit of the write cache unit is used to obtain the address location information indicated by the IO command in response to receiving the IO command, and add the address location information to the allocated cache unit; The circuit for releasing the cache unit is used to, if the IO command is an NVMe write command, in response to generating a DMA command according to the address location information indicated by the NVMe write command, release the cache unit occupied by the address location information indicated by the NVMe write command; or, if the IO command is an NVMe read command, in response to the address location information indicated by the storage command processing completion message having been used the number of times equal to the expected number of times, release the cache unit occupied by the address location information indicated by the storage command processing completion message; wherein the storage command indicated by the storage command processing completion message is generated according to the NVMe read command.

6. The storage device according to claim 5, characterized in that: The address location information includes one or more of the following: a PRP entry, an SGL descriptor, a host memory address determined according to the PRP entry or the SGL description; The circuit of the write cache unit includes a PRP circuit and / or an SGL circuit; The PRP circuit is configured to, in response to receiving an IO command, obtain a PRP entry indicated by the IO command or a host memory address indicated by the PRP entry, and add the PRP entry or the host memory address indicated by the PRP entry to an allocated cache unit; The SGL circuit is used for, in response to receiving an IO command, obtaining an SGL descriptor indicated by the IO command or a host memory address indicated by the SGL descriptor, and adding the SGL descriptor or the host memory address indicated by the SGL descriptor to an allocated cache unit.

7. The storage device according to claim 5 or 6, wherein the host command processing unit comprises a write initiation circuit, and the write initiation circuit comprises a DMA command generation circuit; characterized in that: The DMA command generation circuit includes a circuit for releasing the cache unit, and the DMA command generation circuit generates a DMA command according to the address location information indicated by the NVMe write command, and in response to generating the DMA command, releases the cache unit occupied by the address location information indicated by the NVMe write command.

8. The storage device according to any one of claims 5 to 7, wherein the host command processing unit comprises a read initiation circuit, and the read initiation circuit comprises a completion message processing circuit; characterized in that: The completion message processing circuit includes a circuit for releasing the cache unit. In response to the address location information indicated by the storage command processing completion message having been used a number of times equal to an expected number of times, the completion message processing circuit releases the cache unit occupied by the address location information indicated by the storage command processing completion message; wherein the storage command indicated by the storage command processing completion message is generated based on the NVMe read command.

9. The storage device according to any one of claims 5 to 7, characterized in that: The circuit for releasing the cache unit includes a first memory, a first calculation circuit, a comparison circuit and an address location information deletion circuit; The first memory is used to record the number of times the address location information indicated by the NVMe read command has been used; The first calculation circuit, in response to receiving a storage command processing completion message, calculates an expected number of times the address location information corresponding to the storage command processing completion message is used; The comparison circuit is coupled to the first memory and the first calculation circuit, and is used to compare the number of times the address location information indicated by the storage command processing completion message has been used with the expected number of times, and output a comparison result; The address location information deletion circuit is coupled to the comparison circuit and is used to release the cache unit occupied by the address location information indicated by the storage command processing completion message when the comparison result is that the number of times used is equal to the expected number of times.

10. The storage device according to any one of claims 5 to 7, characterized in that: The circuit of the release cache unit includes: a second memory, a second calculation circuit and a control circuit; The second memory is used to record the number of times the address location information indicated by the NVMe read command has been used; The second calculation circuit calculates the expected number of times the address location information corresponding to the storage command processing completion message is used in response to receiving the storage command processing completion message; The control circuit is coupled to the second memory and the second calculation circuit, and is used to compare the number of times the address location information indicated by the storage command processing completion message has been used with the expected number of times; When the number of times used is equal to the expected number of times, the cache unit occupied by the address location information indicated by the storage command processing completion message is released; when the number of times used is not equal to the expected number of times, the number of times used recorded in the second memory is controlled to be increased by one.

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